diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref')
30 files changed, 3312 insertions, 3325 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index c1fb80fc3..201ee02a7 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -191,7 +191,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index b4ecd43cf..4b4f6933d 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:43:43 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:24 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 274300226500 because target called exit() +Exiting @ tick 271948359500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index e5597cd29..c0f2578f2 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.274300 # Number of seconds simulated -sim_ticks 274300226500 # Number of ticks simulated -final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.271948 # Number of seconds simulated +sim_ticks 271948359500 # Number of ticks simulated +final_tick 271948359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112537 # Simulator instruction rate (inst/s) -host_op_rate 112537 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51289289 # Simulator tick rate (ticks/s) -host_mem_usage 215256 # Number of bytes of host memory used -host_seconds 5348.10 # Real time elapsed on the host +host_inst_rate 167086 # Simulator instruction rate (inst/s) +host_op_rate 167086 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75497413 # Simulator tick rate (ticks/s) +host_mem_usage 219024 # Number of bytes of host memory used +host_seconds 3602.09 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 54720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory -system.physmem.bytes_read::total 5894080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 54720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 54720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3798144 # Number of bytes written to this memory -system.physmem.bytes_written::total 3798144 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 855 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory -system.physmem.num_reads::total 92095 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59346 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59346 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 21288207 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 21487696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199489 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199489 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 13846667 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13846667 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 13846667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 21288207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35334364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1620224 # Number of bytes read from this memory +system.physmem.bytes_read::total 1674048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 57024 # Number of bytes written to this memory +system.physmem.bytes_written::total 57024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25316 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory +system.physmem.num_writes::total 891 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 197920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5957837 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6155757 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197920 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197920 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 209687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 209687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 209687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5957837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6365444 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517577 # DTB read hits +system.cpu.dtb.read_hits 114517207 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520208 # DTB read accesses -system.cpu.dtb.write_hits 39666608 # DTB write hits +system.cpu.dtb.read_accesses 114519838 # DTB read accesses +system.cpu.dtb.write_hits 39661898 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39668910 # DTB write accesses -system.cpu.dtb.data_hits 154184185 # DTB hits +system.cpu.dtb.write_accesses 39664200 # DTB write accesses +system.cpu.dtb.data_hits 154179105 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154189118 # DTB accesses -system.cpu.itb.fetch_hits 25020502 # ITB hits +system.cpu.dtb.data_accesses 154184038 # DTB accesses +system.cpu.itb.fetch_hits 25013413 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25020524 # ITB accesses +system.cpu.itb.fetch_accesses 25013435 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 548600454 # number of cpu cycles simulated +system.cpu.numCycles 543896720 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86318297 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 81372201 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36359139 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52872243 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34320184 # Number of BTB hits +system.cpu.branch_predictor.lookups 86316674 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81371545 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36360802 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 52676212 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34326876 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 64.911534 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36897167 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49421130 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541659172 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 65.165802 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 36904283 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49412391 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541655345 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005514018 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1005510191 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 254972528 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 155051949 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 33760596 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2593556 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36354152 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26193756 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.122091 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412334574 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 254971320 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 155049936 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 33767521 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2588294 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36355815 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26192089 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.124753 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412333421 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 538371184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 538321020 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 412150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59439534 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489160920 # Number of cycles cpu stages are processed. -system.cpu.activity 89.165242 # Percentage of cycles cpu is active +system.cpu.timesIdled 407697 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 54736228 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489160492 # Number of cycles cpu stages are processed. +system.cpu.activity 89.936283 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -114,72 +114,72 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.911513 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.903698 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.911513 # CPI: Total CPI of All Threads -system.cpu.ipc 1.097077 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.903698 # CPI: Total CPI of All Threads +system.cpu.ipc 1.106565 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.097077 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 209725198 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338875256 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.770867 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 237724577 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310875877 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 56.667083 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 206774969 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341825485 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.308641 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 437071966 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111528488 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.329638 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 201598142 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347002312 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.252283 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.106565 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 205017879 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338878841 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.305734 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 233023029 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310873691 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.156750 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 202072445 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341824275 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.847276 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 432365235 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111531485 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.506004 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 196896047 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 347000673 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.799001 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 728.232127 # Cycle average of tags in use -system.cpu.icache.total_refs 25019479 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 728.555018 # Cycle average of tags in use +system.cpu.icache.total_refs 25012389 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29262.548538 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29254.256140 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 728.232127 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355582 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355582 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25019479 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25019479 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25019479 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25019479 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25019479 # number of overall hits -system.cpu.icache.overall_hits::total 25019479 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses -system.cpu.icache.overall_misses::total 1021 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56709500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56709500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56709500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56709500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56709500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56709500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25020500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25020500 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25020500 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25020500 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25020500 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25020500 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 728.555018 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355740 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355740 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25012389 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25012389 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25012389 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25012389 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25012389 # number of overall hits +system.cpu.icache.overall_hits::total 25012389 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses +system.cpu.icache.overall_misses::total 1022 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 56014500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 56014500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 56014500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 56014500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 56014500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 56014500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25013411 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25013411 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25013411 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25013411 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25013411 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25013411 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55543.095005 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55543.095005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55543.095005 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54808.708415 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54808.708415 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54808.708415 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54808.708415 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,70 +188,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45765000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45765000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45765000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45765000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45765000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45765000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45159500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45159500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45159500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45159500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45159500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45159500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53526.315789 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52818.128655 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52818.128655 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.124914 # Cycle average of tags in use -system.cpu.dcache.total_refs 152394215 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.146809 # Cycle average of tags in use +system.cpu.dcache.total_refs 152406141 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.641827 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 267632000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.124914 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999542 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999542 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120509 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120509 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38273706 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38273706 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 152394215 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152394215 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152394215 # number of overall hits -system.cpu.dcache.overall_hits::total 152394215 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393533 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1177615 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1177615 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1571148 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1571148 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1571148 # number of overall misses -system.cpu.dcache.overall_misses::total 1571148 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150462000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8150462000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25247540000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25247540000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33398002000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33398002000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33398002000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33398002000 # number of overall miss cycles +system.cpu.dcache.avg_refs 334.668016 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 260481000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.146809 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999548 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999548 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38285634 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38285634 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 152406141 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152406141 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152406141 # number of overall hits +system.cpu.dcache.overall_hits::total 152406141 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1165687 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1165687 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1559222 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1559222 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1559222 # number of overall misses +system.cpu.dcache.overall_misses::total 1559222 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5944936500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5944936500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18222826500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18222826500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24167763000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24167763000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24167763000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24167763000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data 153965363 system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029850 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029850 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010205 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010205 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010205 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010205 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.000094 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.000094 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21439.553674 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21257.069353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21257.069353 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12006000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3424818500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2777 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 216268 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4323.370544 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15835.992842 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15106.500057 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15106.500057 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15632.692567 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15632.692567 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15499.885841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15499.885841 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10505000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2188634000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2561 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 211460 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4101.913315 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10350.108768 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks -system.cpu.dcache.writebacks::total 408190 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192301 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192301 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923452 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 923452 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115753 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115753 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115753 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115753 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks +system.cpu.dcache.writebacks::total 436902 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911524 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 911524 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1103827 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1103827 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1103827 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1103827 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562095500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562095500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466864500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466864500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028960000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9028960000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028960000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9028960000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2433186000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2433186000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3829787500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3829787500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6262973500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6262973500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6262973500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6262973500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -318,65 +318,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.436650 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17701.436650 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21509.285380 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21509.285380 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12091.446688 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12091.446688 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15068.233771 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15068.233771 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13752.837646 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13752.837646 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13752.837646 # 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Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16057.614667 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 28.392088 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1610.804416 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.490040 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000866 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.049158 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.540064 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 170049 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 170049 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 194106 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33775500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1014700500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1048476000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024551 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40161.117717 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40012.378641 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40037.593227 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40094.805624 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40094.805624 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 01ebbe1c7..53e4b73f0 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index ef914e93c..21003a7f0 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:42:45 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:29 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 134621123500 because target called exit() +Exiting @ tick 133563007500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index aa861e979..38226af10 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.134621 # Number of seconds simulated -sim_ticks 134621123500 # Number of ticks simulated -final_tick 134621123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133563 # Number of seconds simulated +sim_ticks 133563007500 # Number of ticks simulated +final_tick 133563007500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 192359 # Simulator instruction rate (inst/s) -host_op_rate 192359 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45788058 # Simulator tick rate (ticks/s) -host_mem_usage 216172 # Number of bytes of host memory used -host_seconds 2940.09 # Real time elapsed on the host +host_inst_rate 301381 # Simulator instruction rate (inst/s) +host_op_rate 301381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71175252 # Simulator tick rate (ticks/s) +host_mem_usage 220044 # Number of bytes of host memory used +host_seconds 1876.54 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 64128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5873472 # Number of bytes read from this memory -system.physmem.bytes_read::total 5937600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3797952 # Number of bytes written to this memory -system.physmem.bytes_written::total 3797952 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1002 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 91773 # Number of read requests responded to by this memory -system.physmem.num_reads::total 92775 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59343 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59343 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 476359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 43629646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 44106005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 476359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 476359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 28212155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 28212155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 28212155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 476359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 43629646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72318160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1627392 # Number of bytes read from this memory +system.physmem.bytes_read::total 1688512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 58688 # Number of bytes written to this memory +system.physmem.bytes_written::total 58688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 955 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25428 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26383 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 917 # Number of write requests responded to by this memory +system.physmem.num_writes::total 917 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 457612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12184452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12642063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 457612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 457612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 439403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 439403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 439403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 457612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12184452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13081466 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123836708 # DTB read hits -system.cpu.dtb.read_misses 23555 # DTB read misses +system.cpu.dtb.read_hits 123849413 # DTB read hits +system.cpu.dtb.read_misses 20691 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123860263 # DTB read accesses -system.cpu.dtb.write_hits 40831838 # DTB write hits -system.cpu.dtb.write_misses 31545 # DTB write misses +system.cpu.dtb.read_accesses 123870104 # DTB read accesses +system.cpu.dtb.write_hits 40835064 # DTB write hits +system.cpu.dtb.write_misses 30091 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40863383 # DTB write accesses -system.cpu.dtb.data_hits 164668546 # DTB hits -system.cpu.dtb.data_misses 55100 # DTB misses +system.cpu.dtb.write_accesses 40865155 # DTB write accesses +system.cpu.dtb.data_hits 164684477 # DTB hits +system.cpu.dtb.data_misses 50782 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164723646 # DTB accesses -system.cpu.itb.fetch_hits 66483943 # ITB hits -system.cpu.itb.fetch_misses 37 # ITB misses +system.cpu.dtb.data_accesses 164735259 # DTB accesses +system.cpu.itb.fetch_hits 66492910 # ITB hits +system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66483980 # ITB accesses +system.cpu.itb.fetch_accesses 66492948 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,145 +67,145 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 269242248 # number of cpu cycles simulated +system.cpu.numCycles 267126016 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78494350 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72856279 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3049613 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42772936 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41636011 # Number of BTB hits +system.cpu.BPredUnit.lookups 78502606 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72859176 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3048930 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42879233 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41644328 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1626078 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 617 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68428248 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 710832339 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78494350 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43262089 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119193912 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12932117 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 71677823 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1629564 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 215 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68435581 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 710898129 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78502606 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43273892 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119207604 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12936161 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 69569484 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 965 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 66483943 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 942005 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269174552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.640786 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.458790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 914 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 66492910 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 942940 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267090859 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.661634 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.464377 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 149980640 55.72% 55.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10366067 3.85% 59.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11842490 4.40% 63.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10610817 3.94% 67.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6990702 2.60% 70.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2664486 0.99% 71.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3492691 1.30% 72.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3105815 1.15% 73.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70120844 26.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 147883255 55.37% 55.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10367188 3.88% 59.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11844651 4.43% 63.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10612793 3.97% 67.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6990815 2.62% 70.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2667876 1.00% 71.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3494727 1.31% 72.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3104174 1.16% 73.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70125380 26.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269174552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.291538 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.640122 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85707948 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 55913414 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104656914 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13023782 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9872494 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3909156 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 702084562 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4999 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9872494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93982559 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12740757 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2287 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104137265 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 48439190 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 690176100 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 220 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36870562 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5345683 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527299875 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 906867454 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 906864467 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2987 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267090859 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.293879 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.661284 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85625908 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 53897418 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104721883 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12969411 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9876239 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3910148 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1104 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 702131172 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4692 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9876239 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93864195 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11132886 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1433 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104174566 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 48041540 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 690226135 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36911224 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4900299 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527321421 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 906904042 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 906901104 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2938 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63444986 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 171 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 186 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 107659132 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 129005013 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42430995 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14679275 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9584938 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626474820 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 120 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608397310 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 335936 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60222555 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33444580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 103 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269174552 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.260233 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.839356 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 63466532 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 108 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 116 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 106984731 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 129019631 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42434130 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14712304 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9648397 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626510721 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 98 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608418192 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 334492 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60261200 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33473416 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 81 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267090859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.277945 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.835634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54646313 20.30% 20.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 54798689 20.36% 40.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53375432 19.83% 60.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36717503 13.64% 74.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30865027 11.47% 85.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24096775 8.95% 94.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10651297 3.96% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3344645 1.24% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 678871 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52595450 19.69% 19.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54748440 20.50% 40.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53400082 19.99% 60.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36696955 13.74% 73.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30804090 11.53% 85.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24162728 9.05% 94.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10693904 4.00% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3328381 1.25% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 660829 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269174552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267090859 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2904763 73.47% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 634502 16.05% 89.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 414382 10.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2950080 75.40% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 39 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 582636 14.89% 90.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 379789 9.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441013335 72.49% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7329 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441018930 72.49% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7345 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued @@ -228,86 +228,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126118254 20.73% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41258345 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126131577 20.73% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41260299 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608397310 # Type of FU issued -system.cpu.iq.rate 2.259665 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3953686 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006499 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1490254859 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 686699872 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598814509 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3935 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2431 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1728 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 612349032 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1964 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12165746 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 608418192 # Type of FU issued +system.cpu.iq.rate 2.277645 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3912544 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006431 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1488170355 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 686774500 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598832188 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3924 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2359 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1719 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 612328769 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1967 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12182137 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14490971 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33593 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4856 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2979674 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14505589 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 34191 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4885 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2982809 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6726 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 51107 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6785 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 71183 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9872494 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1561922 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 98319 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 670401264 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1688610 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 129005013 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42430995 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 120 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 41033 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13811 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4856 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1345444 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2209649 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3555093 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602577350 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123860441 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5819960 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9876239 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 295412 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 42917 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 670453714 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1691855 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 129019631 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42434130 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 98 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 899 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7278 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4885 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1348504 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2206028 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3554532 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602596052 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 123870207 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5822140 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 43926324 # number of nop insts executed -system.cpu.iew.exec_refs 164740912 # number of memory reference insts executed -system.cpu.iew.exec_branches 67006670 # Number of branches executed -system.cpu.iew.exec_stores 40880471 # Number of stores executed -system.cpu.iew.exec_rate 2.238049 # Inst execution rate -system.cpu.iew.wb_sent 600066569 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598816237 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417486240 # num instructions producing a value -system.cpu.iew.wb_consumers 531487841 # num instructions consuming a value +system.cpu.iew.exec_nop 43942895 # number of nop insts executed +system.cpu.iew.exec_refs 164752686 # number of memory reference insts executed +system.cpu.iew.exec_branches 67005259 # Number of branches executed +system.cpu.iew.exec_stores 40882479 # Number of stores executed +system.cpu.iew.exec_rate 2.255849 # Inst execution rate +system.cpu.iew.wb_sent 600080079 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598833907 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417539542 # num instructions producing a value +system.cpu.iew.wb_consumers 531416482 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.224080 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.785505 # average fanout of values written-back +system.cpu.iew.wb_rate 2.241766 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.785711 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitCommittedOps 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 68396273 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 68437583 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3048532 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259302058 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.321065 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.702332 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3047922 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 257214620 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.339902 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.706449 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 80379492 31.00% 31.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72839999 28.09% 59.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 26734500 10.31% 69.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8121130 3.13% 72.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10288458 3.97% 76.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20405541 7.87% 84.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6352213 2.45% 86.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3556041 1.37% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30624684 11.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 78375558 30.47% 30.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72865724 28.33% 58.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26619590 10.35% 69.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8074736 3.14% 72.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10311668 4.01% 76.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20443429 7.95% 84.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6319286 2.46% 86.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3488714 1.36% 88.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30715915 11.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259302058 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 257214620 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -318,70 +318,70 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 30624684 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 30715915 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 898866221 # The number of ROB reads -system.cpu.rob.rob_writes 1350401622 # The number of ROB writes -system.cpu.timesIdled 2160 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 67696 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 896728862 # The number of ROB reads +system.cpu.rob.rob_writes 1350487768 # The number of ROB writes +system.cpu.timesIdled 758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35157 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.476069 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.476069 # CPI: Total CPI of All Threads -system.cpu.ipc 2.100534 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.100534 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848641681 # number of integer regfile reads -system.cpu.int_regfile_writes 492726607 # number of integer regfile writes -system.cpu.fp_regfile_reads 387 # number of floating regfile reads -system.cpu.fp_regfile_writes 54 # number of floating regfile writes +system.cpu.cpi 0.472328 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.472328 # CPI: Total CPI of All Threads +system.cpu.ipc 2.117175 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.117175 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848664377 # number of integer regfile reads +system.cpu.int_regfile_writes 492741272 # number of integer regfile writes +system.cpu.fp_regfile_reads 384 # number of floating regfile reads +system.cpu.fp_regfile_writes 47 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 49 # number of replacements -system.cpu.icache.tagsinuse 844.563885 # Cycle average of tags in use -system.cpu.icache.total_refs 66482496 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1002 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 66349.796407 # Average number of references to valid blocks. +system.cpu.icache.replacements 44 # number of replacements +system.cpu.icache.tagsinuse 827.496665 # Cycle average of tags in use +system.cpu.icache.total_refs 66491540 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 975 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 68196.451282 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 844.563885 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.412385 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.412385 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66482496 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66482496 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66482496 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66482496 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66482496 # number of overall hits -system.cpu.icache.overall_hits::total 66482496 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1447 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1447 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1447 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1447 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1447 # number of overall misses -system.cpu.icache.overall_misses::total 1447 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50567500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50567500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50567500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50567500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50567500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50567500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66483943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66483943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66483943 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66483943 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66483943 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66483943 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34946.440912 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34946.440912 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34946.440912 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34946.440912 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 827.496665 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.404051 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.404051 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66491540 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66491540 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66491540 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66491540 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66491540 # number of overall hits +system.cpu.icache.overall_hits::total 66491540 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1370 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1370 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1370 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1370 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1370 # number of overall misses +system.cpu.icache.overall_misses::total 1370 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 47830500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 47830500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 47830500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 47830500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 47830500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 47830500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66492910 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66492910 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66492910 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66492910 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66492910 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66492910 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34912.773723 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34912.773723 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34912.773723 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34912.773723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34912.773723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34912.773723 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,293 +390,296 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 445 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 445 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 445 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 445 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 445 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 445 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1002 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1002 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1002 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1002 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1002 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1002 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35750000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 35750000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35750000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 35750000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35750000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 35750000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 395 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 395 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 395 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 395 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34096000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 34096000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35678.642715 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35678.642715 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34970.256410 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34970.256410 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34970.256410 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34970.256410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34970.256410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34970.256410 # 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number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38150562 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 149091370 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 149091370 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 149091370 # number of overall hits -system.cpu.dcache.overall_hits::total 149091370 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 722352 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 722352 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1300759 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1300759 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2023111 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2023111 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2023111 # number of overall misses -system.cpu.dcache.overall_misses::total 2023111 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11755158500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11755158500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19630287922 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19630287922 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 3500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31385446422 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31385446422 # 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Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999456 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 111034129 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 111034129 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 38205852 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 38205852 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 59 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 59 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 149239981 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 149239981 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 149239981 # number of overall hits +system.cpu.dcache.overall_hits::total 149239981 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 620415 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 620415 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1245469 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1245469 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1865884 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1865884 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1865884 # number of overall misses +system.cpu.dcache.overall_misses::total 1865884 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4714177500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4714177500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12635422233 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12635422233 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 7000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 7000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17349599733 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17349599733 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17349599733 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17349599733 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111654544 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111654544 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 151114481 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 151114481 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 151114481 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 151114481 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006469 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.006469 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032971 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032971 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015873 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.015873 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013388 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.013388 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.013388 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.013388 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16273.449094 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16273.449094 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15091.410417 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 15091.410417 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151105865 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151105865 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151105865 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151105865 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005557 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005557 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031570 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.031570 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.032787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.032787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.012348 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.012348 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.012348 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.012348 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7598.426054 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7598.426054 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10145.111788 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10145.111788 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 3500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 3500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15513.457453 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15513.457453 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 678496 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 191500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 100 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6784.960000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17409.090909 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9298.327084 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9298.327084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9298.327084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9298.327084 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 113496 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 187500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4934.608696 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18750 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 415225 # number of writebacks -system.cpu.dcache.writebacks::total 415225 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 512035 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 512035 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1046237 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1046237 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1558272 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1558272 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1558272 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1558272 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210317 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210317 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254522 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254522 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 464839 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 464839 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 464839 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 464839 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1619332500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1619332500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3028681995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3028681995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4648014495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4648014495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4648014495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4648014495 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001883 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003076 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003076 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7699.484588 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7699.484588 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11899.490005 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11899.490005 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 444730 # number of writebacks +system.cpu.dcache.writebacks::total 444730 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 410277 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 410277 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 991041 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 991041 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1401318 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1401318 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1401318 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1401318 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210138 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210138 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254428 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254428 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464566 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464566 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464566 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464566 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 739150000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 739150000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1881373462 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1881373462 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2620523462 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 2620523462 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2620523462 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 2620523462 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006449 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006449 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003074 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003074 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003074 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003074 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3517.450437 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3517.450437 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7394.522073 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7394.522073 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 5640.799073 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 5640.799073 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 5640.799073 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 5640.799073 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74480 # number of replacements -system.cpu.l2cache.tagsinuse 17651.004599 # Cycle average of tags in use -system.cpu.l2cache.total_refs 461925 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90375 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.111203 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 947 # number of replacements +system.cpu.l2cache.tagsinuse 22959.894157 # Cycle average of tags in use +system.cpu.l2cache.total_refs 555227 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23376 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.752011 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15915.661195 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 39.497783 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1695.845621 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.485707 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001205 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.051753 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.538666 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 178382 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 178382 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 415225 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 415225 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 194684 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 194684 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 373066 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 373066 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 373066 # number of overall hits -system.cpu.l2cache.overall_hits::total 373066 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1002 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 31935 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 32937 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 59838 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 59838 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1002 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 91773 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 92775 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1002 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 91773 # number of overall misses -system.cpu.l2cache.overall_misses::total 92775 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 34422500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1098528500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1132951000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2066830500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2066830500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 34422500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3165359000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 3199781500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 34422500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3165359000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 3199781500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1002 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 210317 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 211319 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 415225 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 415225 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254522 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254522 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1002 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 464839 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 465841 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1002 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 464839 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 465841 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # 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number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5242 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21141 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21141 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 955 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25428 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26383 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 955 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25428 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26383 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29726000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 133026000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 162752000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 668424000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 668424000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29726000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 801450000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 831176000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29726000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 801450000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 831176000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020401 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024830 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083092 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083092 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054735 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056672 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.979487 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054735 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056672 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31126.701571 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31030.090973 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31047.691721 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31617.425855 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31617.425855 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31126.701571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31518.404908 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31504.226206 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31126.701571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31518.404908 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31504.226206 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini index f4efff3d6..265a2a956 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout index fcee7bced..be37b32c1 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:42:36 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:37 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 765623032000 because target called exit() +Exiting @ tick 762853846000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 4082e04ad..a7b4a0a92 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.765623 # Number of seconds simulated -sim_ticks 765623032000 # Number of ticks simulated -final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.762854 # Number of seconds simulated +sim_ticks 762853846000 # Number of ticks simulated +final_tick 762853846000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1675799 # Simulator instruction rate (inst/s) -host_op_rate 1675799 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2131786057 # Simulator tick rate (ticks/s) -host_mem_usage 214908 # Number of bytes of host memory used -host_seconds 359.15 # Real time elapsed on the host +host_inst_rate 2331221 # Simulator instruction rate (inst/s) +host_op_rate 2331221 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2954822927 # Simulator tick rate (ticks/s) +host_mem_usage 219024 # Number of bytes of host memory used +host_seconds 258.17 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 50880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5839104 # Number of bytes read from this memory -system.physmem.bytes_read::total 5889984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3797824 # Number of bytes written to this memory -system.physmem.bytes_written::total 3797824 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 795 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 91236 # Number of read requests responded to by this memory -system.physmem.num_reads::total 92031 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59341 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59341 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 66456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 7626604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7693060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 66456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 66456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4960436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4960436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4960436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 66456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 7626604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12653496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1620160 # Number of bytes read from this memory +system.physmem.bytes_read::total 1670272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 56512 # Number of bytes written to this memory +system.physmem.bytes_written::total 56512 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25315 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory +system.physmem.num_writes::total 883 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 65690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2123814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2189505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 65690 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 65690 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 74080 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 74080 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 74080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 65690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2123814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2263584 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 1531246064 # number of cpu cycles simulated +system.cpu.numCycles 1525707692 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 601856964 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 153970296 # nu system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1531246064 # Number of busy cycles +system.cpu.num_busy_cycles 1525707692 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 673.337154 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.359193 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 673.337154 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.328778 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.328778 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 673.359193 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.328789 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.328789 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 795 # n system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses system.cpu.icache.overall_misses::total 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44520000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44520000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44520000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44520000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44520000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44520000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44016000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44016000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44016000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44016000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44016000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44016000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55366.037736 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55366.037736 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55366.037736 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55366.037736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55366.037736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55366.037736 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 795 system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42135000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42135000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42135000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42135000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42135000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.177385 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.170317 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999553 # Average percentage of cache occupancy +system.cpu.dcache.warmup_cycle 571210000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.177385 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999555 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999555 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 455395 # n system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses system.cpu.dcache.overall_misses::total 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4126262000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4126262000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6081180000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6081180000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10207442000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10207442000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10207442000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10207442000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2990372000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2990372000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4448388000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4448388000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7438760000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7438760000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7438760000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7438760000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20504.999205 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23926.299265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22414.479737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22414.479737 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14860.320426 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14860.320426 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17502.106916 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17502.106916 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16334.742367 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16334.742367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16334.742367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16334.742367 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks -system.cpu.dcache.writebacks::total 408190 # number of writebacks +system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks +system.cpu.dcache.writebacks::total 436902 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3522566000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3522566000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5318691000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5318691000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8841257000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8841257000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8841257000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -258,65 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.999205 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20926.299265 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73734 # number of replacements -system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use -system.cpu.l2cache.total_refs 445709 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 903 # number of replacements +system.cpu.l2cache.tagsinuse 22842.001450 # Cycle average of tags in use +system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16101.078831 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 29.487971 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1692.948088 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.491366 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000900 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.051665 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.543931 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 170065 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 170065 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 194094 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 194094 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 364159 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 364159 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 364159 # number of overall hits -system.cpu.l2cache.overall_hits::total 364159 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 31167 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 31962 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 60069 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 60069 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 795 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 91236 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 92031 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses @@ -325,17 +328,17 @@ system.cpu.l2cache.demand_accesses::total 456190 # n system.cpu.l2cache.overall_accesses::cpu.inst 795 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.158207 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236340 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.236340 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.200345 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.201738 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.200345 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.201738 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984906 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020484 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024279 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083383 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083383 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984906 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.055589 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.057209 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984906 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.055589 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.057209 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -355,41 +358,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59341 # number of writebacks -system.cpu.l2cache.writebacks::total 59341 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31167 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 31962 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60069 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 60069 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 795 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 3681240000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158207 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236340 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.201738 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.201738 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 883 # number of writebacks +system.cpu.l2cache.writebacks::total 883 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 783 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4122 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4905 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21193 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 847720000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1012600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1043920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1012600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1043920000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020484 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024279 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083383 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083383 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057209 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.057209 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index c1e9b189c..d26a36061 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 1edb7f5fa..2a1e3a459 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:27:39 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:37:13 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 164248292500 because target called exit() +Exiting @ tick 163291004000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index ed106fd55..4e7834f0d 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164248 # Number of seconds simulated -sim_ticks 164248292500 # Number of ticks simulated -final_tick 164248292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.163291 # Number of seconds simulated +sim_ticks 163291004000 # Number of ticks simulated +final_tick 163291004000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143439 # Simulator instruction rate (inst/s) -host_op_rate 151568 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41328806 # Simulator tick rate (ticks/s) -host_mem_usage 231960 # Number of bytes of host memory used -host_seconds 3974.18 # Real time elapsed on the host -sim_insts 570052728 # Number of instructions simulated -sim_ops 602360935 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 51136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5799296 # Number of bytes read from this memory -system.physmem.bytes_read::total 5850432 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 51136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 51136 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3722112 # Number of bytes written to this memory -system.physmem.bytes_written::total 3722112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 799 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 90614 # Number of read requests responded to by this memory -system.physmem.num_reads::total 91413 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58158 # Number of write requests responded to by this memory -system.physmem.num_writes::total 58158 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 311334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35308105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 35619439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 311334 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 311334 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 22661496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 22661496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 22661496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 311334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35308105 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58280935 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 225808 # Simulator instruction rate (inst/s) +host_op_rate 238605 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64682367 # Simulator tick rate (ticks/s) +host_mem_usage 234804 # Number of bytes of host memory used +host_seconds 2524.51 # Real time elapsed on the host +sim_insts 570052735 # Number of instructions simulated +sim_ops 602360941 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 47872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1770240 # Number of bytes read from this memory +system.physmem.bytes_read::total 1818112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 203264 # Number of bytes written to this memory +system.physmem.bytes_written::total 203264 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 748 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27660 # Number of read requests responded to by this memory +system.physmem.num_reads::total 28408 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 3176 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3176 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 293170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10841014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11134183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 293170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 293170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1244796 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1244796 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1244796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 293170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10841014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12378980 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,141 +77,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 328496586 # number of cpu cycles simulated +system.cpu.numCycles 326582009 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85500889 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80301573 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2363462 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47194810 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46809578 # Number of BTB hits +system.cpu.BPredUnit.lookups 85496783 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80297868 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2361759 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47129611 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46810915 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1441693 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2047 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68928725 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669724193 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85500889 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48251271 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130040939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13471504 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 117632066 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 466 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67495318 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 807242 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 327633093 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.178244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.200456 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1442822 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 939 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68930661 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669745010 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85496783 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48253737 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130048027 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13475244 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 116341672 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 687 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67499108 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 807540 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 326356874 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.186850 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.203825 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 197592366 60.31% 60.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20955363 6.40% 66.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4944852 1.51% 68.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14316797 4.37% 72.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8978717 2.74% 75.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9406752 2.87% 78.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4386482 1.34% 79.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5812411 1.77% 81.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61239353 18.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 196309073 60.15% 60.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20957347 6.42% 66.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4946491 1.52% 68.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14317000 4.39% 72.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8978746 2.75% 75.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9407391 2.88% 78.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4385745 1.34% 79.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5814869 1.78% 81.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61240212 18.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 327633093 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.260279 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.038755 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93122772 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94805335 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108615724 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20060132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11029130 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4785077 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1812 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 705993706 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5866 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11029130 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107405098 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13994903 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53643 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114322395 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80827924 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697209083 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 245 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59229209 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 19383033 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 653 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723812839 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3241314962 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3241314834 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 326356874 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.261793 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.050771 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93064197 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 93574356 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108736934 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19947205 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11034182 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4784985 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1738 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 706036905 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6288 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11034182 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107346412 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13092326 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46822 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114338400 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 80498732 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697255622 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 101 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59224108 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 19051405 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 625 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723858007 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3241539667 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241539539 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627419202 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96393637 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6694 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6687 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169956085 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172904405 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80621547 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21577919 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28225780 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 681971655 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4856 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646826004 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1423990 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79433587 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197870891 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1925 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 327633093 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.974239 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.736392 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627419213 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96438794 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6501 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6457 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169431016 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172916819 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80629893 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21434071 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 27751379 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 682016489 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4774 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646845145 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1424192 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79472523 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197906343 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1840 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 326356874 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.982018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.741007 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68428283 20.89% 20.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 84743637 25.87% 46.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75345420 23.00% 69.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40565003 12.38% 82.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28664322 8.75% 90.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15213545 4.64% 95.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5876273 1.79% 97.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6659013 2.03% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2137597 0.65% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 67525997 20.69% 20.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 84702389 25.95% 46.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 74951613 22.97% 69.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40526195 12.42% 82.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28606192 8.77% 90.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15221367 4.66% 95.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5979021 1.83% 97.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6497584 1.99% 99.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2346516 0.72% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 327633093 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 326356874 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 205009 5.12% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2904405 72.49% 77.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 897167 22.39% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 204976 4.99% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2983992 72.63% 77.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 919347 22.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403920644 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6585 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403923414 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6566 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -239,159 +239,159 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166111461 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76787311 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166112206 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76802956 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646826004 # Type of FU issued -system.cpu.iq.rate 1.969049 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4006581 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006194 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1626715636 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761421594 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638533475 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646845145 # Type of FU issued +system.cpu.iq.rate 1.980651 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4108315 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006351 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1625579635 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761505232 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638567907 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650832565 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650953440 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30420680 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30447417 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23951584 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 127945 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11724 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10400307 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23963996 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 129674 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11684 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10408650 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12832 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12549 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12812 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 13814 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11029130 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 827373 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 62655 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 682042744 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 662438 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172904405 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80621547 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3504 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13090 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6258 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11724 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1313555 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1583724 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2897279 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642671991 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163979527 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4154013 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11034182 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 314683 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 40041 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 682087415 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 655237 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172916819 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80629893 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3420 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 12514 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1466 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11684 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1312850 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1582780 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2895630 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642706502 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163991051 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4138643 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 66233 # number of nop insts executed -system.cpu.iew.exec_refs 239982954 # number of memory reference insts executed -system.cpu.iew.exec_branches 74668739 # Number of branches executed -system.cpu.iew.exec_stores 76003427 # Number of stores executed -system.cpu.iew.exec_rate 1.956404 # Inst execution rate -system.cpu.iew.wb_sent 640027985 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638533491 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420151811 # num instructions producing a value -system.cpu.iew.wb_consumers 654946950 # num instructions consuming a value +system.cpu.iew.exec_nop 66152 # number of nop insts executed +system.cpu.iew.exec_refs 240011876 # number of memory reference insts executed +system.cpu.iew.exec_branches 74666851 # Number of branches executed +system.cpu.iew.exec_stores 76020825 # Number of stores executed +system.cpu.iew.exec_rate 1.967979 # Inst execution rate +system.cpu.iew.wb_sent 640060409 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638567923 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420584081 # num instructions producing a value +system.cpu.iew.wb_consumers 656222195 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.943806 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.641505 # average fanout of values written-back +system.cpu.iew.wb_rate 1.955306 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.640917 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 570052779 # The number of committed instructions -system.cpu.commit.commitCommittedOps 602360986 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 79691237 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2423863 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 316603964 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.902569 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.239613 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 570052786 # The number of committed instructions +system.cpu.commit.commitCommittedOps 602360992 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 79735934 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2934 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2422217 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 315322693 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.910300 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.242360 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 92664555 29.27% 29.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103983968 32.84% 62.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43054287 13.60% 75.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8920631 2.82% 78.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25673085 8.11% 86.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13110941 4.14% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7578873 2.39% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1154724 0.36% 93.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20462900 6.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91618801 29.06% 29.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103774162 32.91% 61.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42992063 13.63% 75.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8898067 2.82% 78.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25658030 8.14% 86.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13146506 4.17% 90.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7589457 2.41% 93.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1157745 0.37% 93.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20487862 6.50% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 316603964 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570052779 # Number of instructions committed -system.cpu.commit.committedOps 602360986 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 315322693 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570052786 # Number of instructions committed +system.cpu.commit.committedOps 602360992 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219174061 # Number of memory references committed -system.cpu.commit.loads 148952821 # Number of loads committed +system.cpu.commit.refs 219174066 # Number of memory references committed +system.cpu.commit.loads 148952823 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828828 # Number of branches committed +system.cpu.commit.branches 70828830 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533523547 # Number of committed integer instructions. +system.cpu.commit.int_insts 533523551 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20462900 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20487862 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 978192675 # The number of ROB reads -system.cpu.rob.rob_writes 1375166180 # The number of ROB writes -system.cpu.timesIdled 37006 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 863493 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570052728 # Number of Instructions Simulated -system.cpu.committedOps 602360935 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570052728 # Number of Instructions Simulated -system.cpu.cpi 0.576256 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.576256 # CPI: Total CPI of All Threads -system.cpu.ipc 1.735338 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.735338 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210352058 # number of integer regfile reads -system.cpu.int_regfile_writes 664199500 # number of integer regfile writes +system.cpu.rob.rob_reads 976931145 # The number of ROB reads +system.cpu.rob.rob_writes 1375260810 # The number of ROB writes +system.cpu.timesIdled 9894 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 225135 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570052735 # Number of Instructions Simulated +system.cpu.committedOps 602360941 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570052735 # Number of Instructions Simulated +system.cpu.cpi 0.572898 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.572898 # CPI: Total CPI of All Threads +system.cpu.ipc 1.745512 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.745512 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210543463 # number of integer regfile reads +system.cpu.int_regfile_writes 664223214 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 905055598 # number of misc regfile reads -system.cpu.misc_regfile_writes 3110 # number of misc regfile writes -system.cpu.icache.replacements 66 # number of replacements -system.cpu.icache.tagsinuse 704.852693 # Cycle average of tags in use -system.cpu.icache.total_refs 67494169 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 836 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 80734.651914 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 905101471 # number of misc regfile reads +system.cpu.misc_regfile_writes 3116 # number of misc regfile writes +system.cpu.icache.replacements 67 # number of replacements +system.cpu.icache.tagsinuse 689.277263 # Cycle average of tags in use +system.cpu.icache.total_refs 67498009 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 823 # 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average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34196.692776 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34196.692776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34196.692776 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 689.277263 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.336561 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.336561 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67498009 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67498009 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67498009 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67498009 # 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average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17259.271740 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17259.271740 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12687.500000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12687.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16703.549355 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16703.549355 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9569014 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1705 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1705 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1557 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1557 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201716410 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201716410 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201716410 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201716410 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001726 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001726 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018592 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.018592 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012903 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012903 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007530 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007530 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007530 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007530 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7179.592820 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 7179.592820 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9552.873883 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9552.873883 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 7636.363636 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 7636.363636 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9196.023814 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9196.023814 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9196.023814 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9196.023814 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9916851 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2180 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2339 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4389.455963 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4239.782386 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 394908 # number of writebacks -system.cpu.dcache.writebacks::total 394908 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51828 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51828 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1320801 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1320801 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 16 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 16 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1372629 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1372629 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23297500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 869866000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 893163500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23297500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 869866000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 893163500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.908870 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027802 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031459 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089712 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089712 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.908870 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063779 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.908870 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062215 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063779 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31146.390374 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31202.367942 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31195.655659 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31509.472260 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31509.472260 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31146.390374 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31448.517715 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31440.562518 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31146.390374 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31448.517715 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31440.562518 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini index c0d4f8993..ad449ce69 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout index 3264273f7..2afc8e322 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:27:49 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:38:20 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 301191370000 because target called exit() +Exiting @ tick 301191365000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index ab951a1c0..d2a90d0bb 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.301191 # Number of seconds simulated -sim_ticks 301191370000 # Number of ticks simulated -final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 301191365000 # Number of ticks simulated +final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2291609 # Simulator instruction rate (inst/s) -host_op_rate 2421488 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1210789798 # Simulator tick rate (ticks/s) -host_mem_usage 221260 # Number of bytes of host memory used -host_seconds 248.76 # Real time elapsed on the host -sim_insts 570051644 # Number of instructions simulated -sim_ops 602359851 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 2280298136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 399862021 # Number of bytes read from this memory -system.physmem.bytes_read::total 2680160157 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2280298136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2280298136 # Number of instructions bytes read from this memory +host_inst_rate 3330708 # Simulator instruction rate (inst/s) +host_op_rate 3519478 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1759805795 # Simulator tick rate (ticks/s) +host_mem_usage 224176 # Number of bytes of host memory used +host_seconds 171.15 # Real time elapsed on the host +sim_insts 570051636 # Number of instructions simulated +sim_ops 602359842 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 399862020 # Number of bytes read from this memory +system.physmem.bytes_read::total 2680160120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2280298100 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2280298100 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 236359611 # Number of bytes written to this memory system.physmem.bytes_written::total 236359611 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 570074534 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147793179 # Number of read requests responded to by this memory -system.physmem.num_reads::total 717867713 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 570074525 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147793178 # Number of read requests responded to by this memory +system.physmem.num_reads::total 717867703 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 69418858 # Number of write requests responded to by this memory system.physmem.num_writes::total 69418858 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7570927866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1327601189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8898529055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7570927866 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7570927866 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 784748949 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 784748949 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7570927866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2112350138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9683278004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7570927872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1327601208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8898529080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7570927872 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7570927872 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 784748962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 784748962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7570927872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2112350170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9683278042 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 602382741 # number of cpu cycles simulated +system.cpu.numCycles 602382731 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 570051644 # Number of instructions committed -system.cpu.committedOps 602359851 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses +system.cpu.committedInsts 570051636 # Number of instructions committed +system.cpu.committedOps 602359842 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 1993546 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls -system.cpu.num_int_insts 533522639 # number of integer instructions +system.cpu.num_func_calls 1995305 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 67017094 # number of instructions that are conditional controls +system.cpu.num_int_insts 533522631 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2770243005 # number of times the integer registers were read -system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written +system.cpu.num_int_register_reads 2770242967 # number of times the integer registers were read +system.cpu.num_int_register_writes 614470972 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 219173607 # number of memory refs -system.cpu.num_load_insts 148952594 # Number of load instructions +system.cpu.num_mem_refs 219173606 # number of memory refs +system.cpu.num_load_insts 148952593 # Number of load instructions system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 602382741 # Number of busy cycles +system.cpu.num_busy_cycles 602382731 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini index 81852cb71..02db72141 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout index dd5e622ba..b63306c7d 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:27:51 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:38:23 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 796762926000 because target called exit() +Exiting @ tick 794147534000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 44a2387d1..759b7639a 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.796763 # Number of seconds simulated -sim_ticks 796762926000 # Number of ticks simulated -final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.794148 # Number of seconds simulated +sim_ticks 794147534000 # Number of ticks simulated +final_tick 794147534000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1154549 # Simulator instruction rate (inst/s) -host_op_rate 1219245 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1618008338 # Simulator tick rate (ticks/s) -host_mem_usage 230404 # Number of bytes of host memory used -host_seconds 492.43 # Real time elapsed on the host -sim_insts 568539343 # Number of instructions simulated -sim_ops 600398281 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5720064 # Number of bytes read from this memory -system.physmem.bytes_read::total 5759488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3704704 # Number of bytes written to this memory -system.physmem.bytes_written::total 3704704 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 89376 # Number of read requests responded to by this memory -system.physmem.num_reads::total 89992 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57886 # Number of write requests responded to by this memory -system.physmem.num_writes::total 57886 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 49480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 7179129 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7228609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 49480 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 49480 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4649694 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4649694 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4649694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 49480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 7179129 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11878304 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 1549107 # Simulator instruction rate (inst/s) +host_op_rate 1635914 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2163825213 # Simulator tick rate (ticks/s) +host_mem_usage 232760 # Number of bytes of host memory used +host_seconds 367.01 # Real time elapsed on the host +sim_insts 568539335 # Number of instructions simulated +sim_ops 600398272 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1735040 # Number of bytes read from this memory +system.physmem.bytes_read::total 1774144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 39104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 39104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 194752 # Number of bytes written to this memory +system.physmem.bytes_written::total 194752 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 611 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27721 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 3043 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3043 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 49240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2184783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2234023 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 49240 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 49240 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 245234 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 245234 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 245234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 49240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2184783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2479257 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,73 +77,73 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1593525852 # number of cpu cycles simulated +system.cpu.numCycles 1588295068 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 568539343 # Number of instructions committed -system.cpu.committedOps 600398281 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses +system.cpu.committedInsts 568539335 # Number of instructions committed +system.cpu.committedOps 600398272 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 1993546 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls -system.cpu.num_int_insts 533522639 # number of integer instructions +system.cpu.num_func_calls 1995305 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 67017094 # number of instructions that are conditional controls +system.cpu.num_int_insts 533522631 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read -system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written +system.cpu.num_int_register_reads 3212467067 # number of times the integer registers were read +system.cpu.num_int_register_writes 614470972 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 219173607 # number of memory refs -system.cpu.num_load_insts 148952594 # Number of load instructions +system.cpu.num_mem_refs 219173606 # number of memory refs +system.cpu.num_load_insts 148952593 # Number of load instructions system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1593525852 # Number of busy cycles +system.cpu.num_busy_cycles 1588295068 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 12 # number of replacements -system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use -system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 577.753136 # Cycle average of tags in use +system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 577.728532 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.282094 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.282094 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 570073892 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 570073892 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 570073892 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 570073892 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 570073892 # number of overall hits -system.cpu.icache.overall_hits::total 570073892 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 577.753136 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.282106 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.282106 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 570073883 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 570073883 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 570073883 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 570073883 # number of overall hits +system.cpu.icache.overall_hits::total 570073883 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 643 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 643 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 643 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses system.cpu.icache.overall_misses::total 643 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34874000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34874000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34874000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34874000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34874000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34874000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 570074535 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 570074535 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 570074535 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 570074535 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 570074535 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 570074535 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34664000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34664000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34664000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34664000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34664000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34664000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 570074526 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 570074526 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 570074526 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54236.391913 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54236.391913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54236.391913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54236.391913 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53909.797823 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53909.797823 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53909.797823 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53909.797823 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53909.797823 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53909.797823 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,46 +158,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 643 system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32945000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32945000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32735000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32735000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32735000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32735000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32735000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32735000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51236.391913 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51236.391913 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50909.797823 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50909.797823 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 433468 # number of replacements -system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use -system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.217417 # Cycle average of tags in use +system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.222434 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999566 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999566 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 147602036 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147602036 # number of ReadReq hits +system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 536853000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.217417 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999565 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999565 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 216771819 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 216771819 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 216771819 # number of overall hits -system.cpu.dcache.overall_hits::total 216771819 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 216771818 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 216771818 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 216771818 # number of overall hits +system.cpu.dcache.overall_hits::total 216771818 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 437564 # n system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses system.cpu.dcache.overall_misses::total 437564 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3956274000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3956274000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5923414000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5923414000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9879688000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9879688000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9879688000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9879688000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 147791852 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 147791852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2865114000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2865114000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4399402000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4399402000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7264516000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7264516000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7264516000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7264516000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 217209383 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 217209383 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 217209383 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 217209383 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 217209382 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 217209382 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 217209382 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 217209382 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20842.679226 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20842.679226 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23909.028529 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23909.028529 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22578.841038 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22578.841038 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15094.164875 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15094.164875 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17757.568174 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17757.568174 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16602.179338 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16602.179338 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16602.179338 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16602.179338 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 392392 # number of writebacks -system.cpu.dcache.writebacks::total 392392 # number of writebacks +system.cpu.dcache.writebacks::writebacks 418219 # number of writebacks +system.cpu.dcache.writebacks::total 418219 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 437564 system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386826000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386826000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5180170000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5180170000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8566996000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8566996000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8566996000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8566996000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2295666000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2295666000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3656158000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3656158000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5951824000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5951824000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5951824000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5951824000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17842.679226 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17842.679226 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20909.028529 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20909.028529 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12094.164875 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12094.164875 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14757.568174 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14757.568174 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13602.179338 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13602.179338 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13602.179338 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13602.179338 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 71804 # number of replacements -system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use -system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 3963 # number of replacements +system.cpu.l2cache.tagsinuse 21581.956920 # Cycle average of tags in use +system.cpu.l2cache.total_refs 495400 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24559 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 20.171831 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16141.835335 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 24.672100 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1737.507245 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.492610 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000753 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.053025 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.546387 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 158891 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 158918 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 392392 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 392392 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 189297 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 189297 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 348188 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 348215 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 348188 # number of overall hits -system.cpu.l2cache.overall_hits::total 348215 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 30925 # 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Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.015539 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.658629 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 184871 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 184903 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 418219 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 418219 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 225583 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 225583 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 410454 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 410486 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 410454 # number of overall hits +system.cpu.l2cache.overall_hits::total 410486 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 611 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4945 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5556 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 22165 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 22165 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 611 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 27110 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27721 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 611 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 27110 # number of overall misses +system.cpu.l2cache.overall_misses::total 27721 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31772000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 257140000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 288912000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1152580000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1152580000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 31772000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1409720000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1441492000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 31772000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1409720000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1441492000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 392392 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 392392 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 418219 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 418219 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses @@ -346,17 +346,17 @@ system.cpu.l2cache.demand_accesses::total 438207 # n system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958009 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.165605 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235929 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.235929 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958009 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.204258 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.205364 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958009 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.204258 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.205364 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.950233 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026052 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.029172 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089466 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.089466 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.950233 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.061957 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063260 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.950233 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.061957 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063260 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -376,41 +376,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57886 # number of writebacks -system.cpu.l2cache.writebacks::total 57886 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30925 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 31541 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58451 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 58451 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 89376 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 89992 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 89376 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 89992 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1237000000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1261640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2338040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2338040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3575040000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 3599680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3575040000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 3599680000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165605 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235929 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235929 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.205364 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.205364 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 3043 # number of writebacks +system.cpu.l2cache.writebacks::total 3043 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 611 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4945 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5556 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22165 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 22165 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 611 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 27110 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27721 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 611 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 27110 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27721 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24440000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 197800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 886600000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 886600000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1084400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1108840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24440000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1084400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1108840000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026052 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.029172 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089466 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089466 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063260 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063260 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index 6dd839e0e..3fe84dba1 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing +cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index b261460cd..476c2fbae 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:35 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:22 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 388554296500 because target called exit() +Exiting @ tick 387353399000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 042ffd7cf..aefb16cc5 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,174 +1,173 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.388554 # Number of seconds simulated -sim_ticks 388554296500 # Number of ticks simulated -final_tick 388554296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387353 # Number of seconds simulated +sim_ticks 387353399000 # Number of ticks simulated +final_tick 387353399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160259 # Simulator instruction rate (inst/s) -host_op_rate 160764 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44440455 # Simulator tick rate (ticks/s) -host_mem_usage 224388 # Number of bytes of host memory used -host_seconds 8743.26 # Real time elapsed on the host +host_inst_rate 249730 # Simulator instruction rate (inst/s) +host_op_rate 250517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69036992 # Simulator tick rate (ticks/s) +host_mem_usage 223172 # Number of bytes of host memory used +host_seconds 5610.81 # Real time elapsed on the host sim_insts 1401188958 # Number of instructions simulated sim_ops 1405604152 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 85056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5902400 # Number of bytes read from this memory -system.physmem.bytes_read::total 5987456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 85056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 85056 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3788160 # Number of bytes written to this memory -system.physmem.bytes_written::total 3788160 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1329 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 92225 # Number of read requests responded to by this memory -system.physmem.num_reads::total 93554 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59190 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59190 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 218904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15190670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15409574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 218904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 218904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 9749371 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 9749371 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 9749371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 218904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15190670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 25158945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 78784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1679296 # Number of bytes read from this memory +system.physmem.bytes_read::total 1758080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 78784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 78784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 163648 # Number of bytes written to this memory +system.physmem.bytes_written::total 163648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26239 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27470 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2557 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2557 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 203390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4335307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4538698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 203390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 203390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 422477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 422477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 422477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 203390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4335307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4961175 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 777108594 # number of cpu cycles simulated +system.cpu.numCycles 774706799 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98192290 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88412741 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3784661 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 66025458 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65664289 # Number of BTB hits +system.cpu.BPredUnit.lookups 98185703 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88410338 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3780922 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 66067142 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65660680 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1392 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 307 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 165888791 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648818264 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98192290 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65665681 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330417282 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21685615 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 262756820 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 127 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2717 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 162823525 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 752138 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 776762747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.128564 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.147845 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1350 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 222 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 165873006 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648740209 # Number of instructions fetch has processed +system.cpu.fetch.Branches 98185703 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65662030 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330401804 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21677633 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 260655576 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 134 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2710 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 162813671 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 754240 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774625436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.134374 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.150186 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 446345465 57.46% 57.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74375625 9.58% 67.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37980087 4.89% 71.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9083330 1.17% 73.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28159964 3.63% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18826619 2.42% 79.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11515688 1.48% 80.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3871202 0.50% 81.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146604767 18.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 444223632 57.35% 57.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74371089 9.60% 66.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37975725 4.90% 71.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9081691 1.17% 73.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28157593 3.63% 76.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18825345 2.43% 79.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11518334 1.49% 80.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3870567 0.50% 81.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146601460 18.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 776762747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126356 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.121735 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 217443439 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 213446803 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285373546 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42801949 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17697010 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1642584513 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17697010 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 241484414 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36505924 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52170824 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303041095 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 125863480 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1631270043 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30873302 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 72930971 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3136079 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1360952247 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2755876290 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2721902713 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33973577 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774625436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126739 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.128212 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 217582243 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 211191171 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285367331 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42792485 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17692206 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1642537043 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17692206 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 241610870 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34893000 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 51906533 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303032306 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 125490521 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1631238728 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 30863889 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 72608286 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3100712 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1360952696 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2755863339 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2721765470 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34097869 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 116181795 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2680713 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2696169 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271856221 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 438705092 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 180250261 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 255265663 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83296081 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1517040384 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2636529 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1460865188 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 67073 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 113729678 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 136677669 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 392858 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 776762747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.880710 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.430803 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 116182244 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2679261 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2694678 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271420357 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 438695813 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 180248477 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 255317958 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83005231 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1517026367 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2634412 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1460842230 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 78451 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 113716292 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 136734652 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 390741 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774625436 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.885869 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.429732 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147116911 18.94% 18.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184456460 23.75% 42.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210881862 27.15% 69.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131212379 16.89% 86.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70768732 9.11% 95.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20345025 2.62% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7834706 1.01% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3973798 0.51% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 172874 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145113160 18.73% 18.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184290714 23.79% 42.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210981910 27.24% 69.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131056815 16.92% 86.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70797961 9.14% 95.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20401058 2.63% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7831654 1.01% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3987119 0.51% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 165045 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 776762747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774625436 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 106719 6.05% 6.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 167382 9.50% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1159607 65.79% 81.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 328958 18.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 85311 4.91% 4.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 160602 9.25% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1164457 67.05% 81.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326416 18.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 867175983 59.36% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 867158495 59.36% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2649316 0.18% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2649765 0.18% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued @@ -194,86 +193,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419771639 28.73% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171268250 11.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419768740 28.73% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171265230 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1460865188 # Type of FU issued -system.cpu.iq.rate 1.879873 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1762666 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3682454836 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1624473314 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1444449939 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17868026 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9170759 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8547404 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453439561 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9188293 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215395742 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1460842230 # Type of FU issued +system.cpu.iq.rate 1.885671 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1736786 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001189 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3680238914 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1624378157 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1444420049 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17886219 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9235235 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8548145 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1453389871 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9189145 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215326368 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36192248 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 54154 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 246172 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13402119 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36182969 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 54134 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 244807 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13400335 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3683 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 46778 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3669 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 64278 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17697010 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2543877 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 131664 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1613864484 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4125995 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 438705092 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 180250261 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2550339 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 45235 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 9141 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 246172 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2357197 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1561193 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3918390 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1455317466 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 417050361 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5547722 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17692206 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 786779 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 100697 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1613841065 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4120499 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 438695813 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 180248477 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2548675 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 22528 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11302 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 244807 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2356307 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1558704 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3915011 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1455294659 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 417049506 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5547571 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 94187571 # number of nop insts executed -system.cpu.iew.exec_refs 587627055 # number of memory reference insts executed -system.cpu.iew.exec_branches 89112581 # Number of branches executed -system.cpu.iew.exec_stores 170576694 # Number of stores executed -system.cpu.iew.exec_rate 1.872734 # Inst execution rate -system.cpu.iew.wb_sent 1453915806 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1452997343 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154378236 # num instructions producing a value -system.cpu.iew.wb_consumers 1205398776 # num instructions consuming a value +system.cpu.iew.exec_nop 94180286 # number of nop insts executed +system.cpu.iew.exec_refs 587622925 # number of memory reference insts executed +system.cpu.iew.exec_branches 89107301 # Number of branches executed +system.cpu.iew.exec_stores 170573419 # Number of stores executed +system.cpu.iew.exec_rate 1.878510 # Inst execution rate +system.cpu.iew.wb_sent 1453892295 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1452968194 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1154379658 # num instructions producing a value +system.cpu.iew.wb_consumers 1205415324 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.869748 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957673 # average fanout of values written-back +system.cpu.iew.wb_rate 1.875507 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957661 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 124237250 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 124212585 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3784661 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 759066348 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.962310 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.504596 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3780922 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 756933841 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.967838 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.506392 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 240497837 31.68% 31.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276436046 36.42% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43137006 5.68% 73.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54981228 7.24% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19702278 2.60% 83.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13356697 1.76% 85.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30450827 4.01% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10463438 1.38% 90.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70040991 9.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 238474723 31.51% 31.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276385043 36.51% 68.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43107077 5.69% 73.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54927770 7.26% 80.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19677668 2.60% 83.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13341628 1.76% 85.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30470034 4.03% 89.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10497412 1.39% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70052486 9.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 759066348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 756933841 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108101 # Number of instructions committed system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -284,70 +283,70 @@ system.cpu.commit.branches 86248929 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70040991 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70052486 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2302721032 # The number of ROB reads -system.cpu.rob.rob_writes 3245242057 # The number of ROB writes -system.cpu.timesIdled 11126 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 345847 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2300552365 # The number of ROB reads +system.cpu.rob.rob_writes 3245186964 # The number of ROB writes +system.cpu.timesIdled 3424 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 81363 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188958 # Number of Instructions Simulated system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated -system.cpu.cpi 0.554607 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.554607 # CPI: Total CPI of All Threads -system.cpu.ipc 1.803080 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.803080 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1980619731 # number of integer regfile reads -system.cpu.int_regfile_writes 1276281052 # number of integer regfile writes -system.cpu.fp_regfile_reads 16978878 # number of floating regfile reads -system.cpu.fp_regfile_writes 10499994 # number of floating regfile writes -system.cpu.misc_regfile_reads 593300909 # number of misc regfile reads +system.cpu.cpi 0.552892 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552892 # CPI: Total CPI of All Threads +system.cpu.ipc 1.808670 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.808670 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1980590719 # number of integer regfile reads +system.cpu.int_regfile_writes 1276263729 # number of integer regfile writes +system.cpu.fp_regfile_reads 16980710 # number of floating regfile reads +system.cpu.fp_regfile_writes 10502370 # number of floating regfile writes +system.cpu.misc_regfile_reads 593296241 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 200 # number of replacements -system.cpu.icache.tagsinuse 1048.828471 # Cycle average of tags in use -system.cpu.icache.total_refs 162821549 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 120519.281273 # Average number of references to valid blocks. +system.cpu.icache.replacements 213 # number of replacements +system.cpu.icache.tagsinuse 1045.821443 # Cycle average of tags in use +system.cpu.icache.total_refs 162811755 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1361 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 119626.565026 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1048.828471 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.512123 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.512123 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 162821549 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 162821549 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 162821549 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 162821549 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 162821549 # number of overall hits -system.cpu.icache.overall_hits::total 162821549 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1976 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1976 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1976 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1976 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1976 # number of overall misses -system.cpu.icache.overall_misses::total 1976 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 67232500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 67232500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 67232500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 67232500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 67232500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 67232500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162823525 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162823525 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162823525 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162823525 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162823525 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162823525 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1045.821443 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.510655 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.510655 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 162811755 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 162811755 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 162811755 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 162811755 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 162811755 # number of overall hits +system.cpu.icache.overall_hits::total 162811755 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1916 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1916 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1916 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1916 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1916 # number of overall misses +system.cpu.icache.overall_misses::total 1916 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62211500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62211500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62211500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62211500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62211500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62211500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162813671 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162813671 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162813671 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162813671 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162813671 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162813671 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.544534 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34024.544534 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34024.544534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34024.544534 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32469.467641 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 32469.467641 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 32469.467641 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 32469.467641 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 32469.467641 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 32469.467641 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -356,144 +355,144 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 624 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 624 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 624 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 624 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 624 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 624 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1352 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1352 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1352 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1352 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1352 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1352 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47023000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47023000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47023000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47023000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47023000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47023000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 554 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 554 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 554 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 554 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 554 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 554 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1362 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1362 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1362 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1362 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1362 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1362 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43838000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43838000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43838000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43838000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43838000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43838000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34780.325444 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34780.325444 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32186.490455 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32186.490455 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32186.490455 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 32186.490455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32186.490455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 32186.490455 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 458031 # number of replacements -system.cpu.dcache.tagsinuse 4095.115790 # Cycle average of tags in use -system.cpu.dcache.total_refs 365778673 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 462127 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 791.511150 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 131565000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.115790 # Average occupied blocks per requestor +system.cpu.dcache.replacements 458023 # number of replacements +system.cpu.dcache.tagsinuse 4095.115270 # Cycle average of tags in use +system.cpu.dcache.total_refs 365885511 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 462119 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 791.756043 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 131340000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.115270 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999784 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999784 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200803152 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200803152 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164974202 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164974202 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 200904892 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200904892 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164979300 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164979300 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365777354 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365777354 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365777354 # number of overall hits -system.cpu.dcache.overall_hits::total 365777354 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 803342 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 803342 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1872614 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1872614 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365884192 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365884192 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365884192 # number of overall hits +system.cpu.dcache.overall_hits::total 365884192 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 767087 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 767087 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1867516 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1867516 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2675956 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2675956 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2675956 # number of overall misses -system.cpu.dcache.overall_misses::total 2675956 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11885207000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11885207000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 29671016952 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 29671016952 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 267000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 267000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41556223952 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41556223952 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41556223952 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41556223952 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201606494 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201606494 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2634603 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2634603 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2634603 # number of overall misses +system.cpu.dcache.overall_misses::total 2634603 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5082670000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5082670000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23201861832 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23201861832 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 69000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 69000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28284531832 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28284531832 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28284531832 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28284531832 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201671979 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201671979 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 368453310 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 368453310 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 368453310 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 368453310 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003985 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003985 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011224 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011224 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368518795 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368518795 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368518795 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368518795 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003804 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003804 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011193 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011193 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007263 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007263 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007263 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007263 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.703875 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14794.703875 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15844.705290 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 15844.705290 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38142.857143 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 38142.857143 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15529.487014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15529.487014 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.007149 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007149 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007149 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007149 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6625.936823 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 6625.936823 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12423.915957 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12423.915957 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 9857.142857 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 9857.142857 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10735.785176 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10735.785176 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10735.785176 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10735.785176 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2214.285714 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 413195 # number of writebacks -system.cpu.dcache.writebacks::total 413195 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 603294 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 603294 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1610542 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1610542 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2213836 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2213836 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2213836 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2213836 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200048 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200048 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262072 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262072 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 442952 # number of writebacks +system.cpu.dcache.writebacks::total 442952 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 567019 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 567019 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1605472 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1605472 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2172491 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2172491 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2172491 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2172491 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200068 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200068 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262044 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262044 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 462120 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 462120 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 462120 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 462120 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1554226000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1554226000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3602715222 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3602715222 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 246000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 246000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5156941222 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5156941222 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5156941222 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5156941222 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 462112 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 462112 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 462112 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 462112 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 667617500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 667617500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2577100353 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2577100353 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 48000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 48000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3244717853 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3244717853 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3244717853 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3244717853 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses @@ -504,100 +503,100 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 system.cpu.dcache.demand_mshr_miss_rate::total 0.001254 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7769.265376 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7769.265376 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13747.043644 # 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average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9834.609276 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 6857.142857 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 6857.142857 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7021.496635 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7021.496635 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7021.496635 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7021.496635 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 75325 # number of replacements -system.cpu.l2cache.tagsinuse 17833.274372 # Cycle average of tags in use -system.cpu.l2cache.total_refs 440162 # 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number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5670 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21800 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21800 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1231 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26239 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27470 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1231 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26239 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27470 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38155500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 137662500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175818000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 681082000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 681082000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38155500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 818744500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 856900000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38155500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 818744500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 856900000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.903818 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022188 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028149 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083190 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083190 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.903818 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056780 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059269 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.903818 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056780 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059269 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30995.532088 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31012.052264 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31008.465608 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31242.293578 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31242.293578 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30995.532088 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31203.342353 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31194.029851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30995.532088 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31203.342353 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31194.029851 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini index 577b4c1d7..e273f1b51 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing +cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout index 4517a277e..a6ed8a59a 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:45 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:27 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2064258667000 because target called exit() +Exiting @ tick 2061521023000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 0ce23ef70..921624c02 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.064259 # Number of seconds simulated -sim_ticks 2064258667000 # Number of ticks simulated -final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.061521 # Number of seconds simulated +sim_ticks 2061521023000 # Number of ticks simulated +final_tick 2061521023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1371910 # Simulator instruction rate (inst/s) -host_op_rate 1375988 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1906915769 # Simulator tick rate (ticks/s) -host_mem_usage 223048 # Number of bytes of host memory used -host_seconds 1082.51 # Real time elapsed on the host +host_inst_rate 2065708 # Simulator instruction rate (inst/s) +host_op_rate 2071849 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2867468443 # Simulator tick rate (ticks/s) +host_mem_usage 221124 # Number of bytes of host memory used +host_seconds 718.93 # Real time elapsed on the host sim_insts 1485108101 # Number of instructions simulated sim_ops 1489523295 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 70592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory -system.physmem.bytes_read::total 5909952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 70592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 70592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3778240 # Number of bytes written to this memory -system.physmem.bytes_written::total 3778240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1103 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory -system.physmem.num_reads::total 92343 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59035 # Number of write requests responded to by this memory -system.physmem.num_writes::total 59035 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 34197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2828793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2862990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 34197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 34197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1830313 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1830313 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1830313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 34197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2828793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4693303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1672576 # Number of bytes read from this memory +system.physmem.bytes_read::total 1738304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 161472 # Number of bytes written to this memory +system.physmem.bytes_written::total 161472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1027 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27161 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2523 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2523 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 31883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 811331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 843214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 31883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 31883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 78327 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 78327 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 78327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 31883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 811331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 921541 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 4128517334 # number of cpu cycles simulated +system.cpu.numCycles 4123042046 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1485108101 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 569365767 # nu system.cpu.num_load_insts 402515346 # Number of load instructions system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4128517334 # Number of busy cycles +system.cpu.num_busy_cycles 4123042046 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 118 # number of replacements -system.cpu.icache.tagsinuse 906.450625 # Cycle average of tags in use +system.cpu.icache.tagsinuse 906.456939 # Cycle average of tags in use system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 906.450625 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.442603 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.442603 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 906.456939 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.442606 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.442606 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 1107 # n system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses system.cpu.icache.overall_misses::total 1107 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 61824000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 61824000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 61824000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 61824000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 61824000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 61824000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58632000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58632000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58632000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58632000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58632000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58632000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55848.238482 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55848.238482 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55848.238482 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55848.238482 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52964.769648 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52964.769648 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52964.769648 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52964.769648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52964.769648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52964.769648 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,32 +116,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1107 system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58503000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 58503000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58503000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 58503000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58503000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 58503000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55311000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 55311000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55311000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 55311000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55311000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 55311000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52848.238482 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52848.238482 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49964.769648 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49964.769648 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49964.769648 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49964.769648 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49964.769648 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49964.769648 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements -system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.226004 # Cycle average of tags in use system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.226955 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 566952000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.226004 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999811 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999811 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits @@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 453214 # n system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses system.cpu.dcache.overall_misses::total 453214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4019834000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4019834000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6156948000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6156948000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 392000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 392000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10176782000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10176782000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10176782000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10176782000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2888312000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2888312000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4554270000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4554270000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 140000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 140000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7442582000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7442582000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7442582000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7442582000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) @@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20775.839079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20775.839079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23705.368693 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23705.368693 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22454.694692 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22454.694692 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14927.757047 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14927.757047 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17534.767141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17534.767141 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 20000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 20000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16421.783087 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16421.783087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16421.783087 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16421.783087 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,8 +212,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 407009 # number of writebacks -system.cpu.dcache.writebacks::total 407009 # number of writebacks +system.cpu.dcache.writebacks::writebacks 435341 # number of writebacks +system.cpu.dcache.writebacks::total 435341 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses @@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 453214 system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3439376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3439376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5377764000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5377764000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 371000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 371000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8817140000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8817140000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8817140000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8817140000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082940000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6082940000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082940000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6082940000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses @@ -244,70 +244,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17775.839079 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20705.368693 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20705.368693 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.767141 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.767141 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74112 # number of replacements -system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use -system.cpu.l2cache.total_refs 427085 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2614 # number of replacements +system.cpu.l2cache.tagsinuse 22186.870278 # Cycle average of tags in use +system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15849.385934 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 72.801131 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1801.118460 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.483685 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.002222 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.054966 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.540872 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 162271 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 162275 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 407009 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 407009 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 199710 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 199710 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 361981 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 361985 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 361981 # number of overall hits -system.cpu.l2cache.overall_hits::total 361985 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1103 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 31215 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 32318 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 60025 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 60025 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1103 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 91240 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 92343 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1103 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses -system.cpu.l2cache.overall_misses::total 92343 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57356000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1623180000 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 499.254810 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.635685 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.026168 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.015236 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.677090 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 80 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 189212 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 189292 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 435341 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 435341 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 237875 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 237875 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 80 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 427087 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 427167 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 80 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 427087 # number of overall hits +system.cpu.l2cache.overall_hits::total 427167 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1027 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4274 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5301 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21860 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21860 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1027 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26134 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27161 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1027 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26134 # number of overall misses +system.cpu.l2cache.overall_misses::total 27161 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53404000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 222248000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 275652000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1136720000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1136720000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 53404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1358968000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1412372000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 53404000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1358968000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1412372000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 407009 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 407009 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 435341 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 435341 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 259735 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 259735 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 1107 # number of demand (read+write) accesses @@ -316,17 +316,17 @@ system.cpu.l2cache.demand_accesses::total 454328 # n system.cpu.l2cache.overall_accesses::cpu.inst 1107 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 453221 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996387 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.161330 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.166080 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231101 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.231101 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996387 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.201315 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.203252 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996387 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.201315 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.203252 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.927733 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022089 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.027241 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.084163 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.084163 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.927733 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.057663 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059783 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.927733 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.057663 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059783 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -346,41 +346,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59035 # number of writebacks -system.cpu.l2cache.writebacks::total 59035 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1103 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31215 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 32318 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60025 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 60025 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1103 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 92343 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1103 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 92343 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1248600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1292720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2401000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2401000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 3693720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 3693720000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.161330 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166080 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231101 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.231101 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.203252 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.203252 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 2523 # number of writebacks +system.cpu.l2cache.writebacks::total 2523 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1027 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4274 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5301 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21860 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21860 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1027 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26134 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27161 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1027 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26134 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27161 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 170960000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 874400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 874400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1045360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1086440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41080000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1045360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1086440000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022089 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027241 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.084163 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.084163 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059783 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059783 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index 54d39141c..994a9cc44 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -510,7 +510,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index 5eab9f73c..486e549a7 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:07:25 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 28 2012 23:06:37 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -21,7 +21,6 @@ Uncompressed data compared correctly Compressing Input Data, level 3 Compressed data 97831 bytes in length Uncompressing Data -info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 @@ -40,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 636988382500 because target called exit() +Exiting @ tick 636762784500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 26e1be238..608862386 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.636988 # Number of seconds simulated -sim_ticks 636988382500 # Number of ticks simulated -final_tick 636988382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.636763 # Number of seconds simulated +sim_ticks 636762784500 # Number of ticks simulated +final_tick 636762784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63436 # Simulator instruction rate (inst/s) -host_op_rate 116883 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45916521 # Simulator tick rate (ticks/s) -host_mem_usage 227532 # Number of bytes of host memory used -host_seconds 13872.75 # Real time elapsed on the host +host_inst_rate 102830 # Simulator instruction rate (inst/s) +host_op_rate 189469 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74404788 # Simulator tick rate (ticks/s) +host_mem_usage 230588 # Number of bytes of host memory used +host_seconds 8558.09 # Real time elapsed on the host sim_insts 880025312 # Number of instructions simulated sim_ops 1621493982 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 59200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5774848 # Number of bytes read from this memory -system.physmem.bytes_read::total 5834048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 59200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 59200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3731712 # Number of bytes written to this memory -system.physmem.bytes_written::total 3731712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 925 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 90232 # Number of read requests responded to by this memory -system.physmem.num_reads::total 91157 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58308 # Number of write requests responded to by this memory -system.physmem.num_writes::total 58308 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 9065861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9158798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92937 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92937 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5858367 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5858367 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5858367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 9065861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15017166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 58816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1694912 # Number of bytes read from this memory +system.physmem.bytes_read::total 1753728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 58816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 58816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162944 # Number of bytes written to this memory +system.physmem.bytes_written::total 162944 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26483 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27402 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2546 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2546 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2661764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2754131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 255894 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 255894 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 255894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2661764 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3010025 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1273976766 # number of cpu cycles simulated +system.cpu.numCycles 1273525570 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 154678064 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 154678064 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26667110 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 77406078 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 77035710 # Number of BTB hits +system.cpu.BPredUnit.lookups 155344135 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 155344135 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26655607 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 77245204 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 76889704 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180711057 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1490230522 # Number of instructions fetch has processed -system.cpu.fetch.Branches 154678064 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 77035710 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 402278451 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 93695646 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 624053491 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1298 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 186830267 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9529255 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1273914012 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.999814 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.235188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180802236 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1488442027 # Number of instructions fetch has processed +system.cpu.fetch.Branches 155344135 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 76889704 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 402274046 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 93385401 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 623851243 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1029 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 186094276 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8755292 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1273499648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.998943 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.233820 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 878853214 68.99% 68.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24303546 1.91% 70.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15677834 1.23% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17928928 1.41% 73.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26735770 2.10% 75.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18262172 1.43% 77.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 28765750 2.26% 79.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39797773 3.12% 82.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 223589025 17.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 878442365 68.98% 68.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24602632 1.93% 70.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15260428 1.20% 72.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18256548 1.43% 73.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26724815 2.10% 75.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18280477 1.44% 77.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29063774 2.28% 79.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39873032 3.13% 82.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 222995577 17.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1273914012 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.121414 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.169747 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 300082895 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 537078967 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 281798821 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 88083788 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 66869541 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2368899404 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 66869541 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 352603459 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124071504 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2838 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302490800 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 427875870 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2273771459 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 200 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 293326885 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 103161675 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 640 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3463149697 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 7120628194 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 7120621014 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7180 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1273499648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121980 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.168757 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 300474409 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 536583689 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 281514067 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88356524 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 66570959 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2368586772 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 66570959 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 352813558 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 123796819 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1672 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302654861 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 427661779 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2273830132 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 293323791 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 102919235 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 68 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3464511326 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 7120107939 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 7120100187 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7752 # Number of floating rename lookups system.cpu.rename.CommittedMaps 2493860970 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 969288727 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 110 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 110 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 746079760 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 546341437 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 222247757 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 352469730 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 147023702 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2027529381 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 546 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1785574895 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118982 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 405869160 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1051620727 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1273914012 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.401645 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.311838 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 970650356 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 98 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 745542263 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 545308074 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 222233244 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 351719357 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 147016761 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2026127683 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 554 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1785922004 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 133826 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 404499601 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1046828617 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 504 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1273499648 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.402373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.312278 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 347011244 27.24% 27.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 447440186 35.12% 62.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 243114046 19.08% 81.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 151317631 11.88% 93.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 40944695 3.21% 96.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 32410749 2.54% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9957171 0.78% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1368147 0.11% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 350143 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 346409167 27.20% 27.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 447658448 35.15% 62.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 243252093 19.10% 81.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 151077765 11.86% 93.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 40789672 3.20% 96.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 32618177 2.56% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9933898 0.78% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1410310 0.11% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 350118 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1273914012 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1273499648 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 237387 9.29% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2138623 83.73% 93.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 178205 6.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 252918 9.83% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2142956 83.30% 93.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 176798 6.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46809715 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1066790690 59.74% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46813783 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1067070411 59.75% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued @@ -194,86 +194,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 479501542 26.85% 89.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192472948 10.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 479563179 26.85% 89.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192474631 10.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1785574895 # Type of FU issued -system.cpu.iq.rate 1.401576 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2554215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001430 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4847736227 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2433580235 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1726806271 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 772 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2168 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1741319146 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 249 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 208956586 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1785922004 # Type of FU issued +system.cpu.iq.rate 1.402345 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2572672 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001441 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4848049464 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2430808619 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1727155501 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 690 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2256 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1741680668 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 225 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 208913373 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 127299312 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 36681 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 190307 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 34061700 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 126265949 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36209 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 190191 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 34047187 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1845 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 1764 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 66869541 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 356934 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 88692 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2027529927 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63849570 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 546341437 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 222247757 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 103 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 48888 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 421 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 190307 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2139656 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24653796 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26793452 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1767588629 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 473898164 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 17986266 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 66570959 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 346337 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 84829 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2026128237 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63751416 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 545308074 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 222233244 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 86 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49329 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 412 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 190191 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2137841 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24642910 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26780751 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1767814472 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 473818516 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 18107532 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 665742013 # number of memory reference insts executed -system.cpu.iew.exec_branches 109684623 # Number of branches executed -system.cpu.iew.exec_stores 191843849 # Number of stores executed -system.cpu.iew.exec_rate 1.387458 # Inst execution rate -system.cpu.iew.wb_sent 1728148485 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1726806355 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1262041827 # num instructions producing a value -system.cpu.iew.wb_consumers 2984894243 # num instructions consuming a value +system.cpu.iew.exec_refs 665662363 # number of memory reference insts executed +system.cpu.iew.exec_branches 109724389 # Number of branches executed +system.cpu.iew.exec_stores 191843847 # Number of stores executed +system.cpu.iew.exec_rate 1.388126 # Inst execution rate +system.cpu.iew.wb_sent 1728501294 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1727155577 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1262384078 # num instructions producing a value +system.cpu.iew.wb_consumers 2985492726 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.355446 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.422810 # average fanout of values written-back +system.cpu.iew.wb_rate 1.356200 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.422839 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 406040141 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 404636626 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26667277 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1207044471 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.343359 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.660546 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26655738 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1206928689 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.343488 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.659364 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 437250010 36.22% 36.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 432641487 35.84% 72.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 93464877 7.74% 79.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 134893392 11.18% 90.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35716518 2.96% 93.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23306370 1.93% 95.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 25727632 2.13% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8874629 0.74% 98.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15169556 1.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 436768152 36.19% 36.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 432905754 35.87% 72.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 93527824 7.75% 79.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 134952786 11.18% 90.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35694459 2.96% 93.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23721563 1.97% 95.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 25354378 2.10% 98.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8867881 0.73% 98.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15135892 1.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1207044471 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1206928689 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025312 # Number of instructions committed system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -284,68 +284,68 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15169556 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15135892 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3219409038 # The number of ROB reads -system.cpu.rob.rob_writes 4121954747 # The number of ROB writes -system.cpu.timesIdled 1354 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 62754 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3217923405 # The number of ROB reads +system.cpu.rob.rob_writes 4118849074 # The number of ROB writes +system.cpu.timesIdled 528 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 25922 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025312 # Number of Instructions Simulated system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated -system.cpu.cpi 1.447659 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.447659 # CPI: Total CPI of All Threads -system.cpu.ipc 0.690770 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.690770 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4473469252 # number of integer regfile reads -system.cpu.int_regfile_writes 2589680881 # number of integer regfile writes -system.cpu.fp_regfile_reads 84 # number of floating regfile reads -system.cpu.misc_regfile_reads 911429698 # number of misc regfile reads -system.cpu.icache.replacements 22 # number of replacements -system.cpu.icache.tagsinuse 827.099302 # Cycle average of tags in use -system.cpu.icache.total_refs 186828876 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 928 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 201324.219828 # Average number of references to valid blocks. +system.cpu.cpi 1.447147 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.447147 # CPI: Total CPI of All Threads +system.cpu.ipc 0.691015 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.691015 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4473867691 # number of integer regfile reads +system.cpu.int_regfile_writes 2590130278 # number of integer regfile writes +system.cpu.fp_regfile_reads 76 # number of floating regfile reads +system.cpu.misc_regfile_reads 911455321 # number of misc regfile reads +system.cpu.icache.replacements 19 # number of replacements +system.cpu.icache.tagsinuse 827.665584 # Cycle average of tags in use +system.cpu.icache.total_refs 186092930 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 926 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 200964.287257 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 827.099302 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.403857 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.403857 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 186828882 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 186828882 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 186828882 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 186828882 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 186828882 # number of overall hits -system.cpu.icache.overall_hits::total 186828882 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1385 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1385 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1385 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses -system.cpu.icache.overall_misses::total 1385 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 46636000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 46636000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 46636000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 46636000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 46636000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 46636000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 186830267 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 186830267 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 186830267 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 186830267 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 186830267 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 186830267 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 827.665584 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.404134 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.404134 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 186092930 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 186092930 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 186092930 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 186092930 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 186092930 # number of overall hits +system.cpu.icache.overall_hits::total 186092930 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1346 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1346 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1346 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1346 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1346 # number of overall misses +system.cpu.icache.overall_misses::total 1346 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 45797000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 45797000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 45797000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 45797000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 45797000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 45797000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 186094276 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 186094276 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 186094276 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 186094276 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 186094276 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 186094276 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33672.202166 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 33672.202166 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 33672.202166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 33672.202166 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.517088 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34024.517088 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.517088 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34024.517088 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.517088 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34024.517088 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,94 +354,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 450 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 450 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 450 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 450 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 450 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 450 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 935 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 935 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 935 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 935 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 935 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 935 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32805000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32805000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32805000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32805000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32805000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32805000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 420 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 420 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 420 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 420 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 420 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 926 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 926 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 926 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 926 # 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35165.766739 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35165.766739 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35165.766739 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35165.766739 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35165.766739 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 445407 # number of replacements -system.cpu.dcache.tagsinuse 4093.514636 # Cycle average of tags in use -system.cpu.dcache.total_refs 452671406 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 449503 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1007.048687 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 723816000 # 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number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264901979 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264901979 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 453124365 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 453124365 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 453124365 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 453124365 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000780 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000780 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 453088036 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 453088036 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 453088036 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 453088036 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000779 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000779 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001308 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.001000 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001000 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.001000 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001000 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10393.162559 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 10393.162559 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13094.918510 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13094.918510 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11861.789165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11861.789165 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000999 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000999 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000999 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000999 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5997.299811 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 5997.299811 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8181.910862 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8181.910862 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7185.489429 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7185.489429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7185.489429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7185.489429 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -450,136 +450,132 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 400713 # number of writebacks -system.cpu.dcache.writebacks::total 400713 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3434 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3434 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3459 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3459 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3459 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2485166000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3996172000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3996172000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3996172000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3996172000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000767 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 428484 # number of writebacks +system.cpu.dcache.writebacks::total 428484 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3123 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3123 # 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number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000768 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000768 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000992 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000992 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7432.029905 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7432.029905 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10094.012234 # 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average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 20810.359304 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 736.556866 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 675.930273 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.635082 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.022478 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020628 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.678187 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 198774 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 198781 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 428484 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 428484 # 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number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 919 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26483 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27402 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 919 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26483 # number of overall misses +system.cpu.l2cache.overall_misses::total 27402 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31495500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 157147500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 188643000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 753146000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 753146000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 31495500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 910293500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 941789000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 31495500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 910293500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 941789000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 926 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 203334 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 204260 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 428484 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 428484 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246198 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246198 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 926 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 449532 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 450458 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 926 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 449532 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 450458 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992441 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022426 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.026824 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089046 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.089046 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992441 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.058912 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060831 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992441 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.058912 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060831 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34271.490751 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34462.171053 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34430.187991 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34354.148611 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34354.148611 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34271.490751 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34372.748556 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34369.352602 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34271.490751 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34372.748556 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34369.352602 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -588,52 +584,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58308 # number of writebacks -system.cpu.l2cache.writebacks::total 58308 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 925 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31911 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 32836 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58321 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 58321 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 925 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 90232 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 91157 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 925 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 90232 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 91157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28735500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 989353500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1018089000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1807989500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1807989500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28735500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2797343000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2826078500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28735500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2797343000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2826078500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.156964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.160780 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.202376 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.202376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.405405 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.525430 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.268608 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.660140 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.660140 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 2546 # number of writebacks +system.cpu.l2cache.writebacks::total 2546 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 919 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4560 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5479 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21923 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21923 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 919 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26483 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27402 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 919 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26483 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27402 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28532500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 141346000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 169878500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 679632500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 679632500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28532500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 820978500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 849511000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28532500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 820978500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 849511000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992441 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022426 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026824 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089046 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089046 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992441 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060831 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992441 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060831 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31047.334059 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30996.929825 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.384194 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.889477 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.889477 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31047.334059 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31000.207680 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31001.788191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31047.334059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31000.207680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31001.788191 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini index 30e9071fd..3c1333558 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index 7f0dbded6..9e79ba165 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:13:02 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 28 2012 23:10:36 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1803258587000 because target called exit() +Exiting @ tick 1800635309000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 00ab9a331..a3d141ce0 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.803259 # Number of seconds simulated -sim_ticks 1803258587000 # Number of ticks simulated -final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.800635 # Number of seconds simulated +sim_ticks 1800635309000 # Number of ticks simulated +final_tick 1800635309000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 587265 # Simulator instruction rate (inst/s) -host_op_rate 1082068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1203364849 # Simulator tick rate (ticks/s) -host_mem_usage 225604 # Number of bytes of host memory used -host_seconds 1498.51 # Real time elapsed on the host +host_inst_rate 904173 # Simulator instruction rate (inst/s) +host_op_rate 1665987 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1850044030 # Simulator tick rate (ticks/s) +host_mem_usage 228536 # Number of bytes of host memory used +host_seconds 973.29 # Real time elapsed on the host sim_insts 880025313 # Number of instructions simulated sim_ops 1621493983 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5679744 # Number of bytes read from this memory -system.physmem.bytes_read::total 5725952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory +system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3712448 # Number of bytes written to this memory -system.physmem.bytes_written::total 3712448 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 160640 # Number of bytes written to this memory +system.physmem.bytes_written::total 160640 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 88746 # Number of read requests responded to by this memory -system.physmem.num_reads::total 89468 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58007 # Number of write requests responded to by this memory -system.physmem.num_writes::total 58007 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3149711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3175336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 25625 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 25625 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2058744 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2058744 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2058744 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3149711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5234080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 26287 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2510 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2510 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 934319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 959981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 25662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 25662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 89213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 89213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 89213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 934319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1049194 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 3606517174 # number of cpu cycles simulated +system.cpu.numCycles 3601270618 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 880025313 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 607228182 # nu system.cpu.num_load_insts 419042125 # Number of load instructions system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3606517174 # Number of busy cycles +system.cpu.num_busy_cycles 3601270618 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use +system.cpu.icache.tagsinuse 660.189072 # Cycle average of tags in use system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 660.186297 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.322357 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.322357 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 660.189072 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.322358 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.322358 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits @@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.895332 # Cycle average of tags in use system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.896939 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999731 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999731 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4094.895332 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999730 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999730 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 418844799 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 418844799 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 442048 # n system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses system.cpu.dcache.overall_misses::total 442048 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4043270000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4043270000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5872734000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5872734000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9916004000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9916004000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9916004000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9916004000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2943878000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2943878000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4348848000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4348848000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7292726000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7292726000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7292726000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7292726000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 419042125 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 419042125 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20490.305383 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20490.305383 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23997.572756 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23997.572756 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22431.962140 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22431.962140 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14918.855093 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14918.855093 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17770.564150 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17770.564150 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16497.588497 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16497.588497 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16497.588497 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16497.588497 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 396372 # number of writebacks -system.cpu.dcache.writebacks::total 396372 # number of writebacks +system.cpu.dcache.writebacks::writebacks 422980 # number of writebacks +system.cpu.dcache.writebacks::total 422980 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 442048 system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3451292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3451292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5138568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5138568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8589860000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8589860000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8589860000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8589860000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3614682000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3614682000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5966582000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5966582000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5966582000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5966582000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses @@ -226,65 +226,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17490.305383 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17490.305383 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20997.572756 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20997.572756 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14770.564150 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14770.564150 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13497.588497 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13497.588497 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13497.588497 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13497.588497 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 71208 # number of replacements -system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use -system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2581 # number of replacements +system.cpu.l2cache.tagsinuse 22163.019096 # Cycle average of tags in use +system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16187.723361 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 48.180025 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1821.019706 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.494010 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001470 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.055573 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.551054 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 166833 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 166833 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 396372 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 396372 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 186469 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 186469 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 353302 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 353302 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 353302 # number of overall hits -system.cpu.l2cache.overall_hits::total 353302 # number of overall hits +system.cpu.l2cache.occ_blocks::writebacks 21019.596332 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 596.850673 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 546.572092 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.641467 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.018214 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016680 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.676362 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 193009 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 193009 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 422980 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 222752 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 222752 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 415761 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 415761 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 415761 # number of overall hits +system.cpu.l2cache.overall_hits::total 415761 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 30493 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 31215 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 58253 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 58253 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4317 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5039 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21970 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21970 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 722 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 88746 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 89468 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26287 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27009 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 88746 # number of overall misses -system.cpu.l2cache.overall_misses::total 89468 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26287 # number of overall misses +system.cpu.l2cache.overall_misses::total 27009 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37544000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1585636000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1623180000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3029156000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3029156000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 224484000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 262028000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1142440000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1142440000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 37544000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4614792000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 4652336000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1366924000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1404468000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 37544000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4614792000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 4652336000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1366924000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1404468000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 396372 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 396372 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 422980 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 422980 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 244722 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 244722 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses @@ -294,16 +294,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 722 system.cpu.l2cache.overall_accesses::cpu.data 442048 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154531 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.157613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238037 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.238037 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021878 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.025443 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089775 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.089775 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.200761 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.202064 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.059466 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.061000 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.200761 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.202064 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.059466 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.061000 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -323,41 +323,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58007 # number of writebacks -system.cpu.l2cache.writebacks::total 58007 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 2510 # number of writebacks +system.cpu.l2cache.writebacks::total 2510 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30493 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 31215 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58253 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 58253 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4317 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5039 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21970 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21970 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 88746 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 89468 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26287 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27009 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 722 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1051480000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1080360000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154531 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.157613 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238037 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238037 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021878 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025443 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089775 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089775 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.202064 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059466 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061000 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.202064 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059466 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061000 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency |