diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref')
18 files changed, 1221 insertions, 1217 deletions
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index 647cf0cf8..ca675ac92 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing +cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing egid=100 env= errout=cerr @@ -512,7 +512,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 196024f42..5518ac66c 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:54:18 -gem5 started Jul 2 2012 11:32:18 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:13:42 gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 389181871500 because target called exit() +Exiting @ tick 389171398000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 09d53c6a6..1f6271301 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,173 +1,173 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.389182 # Number of seconds simulated -sim_ticks 389181871500 # Number of ticks simulated -final_tick 389181871500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.389171 # Number of seconds simulated +sim_ticks 389171398000 # Number of ticks simulated +final_tick 389171398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 233275 # Simulator instruction rate (inst/s) -host_op_rate 234010 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64792479 # Simulator tick rate (ticks/s) -host_mem_usage 223132 # Number of bytes of host memory used -host_seconds 6006.59 # Real time elapsed on the host -sim_insts 1401188958 # Number of instructions simulated -sim_ops 1405604152 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 78592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1679360 # Number of bytes read from this memory -system.physmem.bytes_read::total 1757952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 78592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 78592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 163456 # Number of bytes written to this memory -system.physmem.bytes_written::total 163456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1228 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26240 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27468 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2554 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2554 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 201942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4315103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4517045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201942 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201942 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 419999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 419999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 419999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4315103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4937044 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 172352 # Simulator instruction rate (inst/s) +host_op_rate 172895 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47869738 # Simulator tick rate (ticks/s) +host_mem_usage 232600 # Number of bytes of host memory used +host_seconds 8129.80 # Real time elapsed on the host +sim_insts 1401188945 # Number of instructions simulated +sim_ops 1405604139 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 78528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1679232 # Number of bytes read from this memory +system.physmem.bytes_read::total 1757760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 78528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 78528 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 163392 # Number of bytes written to this memory +system.physmem.bytes_written::total 163392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26238 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27465 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2553 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2553 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 201783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4314891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4516673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201783 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201783 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 419846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 419846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 419846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 201783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4314891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4936519 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 778363744 # number of cpu cycles simulated +system.cpu.numCycles 778342797 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98202538 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88418167 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3786555 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 66007710 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65666961 # Number of BTB hits +system.cpu.BPredUnit.lookups 98197174 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88413236 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3785239 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 66015510 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65664831 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1332 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 165889798 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648919647 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98202538 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65668293 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330430884 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21692843 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 264292230 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2686 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 162826473 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 754831 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 778319405 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.124393 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146166 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1336 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 221 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 165881717 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648798034 # Number of instructions fetch has processed +system.cpu.fetch.Branches 98197174 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65666167 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330411204 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21674066 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 264316799 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 122 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2684 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 162819499 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 755607 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 778298464 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.124294 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146110 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 447888521 57.55% 57.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74380250 9.56% 67.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37976870 4.88% 71.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9085355 1.17% 73.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28165073 3.62% 76.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18828553 2.42% 79.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11512004 1.48% 80.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3871007 0.50% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146611772 18.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 447887260 57.55% 57.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74376407 9.56% 67.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37977630 4.88% 71.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9084449 1.17% 73.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28163510 3.62% 76.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18828809 2.42% 79.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11510131 1.48% 80.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3871378 0.50% 81.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146598890 18.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 778319405 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126165 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.118444 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 217790097 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214638982 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285156910 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 43029734 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17703682 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1642636299 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17703682 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 241734353 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36955708 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 51946820 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303044657 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126934185 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1631312586 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 31546408 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73332264 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3116970 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1360939473 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2755912805 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2722068159 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33844646 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 116169021 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2679381 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2694981 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 272918574 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 438732735 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 180262547 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 255381650 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 82499363 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1517064379 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2634738 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1460855259 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54931 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 113760463 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 136767182 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 391067 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 778319405 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.876935 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.427664 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 778298464 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126162 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.118344 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 217730423 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214714894 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285147826 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 43019383 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17685938 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1642518992 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17685938 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 241679768 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36912628 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 51960575 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303022356 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 127037199 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1631180439 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 31545211 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73402474 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3147906 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1360824399 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2755700072 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2721856567 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33843505 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 116053960 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2679524 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2694715 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 273063750 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 438707438 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 180249753 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 255184370 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 82754828 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1516941659 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2635026 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1460769058 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54636 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 113641063 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 136677185 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 391355 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 778298464 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.876875 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.427909 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147026932 18.89% 18.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 186493885 23.96% 42.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 211074443 27.12% 69.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 130841076 16.81% 86.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70678954 9.08% 95.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20414805 2.62% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7717737 0.99% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3979587 0.51% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 91986 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 147064057 18.90% 18.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 186545297 23.97% 42.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210910023 27.10% 69.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 130868567 16.81% 86.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70782480 9.09% 95.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20278912 2.61% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7762488 1.00% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3994514 0.51% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 92126 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 778319405 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 778298464 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 100522 6.26% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 166576 10.38% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1142590 71.19% 87.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 195193 12.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 113664 7.00% 7.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 166579 10.26% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 17.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1139490 70.19% 87.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 203791 12.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 867158324 59.36% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 867086456 59.36% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2642655 0.18% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2642669 0.18% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued @@ -193,160 +193,160 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419786972 28.74% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171267308 11.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419773044 28.74% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171266889 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1460855259 # Type of FU issued -system.cpu.iq.rate 1.876829 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1604881 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001099 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3684016874 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1624580550 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1444446185 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17672861 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9115596 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8537125 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453449423 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9010717 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215321766 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1460769058 # Type of FU issued +system.cpu.iq.rate 1.876768 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1623524 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001111 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3683829696 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1624339460 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1444358901 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17685044 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9115270 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8537907 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1453371390 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9021192 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215484580 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36219891 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 54743 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 244893 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13414405 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36194595 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 55177 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 245195 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13401611 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3575 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 58855 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3537 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 56120 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17703682 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1537187 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 135114 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1613898993 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4122313 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 438732735 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 180262547 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2549072 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 88195 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3279 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 244893 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2354936 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1566356 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3921292 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1455308115 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 417068435 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5547144 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17685938 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1543124 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 135108 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1613772123 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4123534 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 438707438 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 180249753 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2549312 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 88176 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3284 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 245195 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2354964 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1564711 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3919675 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1455222367 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 417054039 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5546691 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 94199876 # number of nop insts executed -system.cpu.iew.exec_refs 587640720 # number of memory reference insts executed -system.cpu.iew.exec_branches 89112594 # Number of branches executed -system.cpu.iew.exec_stores 170572285 # Number of stores executed -system.cpu.iew.exec_rate 1.869702 # Inst execution rate -system.cpu.iew.wb_sent 1453906115 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1452983310 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154403216 # num instructions producing a value -system.cpu.iew.wb_consumers 1205257004 # num instructions consuming a value +system.cpu.iew.exec_nop 94195438 # number of nop insts executed +system.cpu.iew.exec_refs 587626307 # number of memory reference insts executed +system.cpu.iew.exec_branches 89109233 # Number of branches executed +system.cpu.iew.exec_stores 170572268 # Number of stores executed +system.cpu.iew.exec_rate 1.869642 # Inst execution rate +system.cpu.iew.wb_sent 1453822475 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1452896808 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1154316777 # num instructions producing a value +system.cpu.iew.wb_consumers 1205166277 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.866715 # insts written-back per cycle +system.cpu.iew.wb_rate 1.866654 # insts written-back per cycle system.cpu.iew.wb_fanout 0.957807 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1485108101 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 124289069 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 1485108088 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1489523282 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 124161815 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3786555 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 760616334 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.958311 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.503558 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3785239 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 760613137 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.958319 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.503249 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 241729742 31.78% 31.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276918822 36.41% 68.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43178321 5.68% 73.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54835847 7.21% 81.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19622698 2.58% 83.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13346857 1.75% 85.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30466514 4.01% 89.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10424135 1.37% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70093398 9.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 241688690 31.78% 31.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276879553 36.40% 68.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43195227 5.68% 73.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54904670 7.22% 81.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19686775 2.59% 83.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13341138 1.75% 85.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30448610 4.00% 89.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10352977 1.36% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70115497 9.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 760616334 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1485108101 # Number of instructions committed -system.cpu.commit.committedOps 1489523295 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 760613137 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1485108088 # Number of instructions committed +system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 569360986 # Number of memory references committed -system.cpu.commit.loads 402512844 # Number of loads committed +system.cpu.commit.refs 569360985 # Number of memory references committed +system.cpu.commit.loads 402512843 # Number of loads committed system.cpu.commit.membars 51356 # Number of memory barriers committed -system.cpu.commit.branches 86248929 # Number of branches committed +system.cpu.commit.branches 86248928 # Number of branches committed system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. +system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70093398 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70115497 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2304270430 # The number of ROB reads -system.cpu.rob.rob_writes 3245352893 # The number of ROB writes -system.cpu.timesIdled 1469 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 44339 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1401188958 # Number of Instructions Simulated -system.cpu.committedOps 1405604152 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1401188958 # Number of Instructions Simulated -system.cpu.cpi 0.555502 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.555502 # CPI: Total CPI of All Threads -system.cpu.ipc 1.800172 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.800172 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1980619061 # number of integer regfile reads -system.cpu.int_regfile_writes 1276279795 # number of integer regfile writes -system.cpu.fp_regfile_reads 16952700 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491726 # number of floating regfile writes -system.cpu.misc_regfile_reads 593312421 # number of misc regfile reads +system.cpu.rob.rob_reads 2304117867 # The number of ROB reads +system.cpu.rob.rob_writes 3245080355 # The number of ROB writes +system.cpu.timesIdled 1467 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 44333 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1401188945 # Number of Instructions Simulated +system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated +system.cpu.cpi 0.555487 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.555487 # CPI: Total CPI of All Threads +system.cpu.ipc 1.800221 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.800221 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1980525328 # number of integer regfile reads +system.cpu.int_regfile_writes 1276196147 # number of integer regfile writes +system.cpu.fp_regfile_reads 16956232 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491758 # number of floating regfile writes +system.cpu.misc_regfile_reads 593298094 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 216 # number of replacements -system.cpu.icache.tagsinuse 1046.067933 # Cycle average of tags in use -system.cpu.icache.total_refs 162824561 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1364 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 119372.845308 # Average number of references to valid blocks. +system.cpu.icache.replacements 214 # number of replacements +system.cpu.icache.tagsinuse 1046.066234 # Cycle average of tags in use +system.cpu.icache.total_refs 162817587 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1362 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 119543.015419 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1046.067933 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1046.066234 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.510775 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.510775 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 162824561 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 162824561 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 162824561 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 162824561 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 162824561 # number of overall hits -system.cpu.icache.overall_hits::total 162824561 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 162817587 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 162817587 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 162817587 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 162817587 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 162817587 # number of overall hits +system.cpu.icache.overall_hits::total 162817587 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1912 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1912 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1912 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1912 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1912 # number of overall misses system.cpu.icache.overall_misses::total 1912 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62993000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62993000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62993000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62993000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62993000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62993000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162826473 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162826473 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162826473 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162826473 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162826473 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162826473 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62928500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62928500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62928500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62928500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62928500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62928500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162819499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162819499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162819499 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162819499 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162819499 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162819499 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32946.129707 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 32946.129707 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 32946.129707 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 32946.129707 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 32946.129707 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 32946.129707 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32912.395397 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 32912.395397 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 32912.395397 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 32912.395397 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 32912.395397 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 32912.395397 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -355,106 +355,106 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 547 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 547 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 547 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 547 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 547 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 547 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1365 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1365 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1365 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1365 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1365 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 44905000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 44905000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 44905000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 44905000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 44905000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 44905000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 549 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 549 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 549 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 549 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 549 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 549 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1363 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1363 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1363 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1363 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1363 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1363 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 44825000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 44825000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 44825000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 44825000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 44825000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 44825000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32897.435897 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32897.435897 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32897.435897 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 32897.435897 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32897.435897 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 32897.435897 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32887.013940 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32887.013940 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32887.013940 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 32887.013940 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32887.013940 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 32887.013940 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 458041 # number of replacements -system.cpu.dcache.tagsinuse 4094.912001 # Cycle average of tags in use -system.cpu.dcache.total_refs 365776449 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 462137 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 791.489210 # Average number of references to valid blocks. +system.cpu.dcache.replacements 457891 # number of replacements +system.cpu.dcache.tagsinuse 4094.911972 # Cycle average of tags in use +system.cpu.dcache.total_refs 365599087 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 461987 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 791.362283 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 160490000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.912001 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4094.911972 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999734 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999734 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200799973 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200799973 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164975157 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164975157 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 200622584 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200622584 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164975184 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164975184 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365775130 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365775130 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365775130 # number of overall hits -system.cpu.dcache.overall_hits::total 365775130 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 900450 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 900450 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1871659 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1871659 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365597768 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365597768 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365597768 # number of overall hits +system.cpu.dcache.overall_hits::total 365597768 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 900300 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 900300 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1871632 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1871632 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2772109 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2772109 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2772109 # number of overall misses -system.cpu.dcache.overall_misses::total 2772109 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11941437000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11941437000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57464288206 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57464288206 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 69500 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 69500 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 69405725206 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 69405725206 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 69405725206 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 69405725206 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201700423 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201700423 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2771932 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2771932 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2771932 # number of overall misses +system.cpu.dcache.overall_misses::total 2771932 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11940266500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11940266500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57531206941 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57531206941 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 69000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 69000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 69471473441 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 69471473441 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 69471473441 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 69471473441 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201522884 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201522884 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 368547239 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 368547239 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 368547239 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 368547239 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004464 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004464 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368369700 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368369700 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368369700 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368369700 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004467 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004467 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011218 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.011218 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007522 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007522 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007522 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007522 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13261.632517 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13261.632517 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30702.327831 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30702.327831 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 9928.571429 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 9928.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25037.155900 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25037.155900 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25037.155900 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25037.155900 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.007525 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007525 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007525 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007525 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13262.541930 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13262.541930 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30738.524956 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30738.524956 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 9857.142857 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 9857.142857 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25062.473914 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25062.473914 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25062.473914 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25062.473914 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 4500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -463,140 +463,140 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 2250 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 442976 # number of writebacks -system.cpu.dcache.writebacks::total 442976 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 700359 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 700359 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1609620 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1609620 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2309979 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2309979 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2309979 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2309979 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200091 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200091 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262039 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262039 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 442836 # number of writebacks +system.cpu.dcache.writebacks::total 442836 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 700344 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 700344 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1609608 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1609608 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2309952 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2309952 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2309952 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2309952 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 199956 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 199956 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262024 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262024 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 462130 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 462130 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 462130 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 462130 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 927899000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 927899000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5906951258 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5906951258 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 461980 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 461980 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 461980 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 461980 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 927311500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 927311500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5914389505 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5914389505 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 47000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 47000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6834850258 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6834850258 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6834850258 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6834850258 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6841701005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6841701005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6841701005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6841701005 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001571 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001570 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001570 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001254 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4637.384990 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4637.384990 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22542.259961 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22542.259961 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4637.577767 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4637.577767 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22571.938086 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22571.938086 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 6714.285714 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 6714.285714 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14789.886521 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14789.886521 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14789.886521 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14789.886521 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14809.517739 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14809.517739 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14809.517739 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14809.517739 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2683 # number of replacements -system.cpu.l2cache.tagsinuse 22381.394167 # Cycle average of tags in use -system.cpu.l2cache.total_refs 541833 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24313 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.285732 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2682 # number of replacements +system.cpu.l2cache.tagsinuse 22381.194058 # Cycle average of tags in use +system.cpu.l2cache.total_refs 541474 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24308 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.275547 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20744.483714 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 995.293943 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 641.616510 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633071 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.030374 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019581 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.683026 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 137 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 195649 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 195786 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 442976 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 442976 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 240248 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 240248 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 137 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 435897 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 436034 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 137 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 435897 # number of overall hits -system.cpu.l2cache.overall_hits::total 436034 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1228 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4437 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5665 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::writebacks 20744.863113 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 994.979192 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 641.351753 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.633083 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.030364 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019573 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.683020 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 136 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 195513 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 195649 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 442836 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 442836 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 240236 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 240236 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 136 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 435749 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 435885 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 136 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 435749 # number of overall hits +system.cpu.l2cache.overall_hits::total 435885 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1227 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4435 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5662 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 21803 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 21803 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1228 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26240 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27468 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1228 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26240 # number of overall misses -system.cpu.l2cache.overall_misses::total 27468 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42725500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 151899500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 194625000 # number of ReadReq miss cycles +system.cpu.l2cache.demand_misses::cpu.inst 1227 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26238 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27465 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1227 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26238 # number of overall misses +system.cpu.l2cache.overall_misses::total 27465 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42694000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 151831500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 194525500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 842839500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 842839500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 42725500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 994739000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1037464500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 42725500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 994739000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1037464500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1365 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 200086 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 201451 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 442976 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 442976 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 262051 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 262051 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1365 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 462137 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 463502 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1365 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 462137 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 463502 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.899634 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022175 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.028121 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083201 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083201 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.899634 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.056780 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059262 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.899634 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.056780 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059262 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34792.752443 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34234.730674 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34355.692851 # average ReadReq miss latency +system.cpu.l2cache.demand_miss_latency::cpu.inst 42694000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 994671000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1037365000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 42694000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 994671000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1037365000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1363 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 199948 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 201311 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 442836 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 442836 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 262039 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 262039 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1363 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 461987 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 463350 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1363 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 461987 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 463350 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.900220 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022181 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.028126 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083205 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083205 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.900220 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.056794 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059275 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.900220 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.056794 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059275 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34795.436023 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34234.836528 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34356.322854 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38657.042609 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38657.042609 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34792.752443 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37909.260671 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37769.932285 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34792.752443 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37909.260671 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37769.932285 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34795.436023 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37909.558655 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37770.435099 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34795.436023 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37909.558655 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37770.435099 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -605,52 +605,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2554 # number of writebacks -system.cpu.l2cache.writebacks::total 2554 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1228 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4437 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5665 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 2553 # number of writebacks +system.cpu.l2cache.writebacks::total 2553 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1227 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4435 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5662 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21803 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 21803 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1228 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26240 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27468 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1228 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26240 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27468 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38798500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 138491500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 177290000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1227 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26238 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27465 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1227 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26238 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27465 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38769500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 138429500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 177199000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 776754500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 776754500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38798500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 915246000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 954044500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38798500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 915246000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 954044500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.899634 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022175 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028121 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083201 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083201 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056780 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059262 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056780 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059262 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31594.869707 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31212.869056 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31295.675199 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38769500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 915184000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 953953500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38769500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 915184000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 953953500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.900220 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022181 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.028126 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083205 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083205 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.900220 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056794 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059275 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.900220 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056794 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059275 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31596.984515 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31212.965051 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31296.185094 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35626.037701 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35626.037701 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31594.869707 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34879.801829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34732.943789 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31594.869707 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34879.801829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34732.943789 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31596.984515 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34880.097568 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34733.424358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31596.984515 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34880.097568 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34733.424358 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 47913c070..bd29989f9 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -99,8 +99,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout index bf7412ed2..a424ec0a0 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:41 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:13:47 gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 744764119000 because target called exit() +Exiting @ tick 744764112500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index ed36e3ce0..4e5a83c19 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.744764 # Number of seconds simulated -sim_ticks 744764119000 # Number of ticks simulated -final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 744764112500 # Number of ticks simulated +final_tick 744764112500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3186892 # Simulator instruction rate (inst/s) -host_op_rate 3196366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1598188492 # Simulator tick rate (ticks/s) -host_mem_usage 214172 # Number of bytes of host memory used -host_seconds 466.01 # Real time elapsed on the host -sim_insts 1485108101 # Number of instructions simulated -sim_ops 1489523295 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 5940452044 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1385817593 # Number of bytes read from this memory -system.physmem.bytes_read::total 7326269637 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5940452044 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5940452044 # Number of instructions bytes read from this memory +host_inst_rate 3155762 # Simulator instruction rate (inst/s) +host_op_rate 3165144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1582576951 # Simulator tick rate (ticks/s) +host_mem_usage 222108 # Number of bytes of host memory used +host_seconds 470.60 # Real time elapsed on the host +sim_insts 1485108088 # Number of instructions simulated +sim_ops 1489523282 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 5940451992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1385817592 # Number of bytes read from this memory +system.physmem.bytes_read::total 7326269584 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5940451992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5940451992 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 614672063 # Number of bytes written to this memory system.physmem.bytes_written::total 614672063 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1485113011 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 402512844 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1887625855 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1485112998 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 402512843 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1887625841 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 166846816 # Number of write requests responded to by this memory system.physmem.num_writes::total 166846816 # Number of write requests responded to by this memory system.physmem.num_other::cpu.data 1326 # Number of other requests responded to by this memory system.physmem.num_other::total 1326 # Number of other requests responded to by this memory system.physmem.bw_read::cpu.inst 7976286575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1860746990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9837033566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1860747005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9837033580 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7976286575 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7976286575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 825324485 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 825324485 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 825324492 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 825324492 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7976286575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2686071475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10662358051 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2686071498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10662358072 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 1489528239 # number of cpu cycles simulated +system.cpu.numCycles 1489528226 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1485108101 # Number of instructions committed -system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses +system.cpu.committedInsts 1485108088 # Number of instructions committed +system.cpu.committedOps 1489523282 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1319481286 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses system.cpu.num_func_calls 1207835 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 78161763 # number of instructions that are conditional controls -system.cpu.num_int_insts 1319481298 # number of integer instructions +system.cpu.num_conditional_control_insts 78161762 # number of instructions that are conditional controls +system.cpu.num_int_insts 1319481286 # number of integer instructions system.cpu.num_fp_insts 8454127 # number of float instructions -system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read -system.cpu.num_int_register_writes 1234343158 # number of times the integer registers were written +system.cpu.num_int_register_reads 2499743560 # number of times the integer registers were read +system.cpu.num_int_register_writes 1234343145 # number of times the integer registers were written system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written -system.cpu.num_mem_refs 569365767 # number of memory refs -system.cpu.num_load_insts 402515346 # Number of load instructions +system.cpu.num_mem_refs 569365766 # number of memory refs +system.cpu.num_load_insts 402515345 # Number of load instructions system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1489528239 # Number of busy cycles +system.cpu.num_busy_cycles 1489528226 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini index ed5d7509c..cd17d9d73 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing +cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing egid=100 env= errout=cerr @@ -181,7 +181,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout index 7b12cccb1..7275352c5 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:54:18 -gem5 started Jul 2 2012 12:13:11 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:13:49 gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2063177751000 because target called exit() +Exiting @ tick 2063177737000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 607412a81..3078a0fec 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.063178 # Number of seconds simulated -sim_ticks 2063177751000 # Number of ticks simulated -final_tick 2063177751000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2063177737000 # Number of ticks simulated +final_tick 2063177737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1349558 # Simulator instruction rate (inst/s) -host_op_rate 1353570 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1874864984 # Simulator tick rate (ticks/s) -host_mem_usage 222108 # Number of bytes of host memory used -host_seconds 1100.44 # Real time elapsed on the host -sim_insts 1485108101 # Number of instructions simulated -sim_ops 1489523295 # Number of ops (including micro ops) simulated +host_inst_rate 1527975 # Simulator instruction rate (inst/s) +host_op_rate 1532517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2122729697 # Simulator tick rate (ticks/s) +host_mem_usage 231576 # Number of bytes of host memory used +host_seconds 971.95 # Real time elapsed on the host +sim_insts 1485108088 # Number of instructions simulated +sim_ops 1489523282 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1672576 # Number of bytes read from this memory system.physmem.bytes_read::total 1738304 # Number of bytes read from this memory @@ -35,43 +35,43 @@ system.physmem.bw_total::cpu.inst 31858 # To system.physmem.bw_total::cpu.data 810680 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 920801 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 4126355502 # number of cpu cycles simulated +system.cpu.numCycles 4126355474 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1485108101 # Number of instructions committed -system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses +system.cpu.committedInsts 1485108088 # Number of instructions committed +system.cpu.committedOps 1489523282 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1319481286 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses system.cpu.num_func_calls 1207835 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 78161763 # number of instructions that are conditional controls -system.cpu.num_int_insts 1319481298 # number of integer instructions +system.cpu.num_conditional_control_insts 78161762 # number of instructions that are conditional controls +system.cpu.num_int_insts 1319481286 # number of integer instructions system.cpu.num_fp_insts 8454127 # number of float instructions -system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read -system.cpu.num_int_register_writes 1234343157 # number of times the integer registers were written +system.cpu.num_int_register_reads 2499743560 # number of times the integer registers were read +system.cpu.num_int_register_writes 1234343144 # number of times the integer registers were written system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written -system.cpu.num_mem_refs 569365767 # number of memory refs -system.cpu.num_load_insts 402515346 # Number of load instructions +system.cpu.num_mem_refs 569365766 # number of memory refs +system.cpu.num_load_insts 402515345 # Number of load instructions system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4126355502 # Number of busy cycles +system.cpu.num_busy_cycles 4126355474 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 118 # number of replacements -system.cpu.icache.tagsinuse 906.409372 # Cycle average of tags in use -system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 906.409378 # Cycle average of tags in use +system.cpu.icache.total_refs 1485111892 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1341564.491418 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 906.409372 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 906.409378 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.442583 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.442583 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1485111905 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1485111905 # number of overall hits -system.cpu.icache.overall_hits::total 1485111905 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1485111892 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1485111892 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1485111892 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1485111892 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1485111892 # number of overall hits +system.cpu.icache.overall_hits::total 1485111892 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1107 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1107 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1107 # number of demand (read+write) misses @@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 58777000 system.cpu.icache.demand_miss_latency::total 58777000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 58777000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 58777000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1485113012 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1485113012 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1485113012 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 1485112999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1485112999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1485112999 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1485112999 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1485112999 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1485112999 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses @@ -136,24 +136,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50095.754291 system.cpu.icache.overall_avg_mshr_miss_latency::total 50095.754291 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements -system.cpu.dcache.tagsinuse 4095.205153 # Cycle average of tags in use -system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4095.205181 # Cycle average of tags in use +system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 588945000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.205153 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 588931000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.205181 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999806 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 402319358 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 568906446 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 568906446 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 568906446 # number of overall hits -system.cpu.dcache.overall_hits::total 568906446 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 568906445 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 568906445 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 568906445 # number of overall hits +system.cpu.dcache.overall_hits::total 568906445 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses @@ -174,16 +174,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7443302000 system.cpu.dcache.demand_miss_latency::total 7443302000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7443302000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7443302000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 569359660 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 569359660 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 569359660 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 569359660 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 569359659 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 569359659 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 569359659 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 569359659 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses @@ -256,14 +256,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13423.371741 system.cpu.dcache.overall_avg_mshr_miss_latency::total 13423.371741 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2614 # number of replacements -system.cpu.l2cache.tagsinuse 22185.384662 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22185.384813 # Cycle average of tags in use system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20828.536366 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 857.441703 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 499.406594 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 20828.536507 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 857.441709 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 499.406597 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.635636 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.026167 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.015241 # Average percentage of cache occupancy diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index 9d85601cf..c34a24e32 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -510,7 +510,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing +cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr @@ -533,7 +533,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index e9fade7f1..df6cae2da 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 12:44:41 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:23:13 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -19,12 +19,12 @@ info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 3 +info: Increasing stack size by one page. Compressed data 97831 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 -info: Increasing stack size by one page. Compressed data 83382 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -40,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 636963896500 because target called exit() +Exiting @ tick 636923447500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 5a09d9960..e0bb93d0f 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.636964 # Number of seconds simulated -sim_ticks 636963896500 # Number of ticks simulated -final_tick 636963896500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.636923 # Number of seconds simulated +sim_ticks 636923447500 # Number of ticks simulated +final_tick 636923447500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94339 # Simulator instruction rate (inst/s) -host_op_rate 173825 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68282764 # Simulator tick rate (ticks/s) -host_mem_usage 230548 # Number of bytes of host memory used -host_seconds 9328.33 # Real time elapsed on the host -sim_insts 880025312 # Number of instructions simulated -sim_ops 1621493982 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 59072 # Number of bytes read from this memory +host_inst_rate 70364 # Simulator instruction rate (inst/s) +host_op_rate 129650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50926468 # Simulator tick rate (ticks/s) +host_mem_usage 235448 # Number of bytes of host memory used +host_seconds 12506.73 # Real time elapsed on the host +sim_insts 880025277 # Number of instructions simulated +sim_ops 1621493925 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 58944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1694720 # Number of bytes read from this memory -system.physmem.bytes_read::total 1753792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 59072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 59072 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162752 # Number of bytes written to this memory -system.physmem.bytes_written::total 162752 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 923 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 1753664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 58944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 58944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 163072 # Number of bytes written to this memory +system.physmem.bytes_written::total 163072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 921 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 26480 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27403 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2543 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2543 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2660622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2753362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92740 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92740 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 255512 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 255512 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 255512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2660622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3008874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 27401 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2548 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2548 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2660791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2753336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 256031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 256031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 256031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2660791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3009366 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1273927794 # number of cpu cycles simulated +system.cpu.numCycles 1273846896 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 155476696 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 155476696 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26665974 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 76215157 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 75849392 # Number of BTB hits +system.cpu.BPredUnit.lookups 155381473 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 155381473 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26661992 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 76481328 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 76085061 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180766435 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1491872316 # Number of instructions fetch has processed -system.cpu.fetch.Branches 155476696 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 75849392 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 402325403 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 93614087 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 624018674 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1031 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 185889439 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8548075 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1273900868 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.002953 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.238276 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180777781 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1491151373 # Number of instructions fetch has processed +system.cpu.fetch.Branches 155381473 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 76085061 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 402336644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 93587210 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 623938160 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1139 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 185942531 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8615707 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1273819882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.001935 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.237130 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 878792706 68.98% 68.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24409433 1.92% 70.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14960209 1.17% 72.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18025508 1.41% 73.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26731742 2.10% 75.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18277101 1.43% 77.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 28493019 2.24% 79.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39802935 3.12% 82.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 224408215 17.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 878702474 68.98% 68.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24435713 1.92% 70.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15105270 1.19% 72.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18072889 1.42% 73.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26727903 2.10% 75.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18276740 1.43% 77.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28604131 2.25% 79.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39838610 3.13% 82.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 224056152 17.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1273900868 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122045 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.171081 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 300130332 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 537055352 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 281851498 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 88074501 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 66789185 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2370363864 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 66789185 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 352614235 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124117956 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1807 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302560946 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 427816739 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2274265358 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 293377579 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 103041568 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 112 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3464406080 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 7122244281 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 7122237233 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7048 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 2493860970 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 970545110 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 88 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 88 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 745535849 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 545979333 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 222242756 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 352158228 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 146951837 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2027253751 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 556 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1785885865 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 143298 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 405620982 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1049961378 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 506 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1273900868 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.401903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.311945 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1273819882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121978 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.170589 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 300142098 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 537000439 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 281769365 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88141967 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 66766013 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2369867389 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 66766013 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 352580189 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124109997 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1918 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302594361 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 427767404 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2274189452 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 293406849 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 103032322 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 51 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3464260390 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 7121426016 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 7121418052 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7964 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 2493860878 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 970399512 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 94 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 94 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 745525627 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 545851562 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 222235793 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 352099065 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 146974262 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2027094513 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 587 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1785918647 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 140586 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 405462466 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1049512028 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 537 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1273819882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.402018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.312119 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 346798223 27.22% 27.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 447596849 35.14% 62.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 243149127 19.09% 81.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 151409869 11.89% 93.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 40759247 3.20% 96.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 32504128 2.55% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9931846 0.78% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1400181 0.11% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 351398 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 346849812 27.23% 27.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 447400536 35.12% 62.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 243205365 19.09% 81.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 151321871 11.88% 93.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 40825213 3.20% 96.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 32566088 2.56% 99.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9897563 0.78% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1402374 0.11% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 351060 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1273900868 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1273819882 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 262837 10.20% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2136217 82.89% 93.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 178017 6.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 260443 10.10% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2141420 83.03% 93.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 177309 6.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812745 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1067077874 59.75% 62.37% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812744 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1067089927 59.75% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued @@ -194,158 +194,158 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 479524386 26.85% 89.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192470860 10.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 479538721 26.85% 89.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192477255 10.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1785885865 # Type of FU issued -system.cpu.iq.rate 1.401874 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2577071 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001443 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4848392282 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2433055974 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1727031567 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 685 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2066 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1741649976 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 215 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 208887212 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1785918647 # Type of FU issued +system.cpu.iq.rate 1.401988 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2579172 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001444 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4848376217 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2432738390 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1727118998 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 717 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2336 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1741684846 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 229 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 208839211 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 126937208 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 36775 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 189921 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 34056699 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 126809441 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36531 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 190384 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 34049736 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2072 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 462 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2138 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 453 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 66789185 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 397482 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 85620 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2027254307 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63893728 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 545979333 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 222242756 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 83 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 48032 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 669 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 189921 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2137684 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24653436 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26791120 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1767797184 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 473889834 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18088681 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 66766013 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 400873 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 86074 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2027095100 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63749855 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 545851562 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 222235793 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 48364 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 665 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 190384 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2138396 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24649145 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26787541 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1767801211 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 473822669 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 18117436 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 665730625 # number of memory reference insts executed -system.cpu.iew.exec_branches 109718993 # Number of branches executed -system.cpu.iew.exec_stores 191840791 # Number of stores executed -system.cpu.iew.exec_rate 1.387675 # Inst execution rate -system.cpu.iew.wb_sent 1728379028 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1727031635 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1262282896 # num instructions producing a value -system.cpu.iew.wb_consumers 2985352291 # num instructions consuming a value +system.cpu.iew.exec_refs 665669278 # number of memory reference insts executed +system.cpu.iew.exec_branches 109723805 # Number of branches executed +system.cpu.iew.exec_stores 191846609 # Number of stores executed +system.cpu.iew.exec_rate 1.387766 # Inst execution rate +system.cpu.iew.wb_sent 1728448502 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1727119074 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1262324846 # num instructions producing a value +system.cpu.iew.wb_consumers 2985456049 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.355675 # insts written-back per cycle +system.cpu.iew.wb_rate 1.355829 # insts written-back per cycle system.cpu.iew.wb_fanout 0.422825 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 880025312 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 405765098 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 880025277 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1621493925 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 405606358 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26666115 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1207111683 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.343284 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.660206 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26662143 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1207053869 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.343348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.659934 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 437166011 36.22% 36.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 432802967 35.85% 72.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 93484629 7.74% 79.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 134841213 11.17% 90.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35727207 2.96% 93.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23483214 1.95% 95.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 25551681 2.12% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8874954 0.74% 98.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15179807 1.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 437041200 36.21% 36.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 432850092 35.86% 72.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 93447270 7.74% 79.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 134928627 11.18% 90.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 35706636 2.96% 93.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23539949 1.95% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 25505485 2.11% 98.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8872667 0.74% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15161943 1.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1207111683 # Number of insts commited each cycle -system.cpu.commit.committedInsts 880025312 # Number of instructions committed -system.cpu.commit.committedOps 1621493982 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1207053869 # Number of insts commited each cycle +system.cpu.commit.committedInsts 880025277 # Number of instructions committed +system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 607228182 # Number of memory references committed -system.cpu.commit.loads 419042125 # Number of loads committed +system.cpu.commit.refs 607228178 # Number of memory references committed +system.cpu.commit.loads 419042121 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 107161579 # Number of branches committed +system.cpu.commit.branches 107161574 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. +system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15179807 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15161943 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3219190956 # The number of ROB reads -system.cpu.rob.rob_writes 4121324121 # The number of ROB writes -system.cpu.timesIdled 604 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26926 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 880025312 # Number of Instructions Simulated -system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated -system.cpu.cpi 1.447604 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.447604 # CPI: Total CPI of All Threads -system.cpu.ipc 0.690797 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.690797 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4473882728 # number of integer regfile reads -system.cpu.int_regfile_writes 2589957068 # number of integer regfile writes -system.cpu.fp_regfile_reads 68 # number of floating regfile reads -system.cpu.misc_regfile_reads 911502074 # number of misc regfile reads -system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 828.056964 # Cycle average of tags in use -system.cpu.icache.total_refs 185888078 # Total number of references to valid blocks. +system.cpu.rob.rob_reads 3218992209 # The number of ROB reads +system.cpu.rob.rob_writes 4120983322 # The number of ROB writes +system.cpu.timesIdled 600 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 880025277 # Number of Instructions Simulated +system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated +system.cpu.cpi 1.447512 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.447512 # CPI: Total CPI of All Threads +system.cpu.ipc 0.690841 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.690841 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4473913165 # number of integer regfile reads +system.cpu.int_regfile_writes 2590095162 # number of integer regfile writes +system.cpu.fp_regfile_reads 76 # number of floating regfile reads +system.cpu.misc_regfile_reads 911461004 # number of misc regfile reads +system.cpu.icache.replacements 22 # number of replacements +system.cpu.icache.tagsinuse 826.529270 # Cycle average of tags in use +system.cpu.icache.total_refs 185941160 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 930 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 199879.653763 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 199936.731183 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 828.056964 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.404325 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.404325 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 185888078 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 185888078 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 185888078 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 185888078 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 185888078 # number of overall hits -system.cpu.icache.overall_hits::total 185888078 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1361 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1361 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1361 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1361 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1361 # number of overall misses -system.cpu.icache.overall_misses::total 1361 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 47861000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 47861000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 47861000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 47861000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 47861000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 47861000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 185889439 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 185889439 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 185889439 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 185889439 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 185889439 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 185889439 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 826.529270 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.403579 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.403579 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 185941162 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 185941162 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 185941162 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 185941162 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 185941162 # number of overall hits +system.cpu.icache.overall_hits::total 185941162 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1369 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1369 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1369 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1369 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1369 # number of overall misses +system.cpu.icache.overall_misses::total 1369 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 47914000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 47914000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 47914000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 47914000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 47914000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 47914000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 185942531 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 185942531 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 185942531 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 185942531 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 185942531 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 185942531 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35166.054372 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35166.054372 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35166.054372 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35166.054372 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35166.054372 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35166.054372 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34999.269540 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34999.269540 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34999.269540 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34999.269540 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34999.269540 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34999.269540 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,94 +354,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 431 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 431 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 431 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 431 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 431 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 431 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 930 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 930 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 930 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 930 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 930 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 930 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34220000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 34220000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34220000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 34220000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34220000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 34220000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 435 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 435 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 435 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 435 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 435 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 435 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 934 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 934 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 934 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 934 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 934 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 934 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34118000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 34118000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34118000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 34118000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34118000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 34118000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36795.698925 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36795.698925 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36795.698925 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36795.698925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36795.698925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36795.698925 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36528.907923 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36528.907923 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36528.907923 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36528.907923 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36528.907923 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36528.907923 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 445433 # number of replacements -system.cpu.dcache.tagsinuse 4093.428364 # Cycle average of tags in use -system.cpu.dcache.total_refs 452731874 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 449529 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1007.124955 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 738592000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.428364 # Average occupied blocks per requestor +system.cpu.dcache.replacements 445452 # number of replacements +system.cpu.dcache.tagsinuse 4093.428018 # Cycle average of tags in use +system.cpu.dcache.total_refs 452712586 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 449548 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1007.039484 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 738623000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.428018 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999372 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999372 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 264792027 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 264792027 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187939847 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187939847 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 452731874 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 452731874 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 452731874 # number of overall hits -system.cpu.dcache.overall_hits::total 452731874 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 206669 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 206669 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 246210 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 246210 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 452879 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 452879 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 452879 # number of overall misses -system.cpu.dcache.overall_misses::total 452879 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1300622500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1300622500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2040839000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2040839000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 3341461500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 3341461500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 3341461500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 3341461500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264998696 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264998696 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 264772769 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264772769 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939813 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939813 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452712582 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452712582 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452712582 # number of overall hits +system.cpu.dcache.overall_hits::total 452712582 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 206710 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 206710 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246244 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246244 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 452954 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 452954 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 452954 # number of overall misses +system.cpu.dcache.overall_misses::total 452954 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1296370500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1296370500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2046596000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2046596000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 3342966500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 3342966500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 3342966500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 3342966500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264979479 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264979479 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 453184753 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 453184753 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 453184753 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 453184753 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 453165536 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 453165536 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 453165536 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 453165536 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000780 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000780 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001308 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000999 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000999 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000999 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000999 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6293.263624 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 6293.263624 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8289.017505 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8289.017505 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7378.265497 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7378.265497 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7378.265497 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7378.265497 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001309 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.001000 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001000 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001000 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001000 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6271.445503 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 6271.445503 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8311.252254 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8311.252254 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 7380.366439 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 7380.366439 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 7380.366439 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 7380.366439 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -450,32 +450,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428496 # number of writebacks -system.cpu.dcache.writebacks::total 428496 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3328 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3328 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 20 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 20 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3348 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3348 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3348 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3348 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203341 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203341 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246190 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246190 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 449531 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 449531 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 449531 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 449531 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 607771500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 607771500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1249776500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1249776500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1857548000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1857548000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1857548000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1857548000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 428527 # number of writebacks +system.cpu.dcache.writebacks::total 428527 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3377 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3377 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 23 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 23 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3400 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3400 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3400 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3400 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203333 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203333 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246221 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246221 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 449554 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 449554 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 449554 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 449554 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 608060000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 608060000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1250112000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1250112000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1858172000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1858172000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1858172000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1858172000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000767 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses @@ -484,98 +484,102 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 system.cpu.dcache.demand_mshr_miss_rate::total 0.000992 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000992 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2988.927467 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2988.927467 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5076.471425 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5076.471425 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4132.191106 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 4132.191106 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4132.191106 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 4132.191106 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2990.463919 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2990.463919 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 5077.194878 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 5077.194878 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 4133.367738 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 4133.367738 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4133.367738 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 4133.367738 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2658 # number of replacements -system.cpu.l2cache.tagsinuse 22224.770293 # Cycle average of tags in use -system.cpu.l2cache.total_refs 517694 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24236 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.360538 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2664 # number of replacements +system.cpu.l2cache.tagsinuse 22218.876300 # Cycle average of tags in use +system.cpu.l2cache.total_refs 517817 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24235 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.366495 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20809.314009 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 737.283312 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 678.172973 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.635050 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.022500 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020696 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.678246 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 198771 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 198778 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 428496 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 428496 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224280 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 224280 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 423051 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 423058 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 423051 # number of overall hits -system.cpu.l2cache.overall_hits::total 423058 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 923 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4558 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5481 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21922 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21922 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 923 # number of demand (read+write) misses +system.cpu.l2cache.occ_blocks::writebacks 20808.584757 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 736.081009 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 674.210534 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.635028 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.022463 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020575 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.678066 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 9 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 198770 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 198779 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 428527 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 428527 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 224300 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 224300 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 9 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 423070 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 423079 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 9 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 423070 # number of overall hits +system.cpu.l2cache.overall_hits::total 423079 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 921 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4549 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 5470 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21931 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21931 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 921 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 26480 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27403 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 923 # number of overall misses +system.cpu.l2cache.demand_misses::total 27401 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 921 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 26480 # number of overall misses -system.cpu.l2cache.overall_misses::total 27403 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32677500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 156724000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 189401500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 752017500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 752017500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32677500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 908741500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 941419000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32677500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 908741500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 941419000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 27401 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32620000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 157237500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 189857500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 752514000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 752514000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32620000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 909751500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 942371500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32620000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 909751500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 942371500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 930 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 203329 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 204259 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 428496 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 428496 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 203319 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 204249 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 428527 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 428527 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246231 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246231 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 930 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 449531 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 450461 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 449550 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 450480 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 930 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 449531 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 450461 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992473 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022417 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.026834 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089041 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.089041 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992473 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.058906 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060833 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992473 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.058906 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060833 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35403.575298 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34384.379114 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34556.011677 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34304.237752 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34304.237752 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35403.575298 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34318.032477 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34354.596212 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35403.575298 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34318.032477 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34354.596212 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 449550 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 450480 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.990323 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022374 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.026781 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089067 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.089067 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990323 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.058903 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060826 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990323 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.058903 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060826 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35418.023887 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34565.289075 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34708.866545 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34312.799234 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34312.799234 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35418.023887 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34356.174471 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34391.865260 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35418.023887 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34356.174471 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34391.865260 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -584,52 +588,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2543 # number of writebacks -system.cpu.l2cache.writebacks::total 2543 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 923 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4558 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5481 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21922 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21922 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 923 # number of demand (read+write) MSHR misses +system.cpu.l2cache.writebacks::writebacks 2548 # number of writebacks +system.cpu.l2cache.writebacks::total 2548 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 921 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4549 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5470 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21931 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21931 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 921 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 26480 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27403 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 923 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27401 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 921 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26480 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27403 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29745000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 141788500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 171533500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 679883500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 679883500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29745000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 821672000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 851417000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29745000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 821672000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 851417000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992473 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022417 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026834 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089041 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089041 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992473 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058906 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060833 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992473 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058906 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060833 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32226.435536 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31107.612988 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31296.022624 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.753307 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.753307 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32226.435536 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31029.909366 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31070.211291 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32226.435536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31029.909366 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31070.211291 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 27401 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29694500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 141471000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 171165500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 680167500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 680167500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29694500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 821638500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 851333000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29694500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 821638500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 851333000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.990323 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022374 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026781 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089067 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089067 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990323 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058903 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060826 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990323 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058903 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060826 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32241.585233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31099.362497 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31291.681901 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.975651 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.975651 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32241.585233 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31028.644260 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31069.413525 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32241.585233 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31028.644260 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31069.413525 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini index 6c78f711c..6d1d261c9 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -120,8 +120,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +width=8 +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout index db4607fa4..177dd7f45 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:08:17 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:24:05 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 963992704000 because target called exit() +Exiting @ tick 963992671000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 0e02ab2e6..a463fb589 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.963993 # Number of seconds simulated -sim_ticks 963992704000 # Number of ticks simulated -final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 963992671000 # Number of ticks simulated +final_tick 963992671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1254577 # Simulator instruction rate (inst/s) -host_op_rate 2311626 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1374282564 # Simulator tick rate (ticks/s) -host_mem_usage 216676 # Number of bytes of host memory used -host_seconds 701.45 # Real time elapsed on the host -sim_insts 880025313 # Number of instructions simulated -sim_ops 1621493983 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 9492133912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1842452913 # Number of bytes read from this memory -system.physmem.bytes_read::total 11334586825 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 9492133912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 9492133912 # Number of instructions bytes read from this memory +host_inst_rate 1263596 # Simulator instruction rate (inst/s) +host_op_rate 2328243 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1384161146 # Simulator tick rate (ticks/s) +host_mem_usage 224820 # Number of bytes of host memory used +host_seconds 696.45 # Real time elapsed on the host +sim_insts 880025278 # Number of instructions simulated +sim_ops 1621493926 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1842452909 # Number of bytes read from this memory +system.physmem.bytes_read::total 11334586469 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 9492133560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 9492133560 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 864451000 # Number of bytes written to this memory system.physmem.bytes_written::total 864451000 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1186516739 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 419042125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1605558864 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1186516695 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 419042121 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1605558816 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 188186057 # Number of write requests responded to by this memory system.physmem.num_writes::total 188186057 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9846686466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1911272674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11757959140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9846686466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9846686466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 896740189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 896740189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9846686466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2808012863 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12654699330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 9846686438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1911272735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11757959173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9846686438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9846686438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 896740220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 896740220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9846686438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2808012955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12654699393 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1927985409 # number of cpu cycles simulated +system.cpu.numCycles 1927985343 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 880025313 # Number of instructions committed -system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses +system.cpu.committedInsts 880025278 # Number of instructions committed +system.cpu.committedOps 1621493926 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1621354436 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls -system.cpu.num_int_insts 1621354493 # number of integer instructions +system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls +system.cpu.num_int_insts 1621354436 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 5129484088 # number of times the integer registers were read -system.cpu.num_int_register_writes 2493860970 # number of times the integer registers were written +system.cpu.num_int_register_reads 5129483910 # number of times the integer registers were read +system.cpu.num_int_register_writes 2493860878 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 607228182 # number of memory refs -system.cpu.num_load_insts 419042125 # Number of load instructions +system.cpu.num_mem_refs 607228178 # number of memory refs +system.cpu.num_load_insts 419042121 # Number of load instructions system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1927985409 # Number of busy cycles +system.cpu.num_busy_cycles 1927985343 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini index 2eec436ef..05ff130e5 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing +cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr @@ -202,7 +202,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index d6878297d..371c8d53f 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 13:03:08 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:30:12 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1801979727000 because target called exit() +Exiting @ tick 1801979679000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 79bdadab4..12b9ffa30 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.801980 # Number of seconds simulated -sim_ticks 1801979727000 # Number of ticks simulated -final_tick 1801979727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1801979679000 # Number of ticks simulated +final_tick 1801979679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 622629 # Simulator instruction rate (inst/s) -host_op_rate 1147227 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1274922997 # Simulator tick rate (ticks/s) -host_mem_usage 228496 # Number of bytes of host memory used -host_seconds 1413.40 # Real time elapsed on the host -sim_insts 880025313 # Number of instructions simulated -sim_ops 1621493983 # Number of ops (including micro ops) simulated +host_inst_rate 670221 # Simulator instruction rate (inst/s) +host_op_rate 1234919 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1372375195 # Simulator tick rate (ticks/s) +host_mem_usage 233400 # Number of bytes of host memory used +host_seconds 1313.04 # Real time elapsed on the host +sim_insts 880025278 # Number of instructions simulated +sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory @@ -35,43 +35,43 @@ system.physmem.bw_total::cpu.inst 25643 # To system.physmem.bw_total::cpu.data 933622 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1048411 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 3603959454 # number of cpu cycles simulated +system.cpu.numCycles 3603959358 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 880025313 # Number of instructions committed -system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses +system.cpu.committedInsts 880025278 # Number of instructions committed +system.cpu.committedOps 1621493926 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1621354436 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls -system.cpu.num_int_insts 1621354493 # number of integer instructions +system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls +system.cpu.num_int_insts 1621354436 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 5129484088 # number of times the integer registers were read -system.cpu.num_int_register_writes 2493860970 # number of times the integer registers were written +system.cpu.num_int_register_reads 5129483910 # number of times the integer registers were read +system.cpu.num_int_register_writes 2493860878 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 607228182 # number of memory refs -system.cpu.num_load_insts 419042125 # Number of load instructions +system.cpu.num_mem_refs 607228178 # number of memory refs +system.cpu.num_load_insts 419042121 # Number of load instructions system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3603959454 # Number of busy cycles +system.cpu.num_busy_cycles 3603959358 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 660.169533 # Cycle average of tags in use -system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 660.169550 # Cycle average of tags in use +system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 660.169533 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 660.169550 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.322348 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.322348 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1186516018 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1186516018 # number of overall hits -system.cpu.icache.overall_hits::total 1186516018 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1186515974 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1186515974 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1186515974 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1186515974 # number of overall hits +system.cpu.icache.overall_hits::total 1186515974 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 722 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 722 # number of demand (read+write) misses @@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 40521000 system.cpu.icache.demand_miss_latency::total 40521000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 40521000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 40521000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1186516740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1186516740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1186516740 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1186516740 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1186516740 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1186516740 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 1186516696 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1186516696 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1186516696 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1186516696 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1186516696 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1186516696 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses @@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53123.268698 system.cpu.icache.overall_avg_mshr_miss_latency::total 53123.268698 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.tagsinuse 4094.884021 # Cycle average of tags in use -system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.884130 # Cycle average of tags in use +system.cpu.dcache.total_refs 606786130 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 788858000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.884021 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 1372.670230 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 788810000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.884130 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999728 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999728 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 418844799 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 418844799 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 187941335 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 606786134 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 606786134 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 606786134 # number of overall hits -system.cpu.dcache.overall_hits::total 606786134 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 606786130 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 606786130 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 606786130 # number of overall hits +system.cpu.dcache.overall_hits::total 606786130 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses @@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7311185000 system.cpu.dcache.demand_miss_latency::total 7311185000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7311185000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7311185000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 419042125 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 419042125 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 607228182 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 607228182 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 607228182 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 607228182 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 607228178 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 607228178 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 607228178 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 607228178 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses @@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13539.346406 system.cpu.dcache.overall_avg_mshr_miss_latency::total 13539.346406 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2581 # number of replacements -system.cpu.l2cache.tagsinuse 22161.849584 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22161.850174 # Cycle average of tags in use system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21018.400125 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 596.832039 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 546.617420 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21018.400685 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 596.832055 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 546.617434 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.641431 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.018214 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.016681 # Average percentage of cache occupancy |