diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref')
| -rw-r--r-- | tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt | 570 | ||||
| -rw-r--r-- | tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 1280 | ||||
| -rw-r--r-- | tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt | 1192 | ||||
| -rw-r--r-- | tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 1200 | ||||
| -rw-r--r-- | tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt | 1136 |
5 files changed, 2689 insertions, 2689 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 722ef4fea..7484e6ff9 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.269661 # Number of seconds simulated -sim_ticks 269661304500 # Number of ticks simulated -final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.269672 # Number of seconds simulated +sim_ticks 269671683500 # Number of ticks simulated +final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98682 # Simulator instruction rate (inst/s) -host_op_rate 98682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44214559 # Simulator tick rate (ticks/s) -host_mem_usage 273520 # Number of bytes of host memory used -host_seconds 6098.93 # Real time elapsed on the host +host_inst_rate 125294 # Simulator instruction rate (inst/s) +host_op_rate 125294 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56139844 # Simulator tick rate (ticks/s) +host_mem_usage 224468 # Number of bytes of host memory used +host_seconds 4803.57 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6040882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6240480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 240657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 240657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 240657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6040882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6481138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199591 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6040649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6240240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199591 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199591 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 240648 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 240648 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 240648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199591 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6040649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6480888 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 26294 # Total number of read requests seen system.physmem.writeReqs 1014 # Total number of write requests seen system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady @@ -43,41 +43,41 @@ system.physmem.bytesConsumedRd 1682816 # by system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1732 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1568 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1581 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1632 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1673 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1558 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1550 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1675 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 76 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 52 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 81 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 53 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 55 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 58 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 74 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1624 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1652 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1558 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1549 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1582 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1713 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1672 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 59 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 66 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 49 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 58 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 59 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 78 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 269661252500 # Total gap between requests +system.physmem.totGap 269671631500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 17608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 16680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 928 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 44 # Wh system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,56 +171,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 364261179 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1024159179 # Sum of mem lat for all requests -system.physmem.totBusLat 105120000 # Total cycles spent in databus access -system.physmem.totBankLat 554778000 # Total cycles spent in bank access -system.physmem.avgQLat 13860.78 # Average queueing delay per request -system.physmem.avgBankLat 21110.27 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38971.05 # Average memory access latency +system.physmem.totQLat 384531397 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1096635147 # Sum of mem lat for all requests +system.physmem.totBusLat 131400000 # Total cycles spent in databus access +system.physmem.totBankLat 580703750 # Total cycles spent in bank access +system.physmem.avgQLat 14632.09 # Average queueing delay per request +system.physmem.avgBankLat 22096.79 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 41728.89 # Average memory access latency system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.24 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 12.19 # Average write queue length over time -system.physmem.readRowHits 17406 # Number of row buffer hits during reads -system.physmem.writeRowHits 51 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes -system.physmem.avgGap 9874807.84 # Average gap between requests -system.cpu.branchPred.lookups 86405274 # Number of BP lookups -system.cpu.branchPred.condPredicted 81476244 # Number of conditional branches predicted +system.physmem.readRowHits 16315 # Number of row buffer hits during reads +system.physmem.writeRowHits 296 # Number of row buffer hits during writes +system.physmem.readRowHitRate 62.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.19 # Row buffer hit rate for writes +system.physmem.avgGap 9875187.91 # Average gap between requests +system.cpu.branchPred.lookups 86405403 # Number of BP lookups +system.cpu.branchPred.condPredicted 81476373 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 36343014 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44773910 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 44774039 # Number of BTB lookups system.cpu.branchPred.BTBHits 34660000 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.411153 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 77.410930 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517568 # DTB read hits +system.cpu.dtb.read_hits 114517881 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520199 # DTB read accesses -system.cpu.dtb.write_hits 39453362 # DTB write hits +system.cpu.dtb.read_accesses 114520512 # DTB read accesses +system.cpu.dtb.write_hits 39453501 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39455664 # DTB write accesses -system.cpu.dtb.data_hits 153970930 # DTB hits +system.cpu.dtb.write_accesses 39455803 # DTB write accesses +system.cpu.dtb.data_hits 153971382 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153975863 # DTB accesses -system.cpu.itb.fetch_hits 24997854 # ITB hits +system.cpu.dtb.data_accesses 153976315 # DTB accesses +system.cpu.itb.fetch_hits 24997849 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 24997876 # ITB accesses +system.cpu.itb.fetch_accesses 24997871 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,18 +234,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 539322610 # number of cpu cycles simulated +system.cpu.numCycles 539343368 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 49180751 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541064074 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1004918560 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1004918920 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255160193 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 255159834 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 154928367 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken). @@ -256,12 +256,12 @@ system.cpu.execution_unit.executions 412128439 # Nu system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 535759910 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 535764686 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 295987 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50789311 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 488533299 # Number of cycles cpu stages are processed. -system.cpu.activity 90.582759 # Percentage of cycles cpu is active +system.cpu.timesIdled 296132 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50809772 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 488533596 # Number of cycles cpu stages are processed. +system.cpu.activity 90.579328 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -273,77 +273,77 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.896098 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.896132 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.896098 # CPI: Total CPI of All Threads -system.cpu.ipc 1.115950 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.896132 # CPI: Total CPI of All Threads +system.cpu.ipc 1.115907 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.115950 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 200593326 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338729284 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.806431 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 228903212 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310419398 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.557275 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 197757745 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341564865 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.332198 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 427944093 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111378517 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.651557 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 192521650 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 346800960 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.303063 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.115907 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 200616262 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338727106 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.803610 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 228924009 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310419359 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.555053 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 197778592 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341564776 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.329744 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 427964982 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111378386 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.650738 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 192544683 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346798685 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.300167 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 729.842734 # Cycle average of tags in use -system.cpu.icache.total_refs 24996820 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.833784 # Cycle average of tags in use +system.cpu.icache.total_refs 24996815 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29236.046784 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29236.040936 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 729.842734 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.356369 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.356369 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 24996820 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24996820 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24996820 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24996820 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24996820 # number of overall hits -system.cpu.icache.overall_hits::total 24996820 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 729.833784 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.356364 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.356364 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24996815 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24996815 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24996815 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24996815 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24996815 # number of overall hits +system.cpu.icache.overall_hits::total 24996815 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses system.cpu.icache.overall_misses::total 1034 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 53126500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 53126500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 53126500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 53126500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 53126500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 53126500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24997854 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24997854 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24997854 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24997854 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24997854 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24997854 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 55838000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 55838000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 55838000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 55838000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 55838000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 55838000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24997849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24997849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24997849 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24997849 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24997849 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24997849 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51379.593810 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51379.593810 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51379.593810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51379.593810 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54001.934236 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54001.934236 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54001.934236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54001.934236 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 93.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 66.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -359,38 +359,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 855 system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43645500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43645500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43645500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43645500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43645500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43645500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46086000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46086000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46086000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46086000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46086000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46086000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51047.368421 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51047.368421 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53901.754386 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53901.754386 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53901.754386 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53901.754386 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22879.132168 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22879.116549 # Cycle average of tags in use system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21684.623478 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 718.963213 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 475.545477 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.661762 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21684.482794 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 718.953898 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 475.679858 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014512 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.698215 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits @@ -415,17 +415,17 @@ system.cpu.l2cache.demand_misses::total 26294 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses system.cpu.l2cache.overall_misses::total 26294 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42639500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 472401500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 515041000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1150527000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1150527000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 42639500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1622928500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1665568000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 42639500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1622928500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1665568000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45081000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470660000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 515741000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1199043000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1199043000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 45081000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1669703000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1714784000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 45081000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1669703000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1714784000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -450,17 +450,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.057631 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50700.951249 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114521.575758 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 103713.451470 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53944.439235 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53944.439235 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50700.951249 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63761.776608 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 63344.032859 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50700.951249 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63761.776608 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 63344.032859 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53604.042806 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.393939 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 103854.409988 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56219.195424 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56219.195424 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65215.790675 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65215.790675 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,17 +482,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32024355 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418973423 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 450997778 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 880714009 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 880714009 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32024355 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1299687432 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1331711787 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32024355 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1299687432 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1331711787 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34645117 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418280186 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452925303 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 933604040 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 933604040 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34645117 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1351884226 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1386529343 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34645117 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1351884226 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1386529343 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses @@ -504,51 +504,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38078.900119 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101569.314667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 90817.111961 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41293.792620 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41293.792620 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38078.900119 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51062.249322 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38078.900119 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51062.249322 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41195.145065 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101401.257212 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91205.256343 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43773.632783 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43773.632783 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.419207 # Cycle average of tags in use -system.cpu.dcache.total_refs 151786016 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4093.423527 # Cycle average of tags in use +system.cpu.dcache.total_refs 151786159 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 333.306286 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.419207 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37665388 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37665388 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 151786016 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 151786016 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 151786016 # number of overall hits -system.cpu.dcache.overall_hits::total 151786016 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1785933 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1785933 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2179347 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2179347 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2179347 # number of overall misses -system.cpu.dcache.overall_misses::total 2179347 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5991137000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5991137000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22893915500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22893915500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28885052500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28885052500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28885052500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28885052500 # number of overall miss cycles +system.cpu.dcache.avg_refs 333.306600 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 332210000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.423527 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120811 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120811 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37665348 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37665348 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 151786159 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 151786159 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 151786159 # number of overall hits +system.cpu.dcache.overall_hits::total 151786159 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393231 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393231 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1785973 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1785973 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2179204 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2179204 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2179204 # number of overall misses +system.cpu.dcache.overall_misses::total 2179204 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984681000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5984681000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23175803000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23175803000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29160484000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29160484000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29160484000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29160484000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -557,40 +557,40 @@ system.cpu.dcache.demand_accesses::cpu.data 153965363 # system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15228.581088 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15228.581088 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12819.022606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12819.022606 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13253.994201 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13253.994201 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 167214 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 552 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5590 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003434 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003434 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045270 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045270 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014154 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014154 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15219.250263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15219.250263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12976.569635 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12976.569635 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13381.254807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13381.254807 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 191152 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6083 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.913059 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.423968 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 62.222222 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks system.cpu.dcache.writebacks::total 436887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531770 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1531770 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1723952 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1723952 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1723952 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1723952 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 191999 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 191999 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531810 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1531810 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1723809 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1723809 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1723809 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1723809 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -599,14 +599,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3734758000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3734758000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6380334500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6380334500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6380334500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6380334500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643654000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643654000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3783295500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3783295500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6426949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426949500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6426949500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -615,14 +615,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.897611 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.897611 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14694.341820 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14694.341820 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14885.311788 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14885.311788 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 393ed8f87..fd6611525 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133779 # Number of seconds simulated -sim_ticks 133778696500 # Number of ticks simulated -final_tick 133778696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133806 # Number of seconds simulated +sim_ticks 133806308500 # Number of ticks simulated +final_tick 133806308500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160169 # Simulator instruction rate (inst/s) -host_op_rate 160169 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37887208 # Simulator tick rate (ticks/s) -host_mem_usage 273648 # Number of bytes of host memory used -host_seconds 3530.97 # Real time elapsed on the host +host_inst_rate 271409 # Simulator instruction rate (inst/s) +host_op_rate 271409 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64213833 # Simulator tick rate (ticks/s) +host_mem_usage 226532 # Number of bytes of host memory used +host_seconds 2083.76 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1636416 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60864 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67008 # Number of bytes written to this memory -system.physmem.bytes_written::total 67008 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 951 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25569 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26520 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1047 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1047 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 454960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12232262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12687222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 454960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 454960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 500887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 500887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 500887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 454960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12232262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13188109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26520 # Total number of read requests seen -system.physmem.writeReqs 1047 # Total number of write requests seen -system.physmem.cpureqs 27567 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697280 # Total number of bytes read from memory -system.physmem.bytesWritten 67008 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697280 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67008 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636352 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67200 # Number of bytes written to this memory +system.physmem.bytes_written::total 67200 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25568 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26529 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 459649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12229259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12688908 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 459649 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 459649 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 502218 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 502218 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 502218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 459649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12229259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13191127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26529 # Total number of read requests seen +system.physmem.writeReqs 1050 # Total number of write requests seen +system.physmem.cpureqs 27579 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697856 # Total number of bytes read from memory +system.physmem.bytesWritten 67200 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697856 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67200 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1612 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1636 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1685 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1568 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1555 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1704 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1678 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 78 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 55 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 75 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 84 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 54 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 57 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 78 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1632 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1679 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1666 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1684 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 61 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 65 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 58 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 53 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 56 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 64 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 75 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 61 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 133778628000 # Total gap between requests +system.physmem.totGap 133806263000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26520 # Categorize read packet sizes +system.physmem.readPktSize::6 26529 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1047 # categorize write packet sizes +system.physmem.writePktSize::6 1050 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1000 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 8850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1089 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,8 +138,8 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 46 # What write queue length does an incoming req see @@ -150,9 +150,9 @@ system.physmem.wrQLenPdf::8 46 # Wh system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see @@ -161,8 +161,8 @@ system.physmem.wrQLenPdf::19 45 # Wh system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,56 +171,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 650833420 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1266537420 # Sum of mem lat for all requests -system.physmem.totBusLat 106020000 # Total cycles spent in databus access -system.physmem.totBankLat 509684000 # Total cycles spent in bank access -system.physmem.avgQLat 24555.12 # Average queueing delay per request -system.physmem.avgBankLat 19229.73 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 47784.85 # Average memory access latency +system.physmem.totQLat 648232398 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1339932398 # Sum of mem lat for all requests +system.physmem.totBusLat 132570000 # Total cycles spent in databus access +system.physmem.totBankLat 559130000 # Total cycles spent in bank access +system.physmem.avgQLat 24448.68 # Average queueing delay per request +system.physmem.avgBankLat 21088.10 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 50536.79 # Average memory access latency system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.08 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.10 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.37 # Average write queue length over time -system.physmem.readRowHits 18044 # Number of row buffer hits during reads -system.physmem.writeRowHits 53 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 5.06 # Row buffer hit rate for writes -system.physmem.avgGap 4852854.06 # Average gap between requests -system.cpu.branchPred.lookups 76440222 # Number of BP lookups -system.cpu.branchPred.condPredicted 70864810 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2706098 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 43060392 # Number of BTB lookups -system.cpu.branchPred.BTBHits 41933015 # Number of BTB hits +system.physmem.avgWrQLen 10.03 # Average write queue length over time +system.physmem.readRowHits 16972 # Number of row buffer hits during reads +system.physmem.writeRowHits 273 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 26.00 # Row buffer hit rate for writes +system.physmem.avgGap 4851744.55 # Average gap between requests +system.cpu.branchPred.lookups 76500721 # Number of BP lookups +system.cpu.branchPred.condPredicted 70919742 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2718676 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 43116993 # Number of BTB lookups +system.cpu.branchPred.BTBHits 41952631 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.381870 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1604413 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.299529 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1606312 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 122603551 # DTB read hits -system.cpu.dtb.read_misses 28565 # DTB read misses +system.cpu.dtb.read_hits 122623794 # DTB read hits +system.cpu.dtb.read_misses 28860 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 122632116 # DTB read accesses -system.cpu.dtb.write_hits 40753368 # DTB write hits -system.cpu.dtb.write_misses 25574 # DTB write misses +system.cpu.dtb.read_accesses 122652654 # DTB read accesses +system.cpu.dtb.write_hits 40761180 # DTB write hits +system.cpu.dtb.write_misses 25673 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40778942 # DTB write accesses -system.cpu.dtb.data_hits 163356919 # DTB hits -system.cpu.dtb.data_misses 54139 # DTB misses +system.cpu.dtb.write_accesses 40786853 # DTB write accesses +system.cpu.dtb.data_hits 163384974 # DTB hits +system.cpu.dtb.data_misses 54533 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 163411058 # DTB accesses -system.cpu.itb.fetch_hits 65475592 # ITB hits -system.cpu.itb.fetch_misses 42 # ITB misses +system.cpu.dtb.data_accesses 163439507 # DTB accesses +system.cpu.itb.fetch_hits 65534932 # ITB hits +system.cpu.itb.fetch_misses 41 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 65475634 # ITB accesses +system.cpu.itb.fetch_accesses 65534973 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,238 +234,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267557394 # number of cpu cycles simulated +system.cpu.numCycles 267612618 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 67119409 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 699052842 # Number of instructions fetch has processed -system.cpu.fetch.Branches 76440222 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43537428 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 117782486 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11617306 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73490715 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 67186400 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 699453099 # Number of instructions fetch has processed +system.cpu.fetch.Branches 76500721 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43558943 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 117852914 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11666249 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73358963 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1303 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65475592 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 928038 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 267274328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.615488 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.444547 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65534932 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 934826 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267314333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.616594 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.444810 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 149491842 55.93% 55.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10342090 3.87% 59.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11847639 4.43% 64.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10563390 3.95% 68.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7011808 2.62% 70.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2869024 1.07% 71.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3576964 1.34% 73.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3101400 1.16% 74.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68470171 25.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149461419 55.91% 55.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10349982 3.87% 59.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11850266 4.43% 64.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10577716 3.96% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7012506 2.62% 70.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2870690 1.07% 71.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3579816 1.34% 73.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3108437 1.16% 74.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68503501 25.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 267274328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285697 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.612721 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 84240613 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57793701 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102635866 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13724657 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8879491 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3873839 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 920 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 691093913 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3105 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8879491 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 92211740 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12790279 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1241 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 103054645 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50336932 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 680961604 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 408 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38688874 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5430085 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 520709674 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 896990234 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 896987596 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2638 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267314333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285864 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.613678 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 84322022 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57655855 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102751859 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13670665 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8913932 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3876852 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 942 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 691462372 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3197 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8913932 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 92304341 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12773232 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1346 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 103106270 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50215212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 681285072 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 434 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38522944 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5472741 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 520920645 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 897379043 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 897376453 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2590 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 56854785 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 64 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 69 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112289485 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 126970724 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42377686 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14852387 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10147583 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 621083354 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 604563100 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 299815 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 54897951 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29938787 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 267274328 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.261957 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.823661 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 57065756 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 66 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 71 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112077327 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 127005785 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42387861 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14833107 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10089887 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 621266103 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 59 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 604722021 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 299730 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 55073821 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 30009810 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 42 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267314333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.262213 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.825151 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52499760 19.64% 19.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55875325 20.91% 40.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53442699 20.00% 60.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36269586 13.57% 74.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31423380 11.76% 85.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23799839 8.90% 94.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9996979 3.74% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3415050 1.28% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 551710 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52513972 19.65% 19.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55954300 20.93% 40.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53424383 19.99% 60.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36299246 13.58% 74.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31212895 11.68% 85.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23807225 8.91% 94.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10138155 3.79% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3408674 1.28% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 555483 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 267274328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267314333 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2734710 70.93% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 35 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 729519 18.92% 89.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 391400 10.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2798552 71.38% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 39 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 727516 18.56% 89.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 394572 10.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 439055623 72.62% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7072 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 124323040 20.56% 93.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41177317 6.81% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439175234 72.62% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7035 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124352577 20.56% 93.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41187127 6.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 604563100 # Type of FU issued -system.cpu.iq.rate 2.259564 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3855664 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006378 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1480552206 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 675984537 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 596489873 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3801 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2284 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1738 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 608416848 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1916 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12282855 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 604722021 # Type of FU issued +system.cpu.iq.rate 2.259692 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3920679 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006483 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1480975025 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 676343136 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 596595322 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3759 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2270 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1723 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 608640802 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1898 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12279325 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12456682 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 35904 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5518 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2926365 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12491743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36092 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5478 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2936540 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6461 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 52889 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6432 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 54776 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8879491 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1456554 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 192142 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 663913486 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1691538 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 126970724 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42377686 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 56 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 144242 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7408 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5518 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1333964 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1804152 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3138116 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599464075 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 122632263 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5099025 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8913932 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1438086 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 192048 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 664143136 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1694587 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 127005785 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42387861 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 59 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 143884 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7497 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5478 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1342912 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1811100 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3154012 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599591446 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 122652830 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5130575 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 42830076 # number of nop insts executed -system.cpu.iew.exec_refs 163429760 # number of memory reference insts executed -system.cpu.iew.exec_branches 66623337 # Number of branches executed -system.cpu.iew.exec_stores 40797497 # Number of stores executed -system.cpu.iew.exec_rate 2.240506 # Inst execution rate -system.cpu.iew.wb_sent 597426155 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 596491611 # cumulative count of insts written-back -system.cpu.iew.wb_producers 415927297 # num instructions producing a value -system.cpu.iew.wb_consumers 530215795 # num instructions consuming a value +system.cpu.iew.exec_nop 42876974 # number of nop insts executed +system.cpu.iew.exec_refs 163458157 # number of memory reference insts executed +system.cpu.iew.exec_branches 66641389 # Number of branches executed +system.cpu.iew.exec_stores 40805327 # Number of stores executed +system.cpu.iew.exec_rate 2.240520 # Inst execution rate +system.cpu.iew.wb_sent 597536756 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 596597045 # cumulative count of insts written-back +system.cpu.iew.wb_producers 415962909 # num instructions producing a value +system.cpu.iew.wb_consumers 530370743 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.229397 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.784449 # average fanout of values written-back +system.cpu.iew.wb_rate 2.229331 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.784287 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 61932723 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 62162261 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2705240 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258394837 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.329214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.691172 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2717793 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258400401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.329164 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.692856 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 79550578 30.79% 30.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72525012 28.07% 58.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25515345 9.87% 68.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9289171 3.59% 72.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10288497 3.98% 76.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 21029047 8.14% 84.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6874256 2.66% 87.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3694459 1.43% 88.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29628472 11.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79574518 30.80% 30.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72566023 28.08% 58.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25599330 9.91% 68.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9197400 3.56% 72.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10258446 3.97% 76.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20921268 8.10% 84.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6836400 2.65% 87.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3734572 1.45% 88.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29712444 11.50% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258394837 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 258400401 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +476,192 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29628472 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29712444 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 892491662 # The number of ROB reads -system.cpu.rob.rob_writes 1336472901 # The number of ROB writes -system.cpu.timesIdled 34286 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 283066 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 892642792 # The number of ROB reads +system.cpu.rob.rob_writes 1336966756 # The number of ROB writes +system.cpu.timesIdled 34291 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 298285 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.473090 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.473090 # CPI: Total CPI of All Threads -system.cpu.ipc 2.113761 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.113761 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 844970192 # number of integer regfile reads -system.cpu.int_regfile_writes 490533624 # number of integer regfile writes -system.cpu.fp_regfile_reads 397 # number of floating regfile reads +system.cpu.cpi 0.473188 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.473188 # CPI: Total CPI of All Threads +system.cpu.ipc 2.113325 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.113325 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 845166386 # number of integer regfile reads +system.cpu.int_regfile_writes 490617161 # number of integer regfile writes +system.cpu.fp_regfile_reads 389 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 36 # number of replacements -system.cpu.icache.tagsinuse 825.012562 # Cycle average of tags in use -system.cpu.icache.total_refs 65474211 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 965 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67848.923316 # Average number of references to valid blocks. +system.cpu.icache.replacements 41 # number of replacements +system.cpu.icache.tagsinuse 825.582407 # Cycle average of tags in use +system.cpu.icache.total_refs 65533545 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 66939.269663 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 825.012562 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.402838 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.402838 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 65474211 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 65474211 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 65474211 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 65474211 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 65474211 # number of overall hits -system.cpu.icache.overall_hits::total 65474211 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1381 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1381 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1381 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1381 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1381 # number of overall misses -system.cpu.icache.overall_misses::total 1381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 68875500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 68875500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 68875500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 68875500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 68875500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 68875500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65475592 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65475592 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65475592 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65475592 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65475592 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65475592 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 825.582407 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.403116 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.403116 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 65533545 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 65533545 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 65533545 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 65533545 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 65533545 # number of overall hits +system.cpu.icache.overall_hits::total 65533545 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1386 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1386 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1386 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1386 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1386 # number of overall misses +system.cpu.icache.overall_misses::total 1386 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 74542000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 74542000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 74542000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 74542000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 74542000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 74542000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 65534931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 65534931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 65534931 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 65534931 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 65534931 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 65534931 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49873.642288 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49873.642288 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49873.642288 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49873.642288 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49873.642288 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49873.642288 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53782.106782 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53782.106782 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53782.106782 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53782.106782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53782.106782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53782.106782 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 93 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.600000 # 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number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50216500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50216500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50216500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50216500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50216500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50216500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 407 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 407 # 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mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39058.344900 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 85735.098422 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77294.407682 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55726.736889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55726.736889 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39058.344900 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60782.703938 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60003.674321 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39058.344900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60782.703938 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60003.674321 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 1050 # number of writebacks +system.cpu.l2cache.writebacks::total 1050 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4311 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5272 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21257 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21257 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25568 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26529 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 25568 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26529 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41447516 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 363900322 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 405347838 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1236862753 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1236862753 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41447516 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1600763075 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1642210591 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41447516 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1600763075 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1642210591 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981614 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020483 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024933 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083503 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083503 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981614 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054981 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056927 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981614 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054981 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056927 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43129.569199 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84412.044073 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76886.919196 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58186.138825 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58186.138825 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43129.569199 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62608.067702 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61902.468657 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43129.569199 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62608.067702 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61902.468657 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 461041 # number of replacements -system.cpu.dcache.tagsinuse 4090.869171 # Cycle average of tags in use -system.cpu.dcache.total_refs 146891319 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 465137 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 315.802267 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 305775000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4090.869171 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998747 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998747 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 109242892 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 109242892 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37648409 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37648409 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 18 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 18 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 146891301 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 146891301 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 146891301 # number of overall hits -system.cpu.dcache.overall_hits::total 146891301 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1026587 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1026587 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1802912 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1802912 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2829499 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2829499 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2829499 # number of overall misses -system.cpu.dcache.overall_misses::total 2829499 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15441177000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15441177000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25867331616 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25867331616 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 28500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 28500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41308508616 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41308508616 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41308508616 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41308508616 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 110269479 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 110269479 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 460939 # number of replacements +system.cpu.dcache.tagsinuse 4090.899850 # Cycle average of tags in use +system.cpu.dcache.total_refs 146914514 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 465035 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 315.921412 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 301771000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4090.899850 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998755 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998755 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 109265934 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 109265934 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37648563 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37648563 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 17 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 17 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 146914497 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 146914497 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 146914497 # number of overall hits +system.cpu.dcache.overall_hits::total 146914497 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1025246 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1025246 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1802758 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1802758 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2828004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2828004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2828004 # number of overall misses +system.cpu.dcache.overall_misses::total 2828004 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15342477500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15342477500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26169777829 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26169777829 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 37000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 37000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41512255329 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41512255329 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41512255329 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41512255329 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 110291180 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 110291180 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 149720800 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 149720800 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 149720800 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 149720800 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009310 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009310 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045700 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.142857 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.142857 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018899 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018899 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15041.274631 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15041.274631 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14347.528674 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14347.528674 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14599.230682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14599.230682 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 277266 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 17305 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 149742501 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 149742501 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 149742501 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 149742501 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009296 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009296 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045696 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045696 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.190476 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.190476 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018886 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018886 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018886 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018886 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14964.679209 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14964.679209 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14516.522922 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14516.522922 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14678.994559 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14678.994559 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14678.994559 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14678.994559 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 301355 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2673 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17784 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.022306 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 83.545455 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.945288 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 243 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 445099 # number of writebacks -system.cpu.dcache.writebacks::total 445099 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 816026 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 816026 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548336 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1548336 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2364362 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2364362 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2364362 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2364362 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210561 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210561 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254576 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254576 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 465137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 465137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 465137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 465137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2703972000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2703972000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4046409990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4046409990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6750381990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6750381990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6750381990 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6750381990 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 445006 # number of writebacks +system.cpu.dcache.writebacks::total 445006 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 814778 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 814778 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548191 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1548191 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2362969 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2362969 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2362969 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2362969 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210468 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210468 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254567 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254567 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 465035 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 465035 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 465035 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 465035 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2697344500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2697344500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4097543997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4097543997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6794888497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6794888497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6794888497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6794888497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001908 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001908 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003107 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003107 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003107 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003107 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12841.751321 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12841.751321 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15894.703311 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15894.703311 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003106 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003106 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12815.936389 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12815.936389 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16096.131851 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16096.131851 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14611.563639 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14611.563639 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14611.563639 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14611.563639 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 08bc3f5b4..e289c0e8e 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164543 # Number of seconds simulated -sim_ticks 164543008000 # Number of ticks simulated -final_tick 164543008000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164572 # Number of seconds simulated +sim_ticks 164572262000 # Number of ticks simulated +final_tick 164572262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116480 # Simulator instruction rate (inst/s) -host_op_rate 123082 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33621508 # Simulator tick rate (ticks/s) -host_mem_usage 289348 # Number of bytes of host memory used -host_seconds 4893.98 # Real time elapsed on the host +host_inst_rate 164809 # Simulator instruction rate (inst/s) +host_op_rate 174150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47579904 # Simulator tick rate (ticks/s) +host_mem_usage 241928 # Number of bytes of host memory used +host_seconds 3458.86 # Real time elapsed on the host sim_insts 570051585 # Number of instructions simulated sim_ops 602359791 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 46912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1700992 # Number of bytes read from this memory -system.physmem.bytes_read::total 1747904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 46912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 46912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162560 # Number of bytes written to this memory -system.physmem.bytes_written::total 162560 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 733 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26578 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27311 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2540 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2540 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 285105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10337674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10622779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 285105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 285105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 987948 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 987948 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 987948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 285105 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10337674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11610727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27312 # Total number of read requests seen -system.physmem.writeReqs 2540 # Total number of write requests seen -system.physmem.cpureqs 29852 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1747904 # Total number of bytes read from memory -system.physmem.bytesWritten 162560 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1747904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162560 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 47424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1701952 # Number of bytes read from this memory +system.physmem.bytes_read::total 1749376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162432 # Number of bytes written to this memory +system.physmem.bytes_written::total 162432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 741 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26593 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27334 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2538 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2538 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 288165 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10341670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10629835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 288165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 288165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 986995 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 986995 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 986995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 288165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10341670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11616830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27336 # Total number of read requests seen +system.physmem.writeReqs 2538 # Total number of write requests seen +system.physmem.cpureqs 29874 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1749376 # Total number of bytes read from memory +system.physmem.bytesWritten 162432 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1749376 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162432 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1695 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1704 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1673 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1741 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1759 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis +system.physmem.perBankRdReqs::1 1726 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1726 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1735 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1761 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1742 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1686 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 160 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 164542992000 # Total gap between requests +system.physmem.totGap 164572246000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27312 # Categorize read packet sizes +system.physmem.readPktSize::6 27336 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2540 # categorize write packet sizes +system.physmem.writePktSize::6 2538 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 785 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,16 +138,16 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see @@ -161,8 +161,8 @@ system.physmem.wrQLenPdf::19 110 # Wh system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,36 +171,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 954202972 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1658730972 # Sum of mem lat for all requests -system.physmem.totBusLat 109248000 # Total cycles spent in databus access -system.physmem.totBankLat 595280000 # Total cycles spent in bank access -system.physmem.avgQLat 34937.13 # Average queueing delay per request -system.physmem.avgBankLat 21795.55 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 60732.68 # Average memory access latency -system.physmem.avgRdBW 10.62 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 921366434 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1672075184 # Sum of mem lat for all requests +system.physmem.totBusLat 136675000 # Total cycles spent in databus access +system.physmem.totBankLat 614033750 # Total cycles spent in bank access +system.physmem.avgQLat 33705.24 # Average queueing delay per request +system.physmem.avgBankLat 22462.46 # Average bank access latency per request +system.physmem.avgBusLat 4999.82 # Average bus latency per request +system.physmem.avgMemAccLat 61167.51 # Average memory access latency +system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 10.62 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 7.51 # Average write queue length over time -system.physmem.readRowHits 17750 # Number of row buffer hits during reads -system.physmem.writeRowHits 1096 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.99 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.15 # Row buffer hit rate for writes -system.physmem.avgGap 5511958.73 # Average gap between requests -system.cpu.branchPred.lookups 85130885 # Number of BP lookups -system.cpu.branchPred.condPredicted 79914937 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2339051 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 47115734 # Number of BTB lookups -system.cpu.branchPred.BTBHits 46860934 # Number of BTB hits +system.physmem.avgWrQLen 7.98 # Average write queue length over time +system.physmem.readRowHits 16887 # Number of row buffer hits during reads +system.physmem.writeRowHits 1046 # Number of row buffer hits during writes +system.physmem.readRowHitRate 61.78 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.21 # Row buffer hit rate for writes +system.physmem.avgGap 5508878.82 # Average gap between requests +system.cpu.branchPred.lookups 85156760 # Number of BP lookups +system.cpu.branchPred.condPredicted 79937555 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2342179 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 47221599 # Number of BTB lookups +system.cpu.branchPred.BTBHits 46882126 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.459204 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1427305 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 879 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.281107 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1427254 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1090 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,134 +244,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329086017 # number of cpu cycles simulated +system.cpu.numCycles 329144525 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 68482650 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 666733796 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85130885 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48288239 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 129602885 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13082707 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119327277 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 198 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 67069040 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 754631 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 328130780 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.165288 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.193984 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 68500133 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 666893560 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85156760 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48309380 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 129633878 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13101459 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119325440 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 311 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 67084243 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 755399 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 328191292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.165364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.193928 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 198528126 60.50% 60.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20911347 6.37% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4965496 1.51% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14342607 4.37% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8889042 2.71% 75.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9432606 2.87% 78.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4398382 1.34% 79.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5787527 1.76% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 60875647 18.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198557643 60.50% 60.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20911639 6.37% 66.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4968720 1.51% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14346044 4.37% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8890886 2.71% 75.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9446619 2.88% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4399795 1.34% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5788532 1.76% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 60881414 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 328130780 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258689 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.026017 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 92913811 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96211222 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 107901766 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20387668 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10716313 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4735353 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1507 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703148359 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5732 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10716313 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107108772 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14420824 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 39598 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114018818 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81826455 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 694730633 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59350869 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20332423 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 690 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 721206841 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3230143140 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3230143012 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 328191292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258721 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.026142 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92969239 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96174869 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 107931491 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20385682 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10730011 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4738020 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1580 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703286632 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5586 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10730011 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107159029 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14373843 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 39888 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114052351 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81836170 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 694854437 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59359193 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20344162 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 721334030 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3230715755 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3230715627 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 93789468 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1631 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1577 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 170614097 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172186244 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80451329 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21497797 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28523197 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 679922328 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2842 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 645571900 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1371428 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 77382290 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 193030922 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 138 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 328130780 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.967423 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.726248 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 93916657 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1707 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1652 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 170570480 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172204690 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80467392 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21722432 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29158581 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 680011931 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2919 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 645607270 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1367531 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 77472778 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 193408701 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 215 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 328191292 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.967168 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.722204 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68155781 20.77% 20.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85368264 26.02% 46.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75828661 23.11% 69.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40814489 12.44% 82.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28806063 8.78% 91.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14910916 4.54% 95.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5593541 1.70% 97.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6461751 1.97% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2191314 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68107234 20.75% 20.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85141417 25.94% 46.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76162034 23.21% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40819071 12.44% 82.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28853170 8.79% 91.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14914630 4.54% 95.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5559324 1.69% 97.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6732498 2.05% 99.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1901914 0.58% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 328130780 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328191292 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 217275 5.77% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2690091 71.47% 77.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 856746 22.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 216791 5.75% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2693843 71.39% 77.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 862775 22.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403353378 62.48% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6568 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403382320 62.48% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6572 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued @@ -399,84 +399,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 165552451 25.64% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76659500 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 165566556 25.65% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76651819 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 645571900 # Type of FU issued -system.cpu.iq.rate 1.961712 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3764112 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005831 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624410084 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 757319559 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 637543970 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 645607270 # Type of FU issued +system.cpu.iq.rate 1.961470 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3773409 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005845 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624546736 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 757499752 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 637553210 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 649335992 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 649380659 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30371258 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30362769 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23233651 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 124604 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12357 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10230316 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23252097 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 121645 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12371 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10246379 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12884 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 32539 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12896 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 35853 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10716313 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 798788 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 92055 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 679928215 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 686727 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172186244 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80451329 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1514 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 33028 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15856 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12357 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1355593 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1460304 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2815897 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 641504035 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163487420 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4067865 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10730011 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 795888 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 91006 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 680017934 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 687807 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172204690 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80467392 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1591 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 32670 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15237 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12371 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1357657 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1460843 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2818500 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 641514820 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163491606 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4092450 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3045 # number of nop insts executed -system.cpu.iew.exec_refs 239375677 # number of memory reference insts executed -system.cpu.iew.exec_branches 74669000 # Number of branches executed -system.cpu.iew.exec_stores 75888257 # Number of stores executed -system.cpu.iew.exec_rate 1.949351 # Inst execution rate -system.cpu.iew.wb_sent 638951120 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 637543986 # cumulative count of insts written-back -system.cpu.iew.wb_producers 418515101 # num instructions producing a value -system.cpu.iew.wb_consumers 649819096 # num instructions consuming a value +system.cpu.iew.exec_nop 3084 # number of nop insts executed +system.cpu.iew.exec_refs 239364786 # number of memory reference insts executed +system.cpu.iew.exec_branches 74674061 # Number of branches executed +system.cpu.iew.exec_stores 75873180 # Number of stores executed +system.cpu.iew.exec_rate 1.949037 # Inst execution rate +system.cpu.iew.wb_sent 638961643 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 637553226 # cumulative count of insts written-back +system.cpu.iew.wb_producers 418732313 # num instructions producing a value +system.cpu.iew.wb_consumers 650059572 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937317 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644049 # average fanout of values written-back +system.cpu.iew.wb_rate 1.937001 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644145 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 77576557 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 77666777 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2337624 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 317414467 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.897708 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.237617 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2340669 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 317461281 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.897428 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.237399 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93227454 29.37% 29.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104339541 32.87% 62.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42982023 13.54% 75.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8785495 2.77% 78.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25936003 8.17% 86.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12920810 4.07% 90.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7630828 2.40% 93.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1171764 0.37% 93.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20420549 6.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93255759 29.38% 29.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104348924 32.87% 62.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42985847 13.54% 75.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8791848 2.77% 78.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25959048 8.18% 86.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12901404 4.06% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7629324 2.40% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1168492 0.37% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20420635 6.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 317414467 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 317461281 # Number of insts commited each cycle system.cpu.commit.committedInsts 570051636 # Number of instructions committed system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,195 +487,195 @@ system.cpu.commit.branches 70892524 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 533522631 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20420549 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20420635 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 976929705 # The number of ROB reads -system.cpu.rob.rob_writes 1370620821 # The number of ROB writes -system.cpu.timesIdled 41180 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 955237 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 977066653 # The number of ROB reads +system.cpu.rob.rob_writes 1370815087 # The number of ROB writes +system.cpu.timesIdled 44013 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 953233 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 570051585 # Number of Instructions Simulated system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated -system.cpu.cpi 0.577292 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.577292 # CPI: Total CPI of All Threads -system.cpu.ipc 1.732227 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.732227 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3204271897 # number of integer regfile reads -system.cpu.int_regfile_writes 663022837 # number of integer regfile writes +system.cpu.cpi 0.577394 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.577394 # CPI: Total CPI of All Threads +system.cpu.ipc 1.731919 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.731919 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3204307958 # number of integer regfile reads +system.cpu.int_regfile_writes 663049374 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 234769906 # number of misc regfile reads +system.cpu.misc_regfile_reads 234758339 # number of misc regfile reads system.cpu.misc_regfile_writes 2656 # number of misc regfile writes -system.cpu.icache.replacements 58 # number of replacements -system.cpu.icache.tagsinuse 683.079303 # Cycle average of tags in use -system.cpu.icache.total_refs 67067899 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 817 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 82090.451652 # Average number of references to valid blocks. +system.cpu.icache.replacements 66 # number of replacements +system.cpu.icache.tagsinuse 690.513263 # Cycle average of tags in use +system.cpu.icache.total_refs 67083102 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 830 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 80823.014458 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 683.079303 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.333535 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.333535 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67067899 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67067899 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67067899 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67067899 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67067899 # number of overall hits -system.cpu.icache.overall_hits::total 67067899 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 690.513263 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.337165 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.337165 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67083102 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67083102 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67083102 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67083102 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67083102 # number of overall hits +system.cpu.icache.overall_hits::total 67083102 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses system.cpu.icache.overall_misses::total 1141 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51270999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51270999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51270999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51270999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51270999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51270999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67069040 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67069040 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67069040 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67069040 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67069040 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67069040 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 54478999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 54478999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 54478999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 54478999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 54478999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 54478999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67084243 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67084243 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67084243 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67084243 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67084243 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67084243 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44935.143734 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44935.143734 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44935.143734 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44935.143734 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44935.143734 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44935.143734 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 401 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47746.712533 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47746.712533 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47746.712533 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47746.712533 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47746.712533 # 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number of writebacks -system.cpu.l2cache.writebacks::total 2540 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 2538 # number of writebacks +system.cpu.l2cache.writebacks::total 2538 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 9 # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26579 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27312 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27884656 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 667944528 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695829184 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1273842866 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1273842866 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27884656 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1941787394 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1969672050 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27884656 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1941787394 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1969672050 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.896088 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024247 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027843 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088160 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088160 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.896088 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059773 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.061308 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.896088 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059773 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.061308 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38041.822647 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139474.739612 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126010.355668 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58459.975493 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58459.975493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38041.822647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73057.202829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72117.459359 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38041.822647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73057.202829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72117.459359 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 741 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4804 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5545 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21791 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1310031171 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31149679 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1937942647 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1969092326 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31149679 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1937942647 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1969092326 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024312 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027945 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088162 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088162 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061347 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061347 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42037.353576 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130705.969192 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118856.835888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60117.992336 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60117.992336 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42037.353576 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72032.935543 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42037.353576 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72032.935543 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440572 # number of replacements -system.cpu.dcache.tagsinuse 4091.500520 # Cycle average of tags in use -system.cpu.dcache.total_refs 197561073 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444668 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 444.288937 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 320822000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4091.500520 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998901 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998901 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 131514845 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 131514845 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 66043576 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 66043576 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1323 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1323 # number of LoadLockedReq hits +system.cpu.dcache.replacements 440669 # number of replacements +system.cpu.dcache.tagsinuse 4091.484070 # Cycle average of tags in use +system.cpu.dcache.total_refs 197567614 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444765 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 444.206747 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 314058000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4091.484070 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998897 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998897 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 131523721 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 131523721 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 66041240 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 66041240 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1324 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1324 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 197558421 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 197558421 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 197558421 # number of overall hits -system.cpu.dcache.overall_hits::total 197558421 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 341798 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 341798 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3373955 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3373955 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 20 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 20 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3715753 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3715753 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3715753 # number of overall misses -system.cpu.dcache.overall_misses::total 3715753 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5154955000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5154955000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 40277017700 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 40277017700 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 312000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 312000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45431972700 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45431972700 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45431972700 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45431972700 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 131856643 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 131856643 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 197564961 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 197564961 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 197564961 # number of overall hits +system.cpu.dcache.overall_hits::total 197564961 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 341919 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 341919 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3376291 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3376291 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3718210 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3718210 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3718210 # number of overall misses +system.cpu.dcache.overall_misses::total 3718210 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5073572500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5073572500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 40705228766 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 40705228766 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 337500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 337500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45778801266 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45778801266 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45778801266 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45778801266 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131865640 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131865640 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1343 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1343 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1346 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1346 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201274174 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201274174 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201274174 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201274174 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002592 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002592 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048604 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.048604 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.014892 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.014892 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018461 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018461 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018461 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018461 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15081.875845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15081.875845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11937.627414 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 11937.627414 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15600 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15600 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12226.854880 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12226.854880 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12226.854880 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12226.854880 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 132982 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4828 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.543911 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 201283171 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201283171 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201283171 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201283171 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002593 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002593 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048637 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.048637 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016345 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016345 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018473 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018473 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018473 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018473 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.521697 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.521697 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12056.196805 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12056.196805 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15340.909091 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15340.909091 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12312.053721 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12312.053721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12312.053721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12312.053721 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 148065 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 30 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4947 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.930261 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421606 # number of writebacks -system.cpu.dcache.writebacks::total 421606 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144292 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 144292 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3126791 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3126791 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 20 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 20 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3271083 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3271083 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3271083 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3271083 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197506 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197506 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247164 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247164 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444670 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444670 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444670 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444670 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2876994000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2876994000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4061058256 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4061058256 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6938052256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6938052256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6938052256 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6938052256 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 421643 # number of writebacks +system.cpu.dcache.writebacks::total 421643 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144320 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 144320 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3129122 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3129122 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3273442 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3273442 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3273442 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3273442 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197599 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197599 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247169 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247169 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444768 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444768 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444768 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444768 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836417500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836417500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096422821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096422821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932840321 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6932840321 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932840321 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6932840321 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003561 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14566.615698 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14566.615698 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16430.622000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16430.622000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15602.699206 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15602.699206 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15602.699206 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15602.699206 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.412219 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.412219 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16573.368104 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16573.368104 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 6eebaa49a..a9ed274c0 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387280 # Number of seconds simulated -sim_ticks 387279743500 # Number of ticks simulated -final_tick 387279743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387316 # Number of seconds simulated +sim_ticks 387315507500 # Number of ticks simulated +final_tick 387315507500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131929 # Simulator instruction rate (inst/s) -host_op_rate 132344 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36464205 # Simulator tick rate (ticks/s) -host_mem_usage 283820 # Number of bytes of host memory used -host_seconds 10620.82 # Real time elapsed on the host +host_inst_rate 205717 # Simulator instruction rate (inst/s) +host_op_rate 206366 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56864239 # Simulator tick rate (ticks/s) +host_mem_usage 235456 # Number of bytes of host memory used +host_seconds 6811.23 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678400 # Number of bytes read from this memory -system.physmem.bytes_read::total 1754816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76416 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 76544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678528 # Number of bytes read from this memory +system.physmem.bytes_read::total 1755072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76544 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1194 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26225 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1196 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26227 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27423 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4333818 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4531133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197315 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197315 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 418591 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 418591 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 418591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4333818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4949724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27420 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 197627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4333749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4531375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418553 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418553 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4333749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4949928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27424 # Total number of read requests seen system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29953 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1754816 # Total number of bytes read from memory +system.physmem.cpureqs 29957 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1755072 # Total number of bytes read from memory system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1754816 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1755072 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1698 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1803 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1696 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1621 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1660 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1721 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1697 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1769 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1755 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1628 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 166 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387279715500 # Total gap between requests +system.physmem.totGap 387315479500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27420 # Categorize read packet sizes +system.physmem.readPktSize::6 27424 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 8259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5215 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 7981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 974 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,8 +138,8 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 107 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see @@ -161,8 +161,8 @@ system.physmem.wrQLenPdf::19 110 # Wh system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,267 +171,267 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 724473296 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1405549296 # Sum of mem lat for all requests -system.physmem.totBusLat 109680000 # Total cycles spent in databus access -system.physmem.totBankLat 571396000 # Total cycles spent in bank access -system.physmem.avgQLat 26421.35 # Average queueing delay per request -system.physmem.avgBankLat 20838.66 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 51260.00 # Average memory access latency +system.physmem.totQLat 713274952 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1439334952 # Sum of mem lat for all requests +system.physmem.totBusLat 137120000 # Total cycles spent in databus access +system.physmem.totBankLat 588940000 # Total cycles spent in bank access +system.physmem.avgQLat 26009.15 # Average queueing delay per request +system.physmem.avgBankLat 21475.35 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 52484.50 # Average memory access latency system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.42 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 17.06 # Average write queue length over time -system.physmem.readRowHits 18324 # Number of row buffer hits during reads -system.physmem.writeRowHits 1098 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.35 # Row buffer hit rate for writes -system.physmem.avgGap 12929580.19 # Average gap between requests -system.cpu.branchPred.lookups 97757265 # Number of BP lookups -system.cpu.branchPred.condPredicted 88048400 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 3615880 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 65812942 # Number of BTB lookups -system.cpu.branchPred.BTBHits 65493412 # Number of BTB hits +system.physmem.avgWrQLen 16.51 # Average write queue length over time +system.physmem.readRowHits 17585 # Number of row buffer hits during reads +system.physmem.writeRowHits 1048 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.37 # Row buffer hit rate for writes +system.physmem.avgGap 12929047.62 # Average gap between requests +system.cpu.branchPred.lookups 97759655 # Number of BP lookups +system.cpu.branchPred.condPredicted 88050231 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 3614520 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 65786552 # Number of BTB lookups +system.cpu.branchPred.BTBHits 65492883 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.514488 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1346 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.553603 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1341 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 221 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774559488 # number of cpu cycles simulated +system.cpu.numCycles 774631016 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 164857001 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1642241879 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97757265 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65494758 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 329201347 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20830567 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 263300608 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2484 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 164855721 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642251558 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97759655 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65494224 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329204399 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20834739 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263342259 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2502 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161939590 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 736919 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774350695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126792 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 161937023 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 736247 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774398184 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126696 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146676 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 445149348 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74062635 9.56% 67.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37899346 4.89% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9077460 1.17% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28106060 3.63% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18772938 2.42% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11486101 1.48% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3791039 0.49% 81.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146005768 18.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445193785 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74062525 9.56% 67.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37899229 4.89% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9077552 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28106227 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18772117 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11485912 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3791430 0.49% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146009407 18.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774350695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126210 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.120227 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 215923264 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214411776 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 284212483 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42813992 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16989180 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1636523306 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16989180 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 239767996 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36725834 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52426044 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302047092 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126394549 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1625641256 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 163 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30927570 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73422293 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3124815 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1356325471 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2746325758 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2712253189 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34072569 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774398184 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126202 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.120044 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 215922553 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214452390 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284209898 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42820116 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16993227 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636550752 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16993227 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239771948 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36701097 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52424917 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302039391 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126467604 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625687860 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30927407 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73464560 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3152152 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356365192 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746429093 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712307786 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34121307 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 111555032 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2644888 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2664020 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271706062 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 436927389 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 179744218 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 254493315 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83217297 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1512489363 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2610612 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1459355655 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 53704 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 109193723 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 130058810 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 366941 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774350695 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.884619 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.431536 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111594753 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2643942 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2663506 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271777312 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436941235 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179754378 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254555015 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 82904621 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512542697 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2609193 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459339312 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53583 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109245499 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130204517 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 365522 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774398184 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.431065 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145647727 18.81% 18.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184570267 23.84% 42.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 209695290 27.08% 69.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131219118 16.95% 86.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70710319 9.13% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20417492 2.64% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8005951 1.03% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3903236 0.50% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181295 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145558409 18.80% 18.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184658706 23.85% 42.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209828049 27.10% 69.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131187469 16.94% 86.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70686123 9.13% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20416273 2.64% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7987184 1.03% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3894628 0.50% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181343 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774350695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774398184 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 116724 6.93% 6.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95410 5.66% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1152580 68.43% 81.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 319525 18.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 118946 7.04% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95273 5.64% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1158517 68.57% 81.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 316903 18.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 866464141 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866474644 59.37% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2644770 0.18% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419120072 28.72% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171126672 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644797 0.18% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419098125 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171121746 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1459355655 # Type of FU issued -system.cpu.iq.rate 1.884110 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1684239 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001154 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3676971209 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1615339802 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1443231270 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17828739 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9193054 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8547507 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1451917046 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9122848 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215321036 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459339312 # Type of FU issued +system.cpu.iq.rate 1.883915 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1689639 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001158 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3676979008 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615425319 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443226704 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17841022 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9210458 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8545776 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451900530 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9128421 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215265115 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34414546 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 58846 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 246003 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12896076 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34428392 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 58884 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 245184 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12906236 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3349 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 91624 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3305 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 101102 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16989180 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3081240 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 246114 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1608786135 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4123964 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 436927389 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 179744218 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2527628 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 148187 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1651 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 246003 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2270880 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1473539 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3744419 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1454037467 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 416573795 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5318188 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16993227 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3018866 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 247688 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608835504 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4126277 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436941235 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179754378 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2526244 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 149012 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1899 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 245184 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2269311 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1473063 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3742374 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454021381 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416550474 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5317931 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 93686160 # number of nop insts executed -system.cpu.iew.exec_refs 587024674 # number of memory reference insts executed -system.cpu.iew.exec_branches 89036390 # Number of branches executed -system.cpu.iew.exec_stores 170450879 # Number of stores executed -system.cpu.iew.exec_rate 1.877244 # Inst execution rate -system.cpu.iew.wb_sent 1452666848 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1451778777 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1153445523 # num instructions producing a value -system.cpu.iew.wb_consumers 1204705379 # num instructions consuming a value +system.cpu.iew.exec_nop 93683614 # number of nop insts executed +system.cpu.iew.exec_refs 586997386 # number of memory reference insts executed +system.cpu.iew.exec_branches 89036634 # Number of branches executed +system.cpu.iew.exec_stores 170446912 # Number of stores executed +system.cpu.iew.exec_rate 1.877050 # Inst execution rate +system.cpu.iew.wb_sent 1452648479 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451772480 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153427719 # num instructions producing a value +system.cpu.iew.wb_consumers 1204682131 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.874328 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957450 # average fanout of values written-back +system.cpu.iew.wb_rate 1.874147 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957454 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119167265 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119216890 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3615880 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757361515 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.966727 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509795 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3614520 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757404957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966614 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509691 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 240009654 31.69% 31.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 275743732 36.41% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42570119 5.62% 73.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54687779 7.22% 80.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19671272 2.60% 83.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13286277 1.75% 85.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30573058 4.04% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10535838 1.39% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70283786 9.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 239974569 31.68% 31.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275852046 36.42% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42571811 5.62% 73.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54691782 7.22% 80.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19624283 2.59% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13282059 1.75% 85.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30580381 4.04% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10561653 1.39% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70266373 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757361515 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757404957 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -442,192 +442,192 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70283786 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70266373 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2295703406 # The number of ROB reads -system.cpu.rob.rob_writes 3234392884 # The number of ROB writes -system.cpu.timesIdled 26078 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 208793 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295813886 # The number of ROB reads +system.cpu.rob.rob_writes 3234496299 # The number of ROB writes +system.cpu.timesIdled 25967 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 232832 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552787 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552787 # CPI: Total CPI of All Threads -system.cpu.ipc 1.809014 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.809014 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1979140277 # number of integer regfile reads -system.cpu.int_regfile_writes 1275189089 # number of integer regfile writes -system.cpu.fp_regfile_reads 16965348 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491584 # number of floating regfile writes -system.cpu.misc_regfile_reads 592679771 # number of misc regfile reads +system.cpu.cpi 0.552838 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552838 # CPI: Total CPI of All Threads +system.cpu.ipc 1.808847 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.808847 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979103244 # number of integer regfile reads +system.cpu.int_regfile_writes 1275174788 # number of integer regfile writes +system.cpu.fp_regfile_reads 16962430 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491706 # number of floating regfile writes +system.cpu.misc_regfile_reads 592650972 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 200 # number of replacements -system.cpu.icache.tagsinuse 1035.695786 # Cycle average of tags in use -system.cpu.icache.total_refs 161937647 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 121029.631540 # Average number of references to valid blocks. +system.cpu.icache.replacements 197 # number of replacements +system.cpu.icache.tagsinuse 1035.237714 # Cycle average of tags in use +system.cpu.icache.total_refs 161935084 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1336 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 121208.895210 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.695786 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505711 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505711 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161937647 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161937647 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161937647 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161937647 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161937647 # number of overall hits -system.cpu.icache.overall_hits::total 161937647 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1943 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1943 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1943 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1943 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1943 # number of overall misses -system.cpu.icache.overall_misses::total 1943 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 81333500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 81333500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 81333500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 81333500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 81333500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 81333500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161939590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161939590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161939590 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161939590 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161939590 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161939590 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1035.237714 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505487 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505487 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161935084 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161935084 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161935084 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161935084 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161935084 # number of overall hits +system.cpu.icache.overall_hits::total 161935084 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1939 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1939 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1939 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1939 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1939 # number of overall misses +system.cpu.icache.overall_misses::total 1939 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 84566500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 84566500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 84566500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 84566500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 84566500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 84566500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161937023 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161937023 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161937023 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161937023 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161937023 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161937023 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41859.752959 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41859.752959 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41859.752959 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41859.752959 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41859.752959 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41859.752959 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43613.460547 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43613.460547 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43613.460547 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43613.460547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43613.460547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43613.460547 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1339 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1339 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1339 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1339 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1339 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1339 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59309500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59309500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59309500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59309500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59309500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59309500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 602 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 602 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 602 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 602 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 602 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 602 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1337 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1337 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1337 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1337 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1337 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1337 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62189000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 62189000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62189000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 62189000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62189000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 62189000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44293.876027 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44293.876027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44293.876027 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 44293.876027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44293.876027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 44293.876027 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46513.836948 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46513.836948 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46513.836948 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 46513.836948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46513.836948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 46513.836948 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22451.919806 # Cycle average of tags in use -system.cpu.l2cache.total_refs 550398 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24266 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.681859 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22451.693912 # Cycle average of tags in use +system.cpu.l2cache.total_refs 550222 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24270 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.670869 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20744.013315 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1060.728994 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 647.177496 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633057 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.032371 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019750 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.685178 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 144 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 196423 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 196567 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 443928 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 443928 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 240651 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 240651 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 144 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 437074 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31927965942 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 122000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 122000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46916057442 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46916057442 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46916057442 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46916057442 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201141784 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201141784 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2814422 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2814422 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2814422 # number of overall misses +system.cpu.dcache.overall_misses::total 2814422 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14739603500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14739603500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31907348686 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31907348686 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 150000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 150000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46646952186 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46646952186 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46646952186 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46646952186 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201164550 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201164550 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 367988600 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 367988600 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 367988600 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 367988600 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004612 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004612 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368011366 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368011366 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368011366 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368011366 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004589 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004589 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011336 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.011336 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007661 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007661 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007661 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007661 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16156.340312 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16156.340312 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16881.108261 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16881.108261 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 17428.571429 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 17428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16642.600778 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16642.600778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16642.600778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16642.600778 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 573681 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35664 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.085717 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.007648 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007648 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007648 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007648 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15968.283038 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15968.283038 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16869.993336 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16869.993336 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 21428.571429 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 21428.571429 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16574.256521 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16574.256521 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16574.256521 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16574.256521 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 590116 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35661 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.547938 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443928 # number of writebacks -system.cpu.dcache.writebacks::total 443928 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 726830 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 726830 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628912 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1628912 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2355742 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2355742 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2355742 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2355742 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200861 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200861 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262431 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262431 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 443933 # number of writebacks +system.cpu.dcache.writebacks::total 443933 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722205 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 722205 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628938 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628938 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2351143 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2351143 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2351143 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2351143 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200850 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200850 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262429 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262429 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 463292 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 463292 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 463292 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 463292 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2635998000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2635998000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319921000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319921000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 108000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 108000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6955919000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6955919000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6955919000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6955919000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 463279 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463279 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463279 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463279 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2612152000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2612152000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357934500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357934500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 136000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 136000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6970086500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6970086500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6970086500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6970086500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000998 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses @@ -800,16 +800,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13123.493361 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13123.493361 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16461.168841 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16461.168841 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 15428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 15428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15014.114209 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15014.114209 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15014.114209 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15014.114209 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.486682 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.486682 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16606.146805 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16606.146805 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 19428.571429 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 19428.571429 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15045.116442 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15045.116442 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15045.116442 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15045.116442 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 3548dbe1a..dc034cfd1 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,83 +1,83 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.607446 # Number of seconds simulated -sim_ticks 607445544000 # Number of ticks simulated -final_tick 607445544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.607292 # Number of seconds simulated +sim_ticks 607292111000 # Number of ticks simulated +final_tick 607292111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56942 # Simulator instruction rate (inst/s) -host_op_rate 104918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39304494 # Simulator tick rate (ticks/s) -host_mem_usage 295872 # Number of bytes of host memory used -host_seconds 15454.86 # Real time elapsed on the host +host_inst_rate 91190 # Simulator instruction rate (inst/s) +host_op_rate 168022 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62928697 # Simulator tick rate (ticks/s) +host_mem_usage 248736 # Number of bytes of host memory used +host_seconds 9650.48 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 57728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 57664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1693184 # Number of bytes read from this memory -system.physmem.bytes_read::total 1750912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 57728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 57728 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 1750848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 57664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 57664 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162176 # Number of bytes written to this memory system.physmem.bytes_written::total 162176 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 902 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 901 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 26456 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27358 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27357 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2534 # Number of write requests responded to by this memory system.physmem.num_writes::total 2534 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2787384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2882418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95034 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95034 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 266980 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 266980 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 266980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2787384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3149398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 94953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2788088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2883041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 267048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 267048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 267048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2788088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3150089 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 27359 # Total number of read requests seen system.physmem.writeReqs 2534 # Total number of write requests seen system.physmem.cpureqs 29893 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1750912 # Total number of bytes read from memory +system.physmem.bytesRead 1750848 # Total number of bytes read from memory system.physmem.bytesWritten 162176 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1750912 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1750848 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162176 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1747 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1779 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1776 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1742 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1655 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1714 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1701 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1664 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1638 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1692 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 156 # Track writes on a per bank basis +system.physmem.perBankRdReqs::9 1708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1730 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1739 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1728 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1750 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1735 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 159 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 607445530000 # Total gap between requests +system.physmem.totGap 607292095000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 26894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 26892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -171,265 +171,265 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 68456669 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 822256669 # Sum of mem lat for all requests -system.physmem.totBusLat 109436000 # Total cycles spent in databus access -system.physmem.totBankLat 644364000 # Total cycles spent in bank access -system.physmem.avgQLat 2502.16 # Average queueing delay per request -system.physmem.avgBankLat 23552.18 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30054.34 # Average memory access latency +system.physmem.totQLat 90448613 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 895548613 # Sum of mem lat for all requests +system.physmem.totBusLat 136795000 # Total cycles spent in databus access +system.physmem.totBankLat 668305000 # Total cycles spent in bank access +system.physmem.avgQLat 3305.99 # Average queueing delay per request +system.physmem.avgBankLat 24427.25 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 32733.24 # Average memory access latency system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.27 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 6.29 # Average write queue length over time -system.physmem.readRowHits 17697 # Number of row buffer hits during reads -system.physmem.writeRowHits 1084 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 42.78 # Row buffer hit rate for writes -system.physmem.avgGap 20320661.36 # Average gap between requests -system.cpu.branchPred.lookups 158385701 # Number of BP lookups -system.cpu.branchPred.condPredicted 158385701 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 26390414 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 84292336 # Number of BTB lookups -system.cpu.branchPred.BTBHits 84079165 # Number of BTB hits +system.physmem.avgWrQLen 6.24 # Average write queue length over time +system.physmem.readRowHits 16426 # Number of row buffer hits during reads +system.physmem.writeRowHits 1032 # Number of row buffer hits during writes +system.physmem.readRowHitRate 60.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.73 # Row buffer hit rate for writes +system.physmem.avgGap 20315528.55 # Average gap between requests +system.cpu.branchPred.lookups 158482804 # Number of BP lookups +system.cpu.branchPred.condPredicted 158482804 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 26384558 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 84639114 # Number of BTB lookups +system.cpu.branchPred.BTBHits 84422216 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.747105 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 99.743738 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1214891089 # number of cpu cycles simulated +system.cpu.numCycles 1214584223 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 179135725 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1458430747 # Number of instructions fetch has processed -system.cpu.fetch.Branches 158385701 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 84079165 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 399080479 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88232216 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 574634441 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 381 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 187842503 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11743851 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1214538070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.059666 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.253312 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 179034165 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1457747721 # Number of instructions fetch has processed +system.cpu.fetch.Branches 158482804 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 84422216 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 399024262 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88084887 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 574618713 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 378 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 188004827 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11985682 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1214221440 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.059311 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.252911 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 822675212 67.74% 67.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26883309 2.21% 69.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 13192065 1.09% 71.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20566257 1.69% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26639433 2.19% 74.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18282936 1.51% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31338155 2.58% 79.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39109954 3.22% 82.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 215850749 17.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 822415344 67.73% 67.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26978129 2.22% 69.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 13144140 1.08% 71.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20617690 1.70% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26634807 2.19% 74.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18232650 1.50% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31447933 2.59% 79.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39056021 3.22% 82.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 215694726 17.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1214538070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.130370 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.200462 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 288247470 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 497953948 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 274080522 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92569137 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 61686993 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2343830219 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 61686993 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 336887109 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124143936 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2487 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 304057721 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 387759824 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2248180627 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 354 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242798221 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120202889 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2618438730 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5723603734 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5723598334 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5400 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1214221440 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130483 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.200203 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 288175293 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 497913619 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 274106217 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92482436 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 61543875 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2343534245 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 61543875 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 336850045 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124204658 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2567 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303948664 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387671631 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2247678746 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 360 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242705543 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120202916 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2618040036 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5722358621 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5722353197 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5424 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895258 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 731543472 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 731144778 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 87 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 731379517 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 532059001 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 219301341 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 342202544 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144686488 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1994506429 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 288 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1784080761 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 243450 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 372613756 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 761627172 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 239 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1214538070 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.468938 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.421549 # Number of insts issued each cycle +system.cpu.rename.skidInsts 731406447 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 531670409 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 219217246 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 342048419 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144614488 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1993488562 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1783952231 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 274040 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 371594187 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 759078017 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 237 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1214221440 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.469215 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.421905 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 360345169 29.67% 29.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 364336445 30.00% 59.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234287346 19.29% 78.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141446603 11.65% 90.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60702765 5.00% 95.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39742301 3.27% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 11032116 0.91% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2048046 0.17% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 597279 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360233763 29.67% 29.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 364161192 29.99% 59.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234288879 19.30% 78.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141409866 11.65% 90.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60623194 4.99% 95.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39782569 3.28% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11078669 0.91% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2040416 0.17% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 602892 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1214538070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1214221440 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 437572 15.09% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2259609 77.90% 92.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 203424 7.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 459684 15.86% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2241246 77.33% 93.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 197213 6.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812462 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1065847679 59.74% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 478866421 26.84% 89.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192554199 10.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812327 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065713813 59.74% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 478893732 26.84% 89.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192532359 10.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1784080761 # Type of FU issued -system.cpu.iq.rate 1.468511 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2900605 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001626 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4785843297 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2367295034 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1724820361 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 350 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1704 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1740168733 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 171 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 209903028 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1783952231 # Type of FU issued +system.cpu.iq.rate 1.468776 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2898143 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001625 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4785297542 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2365259636 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1724635094 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 543 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1776 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 123 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1740037802 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 245 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 210029942 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113016880 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 39297 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 180469 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31115283 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 112628288 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 39424 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 182684 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31031188 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2481 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 68 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2402 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 58 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 61686993 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1142265 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 110648 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1994506717 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63004482 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 532059001 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 219301341 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 80 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 54039 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2855 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 180469 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2045569 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24474359 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26519928 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766291934 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 474573600 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 17788827 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 61543875 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1219448 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 109755 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1993488848 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63065998 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 531670409 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 219217246 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 52970 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2883 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 182684 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2045175 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24468993 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26514168 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766143547 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474612951 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17808684 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 666299746 # number of memory reference insts executed -system.cpu.iew.exec_branches 110359604 # Number of branches executed -system.cpu.iew.exec_stores 191726146 # Number of stores executed -system.cpu.iew.exec_rate 1.453869 # Inst execution rate -system.cpu.iew.wb_sent 1725940615 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1724820453 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1267203875 # num instructions producing a value -system.cpu.iew.wb_consumers 1829107615 # num instructions consuming a value +system.cpu.iew.exec_refs 666319153 # number of memory reference insts executed +system.cpu.iew.exec_branches 110355146 # Number of branches executed +system.cpu.iew.exec_stores 191706202 # Number of stores executed +system.cpu.iew.exec_rate 1.454114 # Inst execution rate +system.cpu.iew.wb_sent 1725748007 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1724635217 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1267063012 # num instructions producing a value +system.cpu.iew.wb_consumers 1828799696 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.419733 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692799 # average fanout of values written-back +system.cpu.iew.wb_rate 1.419939 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692839 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 373014217 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 371996186 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26390469 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1152851077 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.406508 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.830012 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26384610 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1152677565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.406719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.830300 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 418199687 36.28% 36.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 415017727 36.00% 72.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87014149 7.55% 79.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122172880 10.60% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24164674 2.10% 92.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25337442 2.20% 94.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16460362 1.43% 96.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12052065 1.05% 97.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32432091 2.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 418027879 36.27% 36.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 415124601 36.01% 72.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86915055 7.54% 79.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122122398 10.59% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24176868 2.10% 92.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25399940 2.20% 94.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16385768 1.42% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12050207 1.05% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32474849 2.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1152851077 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1152677565 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493926 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -440,194 +440,194 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354437 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32432091 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32474849 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3114927129 # The number of ROB reads -system.cpu.rob.rob_writes 4050738571 # The number of ROB writes -system.cpu.timesIdled 58873 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 353019 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3113692828 # The number of ROB reads +system.cpu.rob.rob_writes 4048559892 # The number of ROB writes +system.cpu.timesIdled 59027 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 362783 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493926 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.380518 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.380518 # CPI: Total CPI of All Threads -system.cpu.ipc 0.724366 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.724366 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3542903494 # number of integer regfile reads -system.cpu.int_regfile_writes 1974699145 # number of integer regfile writes -system.cpu.fp_regfile_reads 92 # number of floating regfile reads -system.cpu.misc_regfile_reads 910807256 # number of misc regfile reads -system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 815.551450 # Cycle average of tags in use -system.cpu.icache.total_refs 187841113 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 206418.805495 # Average number of references to valid blocks. +system.cpu.cpi 1.380170 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.380170 # CPI: Total CPI of All Threads +system.cpu.ipc 0.724549 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.724549 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3542852942 # number of integer regfile reads +system.cpu.int_regfile_writes 1974486988 # number of integer regfile writes +system.cpu.fp_regfile_reads 123 # number of floating regfile reads +system.cpu.misc_regfile_reads 910772207 # number of misc regfile reads +system.cpu.icache.replacements 25 # number of replacements +system.cpu.icache.tagsinuse 816.669933 # Cycle average of tags in use +system.cpu.icache.total_refs 188003443 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 918 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 204796.778867 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 815.551450 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.398218 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.398218 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 187841119 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 187841119 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 187841119 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 187841119 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 187841119 # number of overall hits -system.cpu.icache.overall_hits::total 187841119 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1384 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1384 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1384 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1384 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1384 # number of overall misses -system.cpu.icache.overall_misses::total 1384 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64353500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64353500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64353500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64353500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64353500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64353500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 187842503 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 187842503 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 187842503 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 187842503 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 187842503 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 187842503 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 816.669933 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.398765 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.398765 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 188003447 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 188003447 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 188003447 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 188003447 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 188003447 # number of overall hits +system.cpu.icache.overall_hits::total 188003447 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1380 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1380 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1380 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1380 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1380 # number of overall misses +system.cpu.icache.overall_misses::total 1380 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 65047500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 65047500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 65047500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 65047500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 65047500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 65047500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 188004827 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 188004827 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 188004827 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 188004827 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 188004827 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 188004827 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46498.193642 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46498.193642 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46498.193642 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46498.193642 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46498.193642 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46498.193642 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 203 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47135.869565 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47135.869565 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47135.869565 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47135.869565 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47135.869565 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47135.869565 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 34.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 918 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46138000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46138000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46138000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46138000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46138000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46138000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 455 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 455 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 455 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 455 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 455 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 455 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 925 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 925 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 925 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 925 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 925 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 925 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47382000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47382000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47382000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47382000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47382000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47382000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50259.259259 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50259.259259 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50259.259259 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50259.259259 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50259.259259 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50259.259259 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51223.783784 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51223.783784 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51223.783784 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51223.783784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51223.783784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51223.783784 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22259.528577 # Cycle average of tags in use -system.cpu.l2cache.total_refs 531228 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24191 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.959737 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22259.325739 # Cycle average of tags in use +system.cpu.l2cache.total_refs 531319 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24190 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.964407 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20782.488903 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 799.212802 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 677.826873 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.634231 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.024390 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020686 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.679307 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 199209 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 199217 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 428963 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 428963 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 8 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224450 # 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Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.024398 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.020714 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.679301 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 199250 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 199267 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 429018 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 429018 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 7 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 224476 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 224476 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 17 # 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number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4063849999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4063849999 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7079925999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7079925999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7079925999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7079925999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264667108 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264667108 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 446086 # number of replacements +system.cpu.dcache.tagsinuse 4092.713768 # Cycle average of tags in use +system.cpu.dcache.total_refs 452307982 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 450182 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1004.722494 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 861652000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4092.713768 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999198 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999198 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 264368372 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264368372 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939603 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939603 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452307975 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452307975 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452307975 # number of overall hits +system.cpu.dcache.overall_hits::total 452307975 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 211281 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 211281 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246455 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246455 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 457736 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 457736 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 457736 # number of overall misses +system.cpu.dcache.overall_misses::total 457736 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3022618500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3022618500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4119755500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4119755500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7142374000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7142374000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7142374000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7142374000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264579653 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264579653 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 452853166 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 452853166 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 452853166 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 452853166 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 452765711 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452765711 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452765711 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452765711 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000799 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000799 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001310 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.001010 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001010 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.001010 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001010 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14285.059322 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14285.059322 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16490.622232 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16490.622232 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15472.914465 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15472.914465 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15472.914465 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15472.914465 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 474 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.001011 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001011 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001011 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001011 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14306.153890 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14306.153890 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16716.055669 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16716.055669 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15603.697328 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15603.697328 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 48 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 40 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.875000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.125000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428963 # number of writebacks -system.cpu.dcache.writebacks::total 428963 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7361 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7361 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 84 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 84 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7445 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7445 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7445 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7445 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203774 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203774 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246350 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246350 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 450124 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 450124 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 450124 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 450124 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523540500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523540500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3570238499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3570238499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6093778999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6093778999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6093778999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6093778999 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 429018 # number of writebacks +system.cpu.dcache.writebacks::total 429018 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7464 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7464 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 81 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 81 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7545 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7545 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7545 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7545 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203817 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203817 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246374 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246374 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 450191 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 450191 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 450191 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 450191 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2528414500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2528414500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3626209000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3626209000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6154623500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6154623500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6154623500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6154623500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses @@ -782,14 +782,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12384.016116 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12384.016116 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14492.545155 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14492.545155 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13538.000638 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13538.000638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13538.000638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13538.000638 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12405.317025 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12405.317025 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14718.310374 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14718.310374 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |