diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref')
15 files changed, 2954 insertions, 2833 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 0e8616cf5..8c8aecb35 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -54,8 +55,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -functionTrace=false -functionTraceStart=0 function_trace=false function_trace_start=0 globalCtrBits=2 @@ -63,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -76,7 +76,6 @@ memBlockSize=64 multLatency=1 multRepeatRate=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -94,20 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,20 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -146,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -153,22 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -178,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -191,12 +199,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing +cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 @@ -214,18 +222,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index 282b60660..5289b243e 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:09:56 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:21:21 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 274137499500 because target called exit() +Exiting @ tick 269661304500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 01d17fd64..e8752c3e3 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.269731 # Number of seconds simulated -sim_ticks 269730745500 # Number of ticks simulated -final_tick 269730745500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.269661 # Number of seconds simulated +sim_ticks 269661304500 # Number of ticks simulated +final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168515 # Simulator instruction rate (inst/s) -host_op_rate 168515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75522303 # Simulator tick rate (ticks/s) -host_mem_usage 218132 # Number of bytes of host memory used -host_seconds 3571.54 # Real time elapsed on the host +host_inst_rate 125304 # Simulator instruction rate (inst/s) +host_op_rate 125304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56142087 # Simulator tick rate (ticks/s) +host_mem_usage 214336 # Number of bytes of host memory used +host_seconds 4803.19 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199547 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6039326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6238873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199547 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199547 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 240595 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 240595 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 240595 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199547 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6039326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6479469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6040882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6240480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 240657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 240657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 240657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6040882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6481138 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 26294 # Total number of read requests seen system.physmem.writeReqs 1014 # Total number of write requests seen system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 74 # Tr system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 269730693500 # Total gap between requests +system.physmem.totGap 269661252500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -105,9 +105,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 17613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 17608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1642 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 44 # Wh system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 360576187 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1020404187 # Sum of mem lat for all requests +system.physmem.totQLat 364261179 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1024159179 # Sum of mem lat for all requests system.physmem.totBusLat 105120000 # Total cycles spent in databus access -system.physmem.totBankLat 554708000 # Total cycles spent in bank access -system.physmem.avgQLat 13720.56 # Average queueing delay per request -system.physmem.avgBankLat 21107.61 # Average bank access latency per request +system.physmem.totBankLat 554778000 # Total cycles spent in bank access +system.physmem.avgQLat 13860.78 # Average queueing delay per request +system.physmem.avgBankLat 21110.27 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38828.17 # Average memory access latency +system.physmem.avgMemAccLat 38971.05 # Average memory access latency system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s @@ -187,31 +187,31 @@ system.physmem.peakBW 16000.00 # Th system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 12.19 # Average write queue length over time -system.physmem.readRowHits 17405 # Number of row buffer hits during reads +system.physmem.readRowHits 17406 # Number of row buffer hits during reads system.physmem.writeRowHits 51 # Number of row buffer hits during writes system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes -system.physmem.avgGap 9877350.72 # Average gap between requests +system.physmem.avgGap 9874807.84 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517567 # DTB read hits +system.cpu.dtb.read_hits 114517568 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520198 # DTB read accesses -system.cpu.dtb.write_hits 39453373 # DTB write hits +system.cpu.dtb.read_accesses 114520199 # DTB read accesses +system.cpu.dtb.write_hits 39453362 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39455675 # DTB write accesses -system.cpu.dtb.data_hits 153970940 # DTB hits +system.cpu.dtb.write_accesses 39455664 # DTB write accesses +system.cpu.dtb.data_hits 153970930 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153975873 # DTB accesses -system.cpu.itb.fetch_hits 25065868 # ITB hits +system.cpu.dtb.data_accesses 153975863 # DTB accesses +system.cpu.itb.fetch_hits 24997854 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25065890 # ITB accesses +system.cpu.itb.fetch_accesses 24997876 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 539461492 # number of cpu cycles simulated +system.cpu.numCycles 539322610 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86297721 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 81352852 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36357676 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52914836 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34319624 # Number of BTB hits +system.cpu.branch_predictor.lookups 86405274 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81476244 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36343014 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 44773910 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34660000 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 64.858226 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36896934 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49400787 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541636673 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 77.411153 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005491519 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 1004918560 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 254989713 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 155053642 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 33759621 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2593068 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36352689 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26195221 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.119750 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412334808 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 255160193 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 154928367 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36338027 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26209890 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.096302 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412128439 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 535900413 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 535759910 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 295985 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50743768 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 488717724 # Number of cycles cpu stages are processed. -system.cpu.activity 90.593626 # Percentage of cycles cpu is active +system.cpu.timesIdled 295987 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50789311 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 488533299 # Number of cycles cpu stages are processed. +system.cpu.activity 90.582759 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -272,72 +272,72 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.896328 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.896098 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.896328 # CPI: Total CPI of All Threads -system.cpu.ipc 1.115663 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.896098 # CPI: Total CPI of All Threads +system.cpu.ipc 1.115950 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.115663 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 200698192 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338763300 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.796568 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 228822575 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310638917 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.583149 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 197865765 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341595727 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.321615 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 428073840 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111387652 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.647934 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 192651610 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 346809882 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.288163 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.115950 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 200593326 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338729284 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.806431 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 228903212 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310419398 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.557275 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 197757745 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341564865 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.332198 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 427944093 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111378517 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.651557 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 192521650 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346800960 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.303063 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 729.083311 # Cycle average of tags in use -system.cpu.icache.total_refs 25064833 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.842734 # Cycle average of tags in use +system.cpu.icache.total_refs 24996820 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29315.594152 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29236.046784 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 729.083311 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355998 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355998 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25064833 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25064833 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25064833 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25064833 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25064833 # number of overall hits -system.cpu.icache.overall_hits::total 25064833 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1035 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1035 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1035 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1035 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1035 # number of overall misses -system.cpu.icache.overall_misses::total 1035 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 52854000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 52854000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 52854000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 52854000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 52854000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 52854000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25065868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25065868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25065868 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25065868 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25065868 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25065868 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 729.842734 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.356369 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.356369 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24996820 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24996820 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24996820 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24996820 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24996820 # number of overall hits +system.cpu.icache.overall_hits::total 24996820 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses +system.cpu.icache.overall_misses::total 1034 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 53126500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 53126500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 53126500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 53126500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 53126500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 53126500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24997854 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24997854 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24997854 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24997854 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24997854 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24997854 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51066.666667 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51066.666667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51066.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51066.666667 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51379.593810 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51379.593810 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51379.593810 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51379.593810 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -346,158 +346,50 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 93.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 180 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 180 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 180 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 180 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 180 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 179 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 179 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 179 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 179 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 179 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43286500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43286500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43286500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43286500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43286500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43286500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43645500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43645500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43645500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43645500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43645500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43645500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50627.485380 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50627.485380 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51047.368421 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51047.368421 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.419858 # Cycle average of tags in use -system.cpu.dcache.total_refs 151786041 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 333.306341 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.419858 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37665413 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37665413 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 151786041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 151786041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 151786041 # number of overall hits -system.cpu.dcache.overall_hits::total 151786041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1785908 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1785908 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2179322 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2179322 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2179322 # number of overall misses -system.cpu.dcache.overall_misses::total 2179322 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5991589500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5991589500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22875440000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22875440000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28867029500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28867029500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28867029500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28867029500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15229.731275 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15229.731275 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12808.856895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12808.856895 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13245.876240 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13245.876240 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 165761 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 544 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5600 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.600179 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 60.444444 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks -system.cpu.dcache.writebacks::total 436887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531745 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1531745 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1723927 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1723927 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1723927 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1723927 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645854500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645854500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3731128500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3731128500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6376983000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6376983000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6376983000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6376983000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13148.279101 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13148.279101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14680.061614 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14680.061614 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22878.552216 # Cycle average of tags in use -system.cpu.l2cache.total_refs 531848 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22879.132168 # Cycle average of tags in use +system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. 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+system.cpu.l2cache.occ_blocks::cpu.inst 718.963213 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 475.545477 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.661762 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014512 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits @@ -522,17 +414,17 @@ system.cpu.l2cache.demand_misses::total 26294 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses 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cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1622928500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1665568000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -557,17 +449,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.057631 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50274.078478 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114589.454545 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 103697.543294 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53773.912228 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53773.912228 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 63202.707842 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 63202.707842 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50700.951249 # average ReadReq miss latency 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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 877062534 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31666859 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1296316456 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1327983315 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31666859 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1296316456 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1327983315 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32024355 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418973423 # number of ReadReq MSHR miss cycles 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misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3734758000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3734758000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6380334500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6380334500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6380334500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6380334500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.897611 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.897611 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14694.341820 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14694.341820 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 5bc85930f..ba863cc04 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -451,22 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -489,12 +499,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 @@ -512,18 +522,32 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index ddf76222f..396a60755 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:10:10 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:21:56 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 135504709500 because target called exit() +Exiting @ tick 133778696500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 82eaca8c6..759350e06 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.135739 # Number of seconds simulated -sim_ticks 135738546500 # Number of ticks simulated -final_tick 135738546500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133779 # Number of seconds simulated +sim_ticks 133778696500 # Number of ticks simulated +final_tick 133778696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149707 # Simulator instruction rate (inst/s) -host_op_rate 149707 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35931284 # Simulator tick rate (ticks/s) -host_mem_usage 219152 # Number of bytes of host memory used -host_seconds 3777.73 # Real time elapsed on the host +host_inst_rate 208111 # Simulator instruction rate (inst/s) +host_op_rate 208111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49227708 # Simulator tick rate (ticks/s) +host_mem_usage 215496 # Number of bytes of host memory used +host_seconds 2717.55 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1636160 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory -system.physmem.bytes_written::total 67072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25565 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26528 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 454049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12053761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12507810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 454049 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 454049 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 494126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 494126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 494126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 454049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12053761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13001937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26528 # Total number of read requests seen -system.physmem.writeReqs 1048 # Total number of write requests seen -system.physmem.cpureqs 27576 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697792 # Total number of bytes read from memory -system.physmem.bytesWritten 67072 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697792 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636416 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67008 # Number of bytes written to this memory +system.physmem.bytes_written::total 67008 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 951 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25569 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26520 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1047 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1047 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 454960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12232262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12687222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 454960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 454960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 500887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 500887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 500887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 454960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12232262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13188109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26520 # Total number of read requests seen +system.physmem.writeReqs 1047 # Total number of write requests seen +system.physmem.cpureqs 27567 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697280 # Total number of bytes read from memory +system.physmem.bytesWritten 67008 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697280 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67008 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1612 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1636 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1683 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1685 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1569 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1630 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1617 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1568 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1629 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1615 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1555 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1704 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1678 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 78 # Track writes on a per bank basis @@ -65,26 +65,26 @@ system.physmem.perBankWrReqs::2 55 # Tr system.physmem.perBankWrReqs::3 60 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 75 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 78 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 83 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 84 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 54 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 59 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 57 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 80 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 78 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 135738512500 # Total gap between requests +system.physmem.totGap 133778628000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26528 # Categorize read packet sizes +system.physmem.readPktSize::6 26520 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1048 # categorize write packet sizes +system.physmem.writePktSize::6 1047 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10090 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4903 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1000 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -150,7 +150,7 @@ system.physmem.wrQLenPdf::8 46 # Wh system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 656768415 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1272742415 # Sum of mem lat for all requests -system.physmem.totBusLat 106052000 # Total cycles spent in databus access -system.physmem.totBankLat 509922000 # Total cycles spent in bank access -system.physmem.avgQLat 24771.56 # Average queueing delay per request -system.physmem.avgBankLat 19232.90 # Average bank access latency per request +system.physmem.totQLat 650833420 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1266537420 # Sum of mem lat for all requests +system.physmem.totBusLat 106020000 # Total cycles spent in databus access +system.physmem.totBankLat 509684000 # Total cycles spent in bank access +system.physmem.avgQLat 24555.12 # Average queueing delay per request +system.physmem.avgBankLat 19229.73 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 48004.47 # Average memory access latency -system.physmem.avgRdBW 12.51 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.49 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 12.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.49 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 47784.85 # Average memory access latency +system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.08 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.03 # Average write queue length over time -system.physmem.readRowHits 18053 # Number of row buffer hits during reads -system.physmem.writeRowHits 56 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 5.34 # Row buffer hit rate for writes -system.physmem.avgGap 4922342.34 # Average gap between requests +system.physmem.avgWrQLen 10.37 # Average write queue length over time +system.physmem.readRowHits 18044 # Number of row buffer hits during reads +system.physmem.writeRowHits 53 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 5.06 # Row buffer hit rate for writes +system.physmem.avgGap 4852854.06 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123922794 # DTB read hits -system.cpu.dtb.read_misses 28366 # DTB read misses +system.cpu.dtb.read_hits 122603551 # DTB read hits +system.cpu.dtb.read_misses 28565 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123951160 # DTB read accesses -system.cpu.dtb.write_hits 40833980 # DTB write hits -system.cpu.dtb.write_misses 25612 # DTB write misses +system.cpu.dtb.read_accesses 122632116 # DTB read accesses +system.cpu.dtb.write_hits 40753368 # DTB write hits +system.cpu.dtb.write_misses 25574 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40859592 # DTB write accesses -system.cpu.dtb.data_hits 164756774 # DTB hits -system.cpu.dtb.data_misses 53978 # DTB misses +system.cpu.dtb.write_accesses 40778942 # DTB write accesses +system.cpu.dtb.data_hits 163356919 # DTB hits +system.cpu.dtb.data_misses 54139 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164810752 # DTB accesses -system.cpu.itb.fetch_hits 66580671 # ITB hits -system.cpu.itb.fetch_misses 40 # ITB misses +system.cpu.dtb.data_accesses 163411058 # DTB accesses +system.cpu.itb.fetch_hits 65475592 # ITB hits +system.cpu.itb.fetch_misses 42 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66580711 # ITB accesses +system.cpu.itb.fetch_accesses 65475634 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,246 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 271477094 # number of cpu cycles simulated +system.cpu.numCycles 267557394 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78553522 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72909571 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3050106 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42863354 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41672348 # Number of BTB hits +system.cpu.BPredUnit.lookups 76440222 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 70864810 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2706098 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 43060392 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41933015 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1629524 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 245 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68542455 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 711581178 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78553522 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43301872 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119313775 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13045820 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73380337 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 247 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1305 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 7 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66580671 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 946763 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 271202747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.623798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454049 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1604413 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 67119409 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 699052842 # Number of instructions fetch has processed +system.cpu.fetch.Branches 76440222 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43537428 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 117782486 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11617306 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73490715 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1303 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65475592 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 928038 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267274328 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.615488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.444547 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 151888972 56.01% 56.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10373570 3.83% 59.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11841110 4.37% 64.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10622549 3.92% 68.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7004922 2.58% 70.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2671761 0.99% 71.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3503178 1.29% 72.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3113300 1.15% 74.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70183385 25.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149491842 55.93% 55.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10342090 3.87% 59.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11847639 4.43% 64.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10563390 3.95% 68.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7011808 2.62% 70.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2869024 1.07% 71.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3576964 1.34% 73.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3101400 1.16% 74.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68470171 25.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 271202747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.289356 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.621146 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 86023061 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57429003 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104152322 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13634796 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9963565 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3909126 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1128 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 702760367 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4141 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9963565 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 94304341 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12784998 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1531 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104174044 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49974268 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 690768624 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 416 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38037873 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5669894 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527681051 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 907529781 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 907526811 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2970 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267274328 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285697 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.612721 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 84240613 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57793701 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102635866 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13724657 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8879491 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3873839 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 920 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 691093913 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3105 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8879491 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 92211740 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12790279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1241 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 103054645 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50336932 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 680961604 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 408 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38688874 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5430085 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 520709674 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 896990234 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 896987596 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2638 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63826162 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 100 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 107 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112138467 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 129142032 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42466663 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14842304 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10368291 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626932339 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 92 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608621790 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 344229 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60678365 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33855512 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 271202747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.244158 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.828491 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 56854785 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 64 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 69 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112289485 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 126970724 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42377686 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14852387 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10147583 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 621083354 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 604563100 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 299815 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 54897951 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29938787 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267274328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.261957 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.823661 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55518105 20.47% 20.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55264401 20.38% 40.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53914091 19.88% 60.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 37013789 13.65% 74.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31720099 11.70% 86.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23689667 8.74% 94.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10003906 3.69% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3493839 1.29% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 584850 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52499760 19.64% 19.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55875325 20.91% 40.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53442699 20.00% 60.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36269586 13.57% 74.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31423380 11.76% 85.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23799839 8.90% 94.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9996979 3.74% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3415050 1.28% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 551710 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 271202747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267274328 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2803923 71.85% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 36 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 717323 18.38% 90.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 381401 9.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2734710 70.93% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 35 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 70.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 729519 18.92% 89.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 391400 10.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441148473 72.48% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7331 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126212456 20.74% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41253487 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439055623 72.62% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7072 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124323040 20.56% 93.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41177317 6.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608621790 # Type of FU issued -system.cpu.iq.rate 2.241890 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3902683 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006412 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1492689315 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 687613743 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598990581 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3924 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2505 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1722 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 612522503 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1970 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12211500 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 604563100 # Type of FU issued +system.cpu.iq.rate 2.259564 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3855664 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006378 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1480552206 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 675984537 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 596489873 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3801 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2284 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1738 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 608416848 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1916 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12282855 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14627990 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 32965 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5519 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3015342 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12456682 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 35904 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5518 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2926365 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6777 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 53391 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6461 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 52889 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9963565 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1456092 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 187737 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 670933978 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1716868 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 129142032 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42466663 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 92 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 140012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7404 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5519 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1345446 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2210203 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3555649 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602801961 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123951309 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5819829 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8879491 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1456554 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 192142 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 663913486 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1691538 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 126970724 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42377686 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 56 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 144242 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7408 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5518 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1333964 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1804152 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3138116 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599464075 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 122632263 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5099025 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 44001547 # number of nop insts executed -system.cpu.iew.exec_refs 164826908 # number of memory reference insts executed -system.cpu.iew.exec_branches 67037045 # Number of branches executed -system.cpu.iew.exec_stores 40875599 # Number of stores executed -system.cpu.iew.exec_rate 2.220452 # Inst execution rate -system.cpu.iew.wb_sent 600240253 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598992303 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417488059 # num instructions producing a value -system.cpu.iew.wb_consumers 532706701 # num instructions consuming a value +system.cpu.iew.exec_nop 42830076 # number of nop insts executed +system.cpu.iew.exec_refs 163429760 # number of memory reference insts executed +system.cpu.iew.exec_branches 66623337 # Number of branches executed +system.cpu.iew.exec_stores 40797497 # Number of stores executed +system.cpu.iew.exec_rate 2.240506 # Inst execution rate +system.cpu.iew.wb_sent 597426155 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 596491611 # cumulative count of insts written-back +system.cpu.iew.wb_producers 415927297 # num instructions producing a value +system.cpu.iew.wb_consumers 530215795 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.206419 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.783711 # average fanout of values written-back +system.cpu.iew.wb_rate 2.229397 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.784449 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 68955725 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 61932723 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3049050 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 261239182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.303854 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.691353 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2705240 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258394837 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.329214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.691172 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82351408 31.52% 31.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72672063 27.82% 59.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25867656 9.90% 69.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8932880 3.42% 72.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10297113 3.94% 76.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20861196 7.99% 84.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6530231 2.50% 87.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3837950 1.47% 88.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29888685 11.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79550578 30.79% 30.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72525012 28.07% 58.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25515345 9.87% 68.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9289171 3.59% 72.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10288497 3.98% 76.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21029047 8.14% 84.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6874256 2.66% 87.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3694459 1.43% 88.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29628472 11.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 261239182 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 258394837 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,368 +475,368 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29888685 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29628472 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 902098796 # The number of ROB reads -system.cpu.rob.rob_writes 1351611788 # The number of ROB writes -system.cpu.timesIdled 34221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 274347 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 892491662 # The number of ROB reads +system.cpu.rob.rob_writes 1336472901 # The number of ROB writes +system.cpu.timesIdled 34286 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 283066 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.480021 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.480021 # CPI: Total CPI of All Threads -system.cpu.ipc 2.083242 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.083242 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848885274 # number of integer regfile reads -system.cpu.int_regfile_writes 492863541 # number of integer regfile writes -system.cpu.fp_regfile_reads 396 # number of floating regfile reads -system.cpu.fp_regfile_writes 49 # number of floating regfile writes +system.cpu.cpi 0.473090 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.473090 # CPI: Total CPI of All Threads +system.cpu.ipc 2.113761 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.113761 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 844970192 # number of integer regfile reads +system.cpu.int_regfile_writes 490533624 # number of integer regfile writes +system.cpu.fp_regfile_reads 397 # number of floating regfile reads +system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 43 # number of replacements -system.cpu.icache.tagsinuse 832.109405 # Cycle average of tags in use -system.cpu.icache.total_refs 66579220 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 984 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67661.808943 # Average number of references to valid blocks. +system.cpu.icache.replacements 36 # number of replacements +system.cpu.icache.tagsinuse 825.012562 # Cycle average of tags in use +system.cpu.icache.total_refs 65474211 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 965 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67848.923316 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 832.109405 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.406303 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.406303 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66579220 # number of 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-system.cpu.dcache.blocked_cycles::no_mshrs 279576 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 531 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 17250 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.207304 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44.250000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14599.230682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14599.230682 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 277266 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17305 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.022306 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 83.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 445038 # number of writebacks -system.cpu.dcache.writebacks::total 445038 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 815637 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 815637 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1547591 # 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2700521500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4051961986 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4051961986 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6752483486 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6752483486 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6752483486 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6752483486 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001884 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001884 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses 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+system.cpu.dcache.demand_mshr_miss_latency::total 6750381990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6750381990 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6750381990 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003107 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003107 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003107 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003107 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12841.751321 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12841.751321 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15894.703311 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15894.703311 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1080 # number of replacements -system.cpu.l2cache.tagsinuse 22929.630995 # Cycle average of tags in use -system.cpu.l2cache.total_refs 547178 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23523 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.261404 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21483.752454 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 824.475298 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 621.403243 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.655632 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.025161 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.018964 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.699757 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 206090 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 206111 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 445038 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 445038 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 233241 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 233241 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 439331 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 439352 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 439331 # number of overall hits -system.cpu.l2cache.overall_hits::total 439352 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 963 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4290 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5253 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21275 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21275 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 963 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 25565 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 26528 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 963 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 25565 # number of overall misses -system.cpu.l2cache.overall_misses::total 26528 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50946500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 423158500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 474105000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1457229500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1457229500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 50946500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1880388000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1931334500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 50946500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1880388000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1931334500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 210380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 211364 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 445038 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 445038 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 254516 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 254516 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 984 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 464896 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 465880 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 984 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 464896 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 465880 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.978659 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020392 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024853 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083590 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083590 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.978659 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.054991 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.056942 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.978659 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.054991 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.056942 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52903.946002 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 98638.344988 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 90254.140491 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68494.923619 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68494.923619 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52903.946002 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73553.217289 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72803.622587 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52903.946002 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73553.217289 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72803.622587 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1049 # number of writebacks -system.cpu.l2cache.writebacks::total 1049 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5253 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21275 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21275 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25565 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26528 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25565 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26528 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38838509 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 367821283 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 406659792 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1190995676 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1190995676 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38838509 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1558816959 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1597655468 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38838509 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1558816959 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1597655468 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020392 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024853 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083590 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083590 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.056942 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.056942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40330.746625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 85739.226807 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77414.770988 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55980.995347 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55980.995347 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40330.746625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60974.651242 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60225.251357 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40330.746625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60974.651242 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60225.251357 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index 9953e7dde..c4518abcc 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 21a8a9bfd..5bcc38f1b 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:54:44 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 18:59:47 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 164735271500 because target called exit() +Exiting @ tick 164568389500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index ec201586b..d2efc8854 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.165181 # Number of seconds simulated -sim_ticks 165180822000 # Number of ticks simulated -final_tick 165180822000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164568 # Number of seconds simulated +sim_ticks 164568389500 # Number of ticks simulated +final_tick 164568389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196230 # Simulator instruction rate (inst/s) -host_op_rate 207352 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56860513 # Simulator tick rate (ticks/s) -host_mem_usage 233444 # Number of bytes of host memory used -host_seconds 2905.02 # Real time elapsed on the host +host_inst_rate 155967 # Simulator instruction rate (inst/s) +host_op_rate 164807 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45026221 # Simulator tick rate (ticks/s) +host_mem_usage 230908 # Number of bytes of host memory used +host_seconds 3654.95 # Real time elapsed on the host sim_insts 570052720 # Number of instructions simulated sim_ops 602360926 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 46976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1702592 # Number of bytes read from this memory -system.physmem.bytes_read::total 1749568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 46976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 46976 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 47104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1702080 # Number of bytes read from this memory +system.physmem.bytes_read::total 1749184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47104 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory system.physmem.bytes_written::total 162368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26603 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 736 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26595 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27331 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 284391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10307444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10591835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 284391 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 284391 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 982971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 982971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 982971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 284391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10307444 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11574806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27339 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 286228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10342691 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10628919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 286228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 286228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 986629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 986629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 986629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 286228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10342691 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11615548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27332 # Total number of read requests seen system.physmem.writeReqs 2537 # Total number of write requests seen -system.physmem.cpureqs 29876 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1749568 # Total number of bytes read from memory +system.physmem.cpureqs 29869 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1749184 # Total number of bytes read from memory system.physmem.bytesWritten 162368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1749568 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1749184 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1705 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1738 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1698 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1679 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1720 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1741 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1696 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1745 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1725 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1739 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1666 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1718 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 1759 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 159 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 164 # Tr system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 165180805000 # Total gap between requests +system.physmem.totGap 164568371500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27339 # Categorize read packet sizes +system.physmem.readPktSize::6 27332 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14846 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8786 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2844 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 783 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 110 # Wh system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 952476989 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1656324989 # Sum of mem lat for all requests -system.physmem.totBusLat 109352000 # Total cycles spent in databus access -system.physmem.totBankLat 594496000 # Total cycles spent in bank access -system.physmem.avgQLat 34839.50 # Average queueing delay per request -system.physmem.avgBankLat 21745.35 # Average bank access latency per request -system.physmem.avgBusLat 3999.85 # Average bus latency per request -system.physmem.avgMemAccLat 60584.70 # Average memory access latency -system.physmem.avgRdBW 10.59 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 10.59 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.98 # Average consumed write bandwidth in MB/s +system.physmem.totQLat 953340995 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1657962995 # Sum of mem lat for all requests +system.physmem.totBusLat 109328000 # Total cycles spent in databus access +system.physmem.totBankLat 595294000 # Total cycles spent in bank access +system.physmem.avgQLat 34880.03 # Average queueing delay per request +system.physmem.avgBankLat 21780.11 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 60660.14 # Average memory access latency +system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 5.90 # Average write queue length over time -system.physmem.readRowHits 17775 # Number of row buffer hits during reads -system.physmem.writeRowHits 1102 # Number of row buffer hits during writes -system.physmem.readRowHitRate 65.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.44 # Row buffer hit rate for writes -system.physmem.avgGap 5528879.54 # Average gap between requests +system.physmem.avgWrQLen 6.05 # Average write queue length over time +system.physmem.readRowHits 17765 # Number of row buffer hits during reads +system.physmem.writeRowHits 1091 # Number of row buffer hits during writes +system.physmem.readRowHitRate 65.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 43.00 # Row buffer hit rate for writes +system.physmem.avgGap 5509671.28 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,246 +235,247 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 330361645 # number of cpu cycles simulated +system.cpu.numCycles 329136780 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85614942 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80408346 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2411110 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47313103 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46933261 # Number of BTB hits +system.cpu.BPredUnit.lookups 85146783 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 79928286 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2342158 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47212748 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46871026 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1438558 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1082 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68875257 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669940715 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85614942 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48371819 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130120406 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13468606 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119373897 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 577 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67426910 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 785892 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 329401870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.167030 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.195227 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1427560 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1061 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68501011 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 666829693 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85146783 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48298586 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 129620938 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13095502 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119329475 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 302 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 67084220 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 755001 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 328178874 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.165282 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.193965 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 199281685 60.50% 60.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20931796 6.35% 66.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4976114 1.51% 68.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14405737 4.37% 72.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8916437 2.71% 75.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9491769 2.88% 78.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4395407 1.33% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5797990 1.76% 81.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61204935 18.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198558185 60.50% 60.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20911289 6.37% 66.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4967188 1.51% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14345258 4.37% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8890662 2.71% 75.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9436402 2.88% 78.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4398507 1.34% 79.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5788329 1.76% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 60883054 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 329401870 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259155 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.027901 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93386530 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96217512 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108381185 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20386445 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11030198 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4725688 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1634 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 706212594 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6047 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11030198 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107646383 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14427218 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 44142 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114436491 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81817438 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697478243 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59322145 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20349848 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 693 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 724191424 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3242851069 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3242850941 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 328178874 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258697 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.025996 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92947684 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96199178 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 107899614 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20406722 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10725676 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4737184 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1561 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703240498 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5895 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10725676 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107135136 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14450172 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 44143 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114043084 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81780663 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 694816427 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59310091 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20339427 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 721301804 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3230529001 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3230528873 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96772235 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2137 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2090 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 170767366 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172981751 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80655031 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21643688 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28602277 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 682247714 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3351 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646916263 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1413678 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79713119 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 198676272 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 420 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 329401870 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.963912 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.726446 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 93882615 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2064 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2020 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 170675831 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172202980 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80458110 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21583677 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28704390 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 679987725 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3320 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 645601186 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1370428 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 77447824 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 193234107 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 328178874 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.967223 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.725262 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68982651 20.94% 20.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85413517 25.93% 46.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75907397 23.04% 69.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40996794 12.45% 82.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28857883 8.76% 91.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14995240 4.55% 95.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5624116 1.71% 97.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6449034 1.96% 99.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2175238 0.66% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68164683 20.77% 20.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85309693 25.99% 46.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75934594 23.14% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40814180 12.44% 82.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28810425 8.78% 91.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14904242 4.54% 95.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5586841 1.70% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6537919 1.99% 99.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2116297 0.64% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 329401870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328178874 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 209715 5.57% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2699537 71.67% 77.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 857291 22.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 216945 5.75% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2691247 71.35% 77.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 863918 22.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403968416 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6570 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166149452 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76791822 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403371869 62.48% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6568 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 165559477 25.64% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76663269 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646916263 # Type of FU issued -system.cpu.iq.rate 1.958206 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3766543 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005822 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1628414581 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761976266 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638610282 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 645601186 # Type of FU issued +system.cpu.iq.rate 1.961498 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3772110 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005843 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624523748 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 757451010 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 637563052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650682786 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 649373276 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30415737 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30369655 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 24028931 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 122816 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12363 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10433791 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23250160 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 123060 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12375 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10236870 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12786 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 32242 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12923 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 32784 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11030198 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 797335 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 96405 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 682254196 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 711562 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172981751 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80655031 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2002 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 33535 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 20290 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12363 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1389918 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1519621 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2909539 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642699172 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163997886 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4217091 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10725676 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 798492 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 92069 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 679994152 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 690727 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172202980 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80458110 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1965 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 32845 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16029 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12375 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1358556 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1460812 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2819368 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 641523461 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163490704 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4077725 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3131 # number of nop insts executed -system.cpu.iew.exec_refs 239992833 # number of memory reference insts executed -system.cpu.iew.exec_branches 74738268 # Number of branches executed -system.cpu.iew.exec_stores 75994947 # Number of stores executed -system.cpu.iew.exec_rate 1.945441 # Inst execution rate -system.cpu.iew.wb_sent 640075541 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638610298 # cumulative count of insts written-back -system.cpu.iew.wb_producers 419218635 # num instructions producing a value -system.cpu.iew.wb_consumers 650818648 # num instructions consuming a value +system.cpu.iew.exec_nop 3107 # number of nop insts executed +system.cpu.iew.exec_refs 239380202 # number of memory reference insts executed +system.cpu.iew.exec_branches 74672586 # Number of branches executed +system.cpu.iew.exec_stores 75889498 # Number of stores executed +system.cpu.iew.exec_rate 1.949109 # Inst execution rate +system.cpu.iew.wb_sent 638973087 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 637563068 # cumulative count of insts written-back +system.cpu.iew.wb_producers 418509904 # num instructions producing a value +system.cpu.iew.wb_consumers 649810327 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.933064 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644140 # average fanout of values written-back +system.cpu.iew.wb_rate 1.937076 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644049 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 79903729 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 77641136 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2409576 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 318371673 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.892006 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.234894 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2340694 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 317453199 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.897480 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.237382 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93985379 29.52% 29.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104446341 32.81% 62.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43081844 13.53% 75.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8825548 2.77% 78.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25971107 8.16% 86.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12926353 4.06% 90.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7575563 2.38% 93.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1171571 0.37% 93.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20387967 6.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93244159 29.37% 29.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104350587 32.87% 62.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42987524 13.54% 75.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8793922 2.77% 78.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25958876 8.18% 86.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12900336 4.06% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7627072 2.40% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1171824 0.37% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20418899 6.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 318371673 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 317453199 # Number of insts commited each cycle system.cpu.commit.committedInsts 570052771 # Number of instructions committed system.cpu.commit.committedOps 602360977 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -485,317 +486,191 @@ system.cpu.commit.branches 70892751 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 533523539 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20387967 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20418899 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 980247800 # The number of ROB reads -system.cpu.rob.rob_writes 1375591081 # The number of ROB writes -system.cpu.timesIdled 40973 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 959775 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 977035801 # The number of ROB reads +system.cpu.rob.rob_writes 1370761733 # The number of ROB writes +system.cpu.timesIdled 41126 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 957906 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 570052720 # Number of Instructions Simulated system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated -system.cpu.cpi 0.579528 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.579528 # CPI: Total CPI of All Threads -system.cpu.ipc 1.725541 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.725541 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210576810 # number of integer regfile reads -system.cpu.int_regfile_writes 664235164 # number of integer regfile writes +system.cpu.cpi 0.577380 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.577380 # CPI: Total CPI of All Threads +system.cpu.ipc 1.731963 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.731963 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3204362065 # number of integer regfile reads +system.cpu.int_regfile_writes 663044095 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 905305467 # number of misc regfile reads +system.cpu.misc_regfile_reads 901644614 # number of misc regfile reads system.cpu.misc_regfile_writes 3110 # number of misc regfile writes -system.cpu.icache.replacements 62 # number of replacements -system.cpu.icache.tagsinuse 692.874511 # Cycle average of tags in use -system.cpu.icache.total_refs 67425756 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 825 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 81728.189091 # Average number of references to valid blocks. +system.cpu.icache.replacements 60 # number of replacements +system.cpu.icache.tagsinuse 685.359263 # Cycle average of tags in use +system.cpu.icache.total_refs 67083066 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 820 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 81808.617073 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 692.874511 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.338318 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.338318 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67425756 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67425756 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67425756 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67425756 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67425756 # number of overall hits -system.cpu.icache.overall_hits::total 67425756 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 685.359263 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.334648 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.334648 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67083066 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67083066 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67083066 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67083066 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67083066 # number of overall hits +system.cpu.icache.overall_hits::total 67083066 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses system.cpu.icache.overall_misses::total 1154 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50922500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50922500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50922500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50922500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50922500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50922500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67426910 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67426910 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67426910 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67426910 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67426910 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67426910 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51351999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51351999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51351999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51351999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51351999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51351999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67084220 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67084220 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67084220 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67084220 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67084220 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67084220 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44126.949740 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44126.949740 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44126.949740 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44126.949740 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44126.949740 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44126.949740 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 247 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44499.132582 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44499.132582 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44499.132582 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44499.132582 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44499.132582 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44499.132582 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 38.428571 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 328 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 328 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 328 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 328 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 826 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 826 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 826 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 826 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 826 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 826 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38439500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38439500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38439500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38439500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38439500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38439500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 334 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 334 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 334 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 334 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 334 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38657999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38657999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38657999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38657999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38657999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38657999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46536.924939 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46536.924939 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46536.924939 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 46536.924939 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46536.924939 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 46536.924939 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47143.901220 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47143.901220 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency 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0.998910 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 131984010 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 131984010 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 66075783 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 66075783 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1699 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1699 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 198059793 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 198059793 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 198059793 # number of overall hits -system.cpu.dcache.overall_hits::total 198059793 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 341827 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 341827 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3341748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3341748 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3683575 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3683575 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3683575 # number of overall misses -system.cpu.dcache.overall_misses::total 3683575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5150660000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5150660000 # number of ReadReq miss cycles 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-system.cpu.dcache.ReadReq_avg_miss_latency::total 15068.031490 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12011.493011 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12011.493011 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17630.434783 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17630.434783 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12295.132513 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12295.132513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12295.132513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12295.132513 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 131789 # number of cycles access was blocked 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cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6938434300 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6938434300 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001492 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001492 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002204 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002204 # mshr miss rate for overall accesses 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hits +system.cpu.dcache.ReadReq_mshr_hits::total 144398 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3125625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3125625 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3270023 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3270023 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3270023 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3270023 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197619 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197619 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247159 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247159 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444778 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444778 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444778 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444778 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875780500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875780500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4060483756 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4060483756 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6936264256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6936264256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6936264256 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001499 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001499 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.145796 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.145796 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.629975 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.629975 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index ca675ac92..48dcd7446 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -29,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -77,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -95,7 +97,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -421,16 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -444,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=SparcInterrupts +[system.cpu.isa] +type=SparcISA + [system.cpu.itb] type=SparcTLB size=64 @@ -451,22 +459,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -476,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -494,7 +504,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -516,14 +526,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 5518ac66c..10b614f5f 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:42 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:11:57 +gem5 started Oct 30 2012 14:00:44 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 389171398000 because target called exit() +Exiting @ tick 387281648500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index ef06efc76..c74d8b444 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.389228 # Number of seconds simulated -sim_ticks 389227542000 # Number of ticks simulated -final_tick 389227542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387282 # Number of seconds simulated +sim_ticks 387281648500 # Number of ticks simulated +final_tick 387281648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 219415 # Simulator instruction rate (inst/s) -host_op_rate 220107 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60950012 # Simulator tick rate (ticks/s) -host_mem_usage 227096 # Number of bytes of host memory used -host_seconds 6386.01 # Real time elapsed on the host +host_inst_rate 171377 # Simulator instruction rate (inst/s) +host_op_rate 171918 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47367883 # Simulator tick rate (ticks/s) +host_mem_usage 224920 # Number of bytes of host memory used +host_seconds 8176.04 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 76608 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1678464 # Number of bytes read from this memory -system.physmem.bytes_read::total 1755456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76992 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 1755072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76608 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1203 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1197 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 26226 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27429 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27423 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4312295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4510102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 416497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 416497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 416497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4312295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4926599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27430 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 197810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4333962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4531772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197810 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197810 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418589 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418589 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4333962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4950361 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27424 # Total number of read requests seen system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29963 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1755456 # Total number of bytes read from memory +system.physmem.cpureqs 29957 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1755072 # Total number of bytes read from memory system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1755456 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1755072 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1721 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 1715 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1803 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1805 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1769 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1667 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1678 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1745 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1754 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1755 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1621 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 158 # Tr system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 389227514000 # Total gap between requests +system.physmem.totGap 387281620500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27430 # Categorize read packet sizes +system.physmem.readPktSize::6 27424 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 8259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 8242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -171,265 +171,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 723930803 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1405746803 # Sum of mem lat for all requests -system.physmem.totBusLat 109720000 # Total cycles spent in databus access -system.physmem.totBankLat 572096000 # Total cycles spent in bank access -system.physmem.avgQLat 26391.94 # Average queueing delay per request -system.physmem.avgBankLat 20856.58 # Average bank access latency per request +system.physmem.totQLat 722664308 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1404176308 # Sum of mem lat for all requests +system.physmem.totBusLat 109696000 # Total cycles spent in databus access +system.physmem.totBankLat 571816000 # Total cycles spent in bank access +system.physmem.avgQLat 26351.53 # Average queueing delay per request +system.physmem.avgBankLat 20850.93 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 51248.52 # Average memory access latency -system.physmem.avgRdBW 4.51 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 51202.46 # Average memory access latency +system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 4.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.42 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 17.21 # Average write queue length over time -system.physmem.readRowHits 18327 # Number of row buffer hits during reads -system.physmem.writeRowHits 1092 # Number of row buffer hits during writes +system.physmem.avgWrQLen 17.43 # Average write queue length over time +system.physmem.readRowHits 18322 # Number of row buffer hits during reads +system.physmem.writeRowHits 1102 # Number of row buffer hits during writes system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.11 # Row buffer hit rate for writes -system.physmem.avgGap 12990271.80 # Average gap between requests +system.physmem.writeRowHitRate 43.51 # Row buffer hit rate for writes +system.physmem.avgGap 12927917.36 # Average gap between requests system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 778455085 # number of cpu cycles simulated +system.cpu.numCycles 774563298 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98229199 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88445613 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3785118 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 66042302 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65687206 # Number of BTB hits +system.cpu.BPredUnit.lookups 97756783 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88046378 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3616115 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 65822232 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65492473 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1416 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 222 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 165941423 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1649243289 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98229199 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65688622 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330524246 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21752869 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 264030512 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 127 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3232 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 162872893 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 756309 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 778243541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.125156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146469 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1334 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 221 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 164852368 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642212446 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97756783 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65493807 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329195647 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20823123 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263322100 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2527 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 161933661 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 734964 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774355546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126740 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146682 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 447719295 57.53% 57.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74411347 9.56% 67.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37980792 4.88% 71.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9095898 1.17% 73.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28164996 3.62% 76.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18829907 2.42% 79.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11517848 1.48% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3875799 0.50% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146647659 18.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445159899 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74061304 9.56% 67.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37898461 4.89% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9077519 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28105677 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18773272 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11484924 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3792333 0.49% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146002157 18.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 778243541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126185 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.118611 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 217164629 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 215069073 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285415505 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42850333 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17744001 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1642995255 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17744001 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 241214952 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36881220 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52262769 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303103685 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 127036914 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1631617640 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 159 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30927214 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 74044181 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3148431 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1361239803 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2756565281 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2722455578 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34109703 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774355546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126209 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.120178 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 215883064 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214466469 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284208572 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42814616 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16982825 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636500589 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16982825 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239715972 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36727743 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52434063 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302057850 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126437093 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625611071 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30924044 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73480825 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3128707 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356294088 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746297990 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712224165 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34073825 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 116469364 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2680762 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2695576 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 273321719 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 438834936 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 180276836 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 255914047 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 82184887 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1517277053 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2635551 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1461048176 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 49743 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 113961410 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 136888972 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 391880 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 778243541 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.877366 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.430181 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111523649 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2645349 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2664178 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271657434 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436922066 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179745095 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254298230 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83339884 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512454597 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2610820 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459325981 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53748 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109158045 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130052751 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 367149 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774355546 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884568 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.432012 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147640445 18.97% 18.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 185782276 23.87% 42.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210767336 27.08% 69.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131005887 16.83% 86.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70732163 9.09% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20418483 2.62% 98.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7758324 1.00% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3966460 0.51% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 172167 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145671235 18.81% 18.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184692846 23.85% 42.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209497548 27.05% 69.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131299597 16.96% 86.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70722781 9.13% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20304331 2.62% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8026000 1.04% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3959195 0.51% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 182013 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 778243541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774355546 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 96825 5.83% 5.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95727 5.76% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1146892 69.00% 80.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 322714 19.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90752 5.46% 5.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95014 5.72% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1160014 69.81% 80.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 315922 19.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 867232738 59.36% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2645576 0.18% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419895345 28.74% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171274517 11.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866438962 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644873 0.18% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419117163 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171124983 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1461048176 # Type of FU issued -system.cpu.iq.rate 1.876856 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1662158 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001138 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3684211603 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1624908064 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1444562282 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17840191 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9203552 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8548837 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453579294 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9131040 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215356561 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459325981 # Type of FU issued +system.cpu.iq.rate 1.884063 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1661702 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001139 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3676896998 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615267495 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443201042 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17825960 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9193607 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8546616 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451866721 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9120962 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215450617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36322093 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 55076 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 245947 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13428694 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34409223 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 57798 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 244556 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12896953 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3648 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 92141 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3310 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 91608 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17744001 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3080372 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 245510 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1614123458 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4140274 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 438834936 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 180276836 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2549819 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 147701 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1738 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 245947 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2356068 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1563417 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3919485 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1455490088 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 417172237 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5558088 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16982825 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3082295 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 247112 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608751818 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4125389 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436922066 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179745095 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2527727 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 148822 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1680 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 244556 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2270064 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1474247 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3744311 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454009970 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416570645 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5316011 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 94210854 # number of nop insts executed -system.cpu.iew.exec_refs 587755640 # number of memory reference insts executed -system.cpu.iew.exec_branches 89119477 # Number of branches executed -system.cpu.iew.exec_stores 170583403 # Number of stores executed -system.cpu.iew.exec_rate 1.869716 # Inst execution rate -system.cpu.iew.wb_sent 1454027442 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1453111119 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154511485 # num instructions producing a value -system.cpu.iew.wb_consumers 1205709259 # num instructions consuming a value +system.cpu.iew.exec_nop 93686401 # number of nop insts executed +system.cpu.iew.exec_refs 587021920 # number of memory reference insts executed +system.cpu.iew.exec_branches 89037548 # Number of branches executed +system.cpu.iew.exec_stores 170451275 # Number of stores executed +system.cpu.iew.exec_rate 1.877200 # Inst execution rate +system.cpu.iew.wb_sent 1452636193 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451747658 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153420359 # num instructions producing a value +system.cpu.iew.wb_consumers 1204679279 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.866660 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957537 # average fanout of values written-back +system.cpu.iew.wb_rate 1.874279 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957450 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 124505734 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119133058 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3785118 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 760500151 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.958610 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.504084 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3616115 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757373332 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966696 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509453 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 241986025 31.82% 31.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276568961 36.37% 68.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42982436 5.65% 73.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54874417 7.22% 81.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19672131 2.59% 83.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13330795 1.75% 85.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30549094 4.02% 89.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10561201 1.39% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69975091 9.20% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 239955150 31.68% 31.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275777678 36.41% 68.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42556583 5.62% 73.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54728215 7.23% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19718156 2.60% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13293088 1.76% 85.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30577311 4.04% 89.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10491345 1.39% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70275806 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 760500151 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757373332 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -440,374 +441,374 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69975091 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70275806 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2304489206 # The number of ROB reads -system.cpu.rob.rob_writes 3245826636 # The number of ROB writes -system.cpu.timesIdled 25902 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 211544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295688996 # The number of ROB reads +system.cpu.rob.rob_writes 3234318218 # The number of ROB writes +system.cpu.timesIdled 25993 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 207752 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.555568 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.555568 # CPI: Total CPI of All Threads -system.cpu.ipc 1.799961 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.799961 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1980833855 # number of integer regfile reads -system.cpu.int_regfile_writes 1276392600 # number of integer regfile writes -system.cpu.fp_regfile_reads 16967472 # number of floating regfile reads -system.cpu.fp_regfile_writes 10493116 # number of floating regfile writes -system.cpu.misc_regfile_reads 593429000 # number of misc regfile reads +system.cpu.cpi 0.552790 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552790 # CPI: Total CPI of All Threads +system.cpu.ipc 1.809005 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.809005 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979115545 # number of integer regfile reads +system.cpu.int_regfile_writes 1275157860 # number of integer regfile writes +system.cpu.fp_regfile_reads 16963296 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491838 # number of floating regfile writes +system.cpu.misc_regfile_reads 592677531 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 221 # number of replacements -system.cpu.icache.tagsinuse 1044.865694 # Cycle average of tags in use -system.cpu.icache.total_refs 162870916 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1368 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 119057.687135 # Average number of references to valid blocks. +system.cpu.icache.replacements 190 # number of replacements +system.cpu.icache.tagsinuse 1035.892325 # Cycle average of tags in use +system.cpu.icache.total_refs 161931728 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1331 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 121661.703982 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1044.865694 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.510188 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.510188 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 162870916 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 162870916 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 162870916 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 162870916 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 162870916 # number of overall hits -system.cpu.icache.overall_hits::total 162870916 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1977 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1977 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1977 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1977 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1977 # number of overall misses -system.cpu.icache.overall_misses::total 1977 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82311500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82311500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82311500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82311500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82311500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82311500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162872893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162872893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162872893 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162872893 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162872893 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162872893 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1035.892325 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505807 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505807 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161931728 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161931728 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161931728 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161931728 # number of demand (read+write) hits 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+system.cpu.icache.overall_miss_latency::cpu.inst 80019500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 80019500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161933661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161933661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161933661 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161933661 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161933661 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161933661 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for 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+system.cpu.dcache.occ_blocks::cpu.data 4093.828969 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999470 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999470 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 200081459 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200081459 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164955943 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164955943 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365739456 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365739456 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365739456 # number of overall hits -system.cpu.dcache.overall_hits::total 365739456 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 929575 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 929575 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1888210 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1888210 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365037402 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365037402 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365037402 # number of overall hits +system.cpu.dcache.overall_hits::total 365037402 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 927524 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 927524 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1890873 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1890873 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2817785 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2817785 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2817785 # number of overall misses -system.cpu.dcache.overall_misses::total 2817785 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14994299000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14994299000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31871156950 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31871156950 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2818397 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2818397 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2818397 # number of overall misses +system.cpu.dcache.overall_misses::total 2818397 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14988914500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14988914500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31918196457 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31918196457 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 122000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 122000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46865455950 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46865455950 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46865455950 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46865455950 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201710425 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201710425 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 46907110957 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46907110957 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46907110957 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46907110957 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201008983 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201008983 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 368557241 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 368557241 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 368557241 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 368557241 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004608 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004608 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011317 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011317 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 367855799 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 367855799 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 367855799 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 367855799 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004614 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004614 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011333 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011333 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007645 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007645 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007645 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007645 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16130.273512 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16130.273512 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16879.031967 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16879.031967 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.007662 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007662 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007662 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007662 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16160.136557 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16160.136557 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16880.137617 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16880.137617 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 17428.571429 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 17428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16632.019813 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16632.019813 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16632.019813 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16632.019813 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 577430 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 18 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35655 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16643.187939 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16643.187939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16643.187939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16643.187939 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 574305 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35651 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.194924 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.109085 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 442964 # number of writebacks -system.cpu.dcache.writebacks::total 442964 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 729519 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 729519 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1626163 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1626163 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2355682 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2355682 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2355682 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2355682 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200056 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200056 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262047 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262047 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 443776 # number of writebacks +system.cpu.dcache.writebacks::total 443776 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 726784 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 726784 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628507 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628507 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2355291 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2355291 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2355291 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2355291 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200740 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200740 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262366 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262366 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 462103 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 462103 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 462103 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 462103 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2627957000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2627957000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4314187000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4314187000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 463106 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463106 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463106 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463106 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2634282500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2634282500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319277500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319277500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 108000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 108000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942144000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6942144000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942144000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6942144000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001571 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6953560000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6953560000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6953560000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6953560000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001572 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001572 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001254 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13136.106890 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13136.106890 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16463.409236 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16463.409236 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13122.857926 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13122.857926 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16462.794341 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16462.794341 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 15428.571429 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 15428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15022.936445 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15022.936445 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15022.936445 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15022.936445 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15015.050550 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15015.050550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15015.050550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15015.050550 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22458.024259 # Cycle average of tags in use -system.cpu.l2cache.total_refs 548899 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24278 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.608905 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20744.377954 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1070.274135 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 643.372169 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633068 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.032662 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019634 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.685365 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 165 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 195629 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 195794 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 442964 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 442964 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 240255 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 240255 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 165 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 435884 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 436049 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 165 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 435884 # number of overall hits -system.cpu.l2cache.overall_hits::total 436049 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1204 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4426 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5630 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21800 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21800 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26226 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27430 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1204 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26226 # number of overall misses -system.cpu.l2cache.overall_misses::total 27430 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57312000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 469280500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 526592500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1549286000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1549286000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 57312000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2018566500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2075878500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 57312000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2018566500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2075878500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1369 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 200055 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 201424 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 442964 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 442964 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 262055 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 262055 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1369 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 462110 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 463479 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1369 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 462110 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 463479 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.879474 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022124 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.027951 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083189 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083189 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.879474 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.056753 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059183 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.879474 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.056753 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059183 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47601.328904 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 106028.129236 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 93533.303730 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71068.165138 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71068.165138 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47601.328904 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76968.142302 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75679.128691 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47601.328904 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76968.142302 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75679.128691 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks -system.cpu.l2cache.writebacks::total 2533 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1204 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4426 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5630 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21800 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21800 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1204 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26226 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27430 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1204 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26226 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27430 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42159963 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 413894207 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 456054170 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1275808135 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1275808135 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42159963 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1689702342 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1731862305 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42159963 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1689702342 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1731862305 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.879474 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022124 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027951 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083189 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083189 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.879474 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056753 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059183 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.879474 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056753 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059183 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35016.580565 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 93514.280840 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 81004.293073 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58523.308945 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58523.308945 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35016.580565 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64428.519103 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63137.524790 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35016.580565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64428.519103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63137.524790 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index abf2e74d2..f6f519501 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,17 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system @@ -158,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[3] @@ -430,17 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system @@ -453,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -462,6 +465,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -470,30 +476,31 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -503,10 +510,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -521,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -543,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleMemory -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index dbf6b4770..48eb9aa0f 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 22:44:55 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Oct 30 2012 11:14:29 +gem5 started Oct 30 2012 16:17:19 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -20,10 +18,10 @@ Uncompressing Data info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly -info: Increasing stack size by one page. Compressing Input Data, level 3 Compressed data 97831 bytes in length Uncompressing Data +info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 @@ -42,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 609566727000 because target called exit() +Exiting @ tick 607235830000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 43ee6670c..74f46e926 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.610645 # Number of seconds simulated -sim_ticks 610645123000 # Number of ticks simulated -final_tick 610645123000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.607236 # Number of seconds simulated +sim_ticks 607235830000 # Number of ticks simulated +final_tick 607235830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90668 # Simulator instruction rate (inst/s) -host_op_rate 167061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62914134 # Simulator tick rate (ticks/s) -host_mem_usage 229848 # Number of bytes of host memory used -host_seconds 9706.01 # Real time elapsed on the host +host_inst_rate 71722 # Simulator instruction rate (inst/s) +host_op_rate 132152 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49489751 # Simulator tick rate (ticks/s) +host_mem_usage 226812 # Number of bytes of host memory used +host_seconds 12269.93 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493925 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 58048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1693312 # Number of bytes read from this memory -system.physmem.bytes_read::total 1751360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 58048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 58048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162176 # Number of bytes written to this memory -system.physmem.bytes_written::total 162176 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26458 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27365 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2534 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2534 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2772989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2868049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95060 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95060 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 265581 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 265581 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 265581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2772989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3133630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27367 # Total number of read requests seen -system.physmem.writeReqs 2534 # Total number of write requests seen -system.physmem.cpureqs 29901 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1751360 # Total number of bytes read from memory -system.physmem.bytesWritten 162176 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1751360 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162176 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 57472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1693120 # Number of bytes read from this memory +system.physmem.bytes_read::total 1750592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 57472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 57472 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory +system.physmem.bytes_written::total 162112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27353 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 94645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2788241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2882887 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94645 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94645 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 266967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 266967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 266967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2788241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3149854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27355 # Total number of read requests seen +system.physmem.writeReqs 2533 # Total number of write requests seen +system.physmem.cpureqs 29888 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1750592 # Total number of bytes read from memory +system.physmem.bytesWritten 162112 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1750592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1748 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1747 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1672 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1754 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1756 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1780 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1754 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1779 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 1777 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1811 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1808 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1637 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1638 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1660 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1692 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1691 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis @@ -72,19 +72,19 @@ system.physmem.perBankWrReqs::9 158 # Tr system.physmem.perBankWrReqs::10 154 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 154 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 156 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 156 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 610645109000 # Total gap between requests +system.physmem.totGap 607235813000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27367 # Categorize read packet sizes +system.physmem.readPktSize::6 27355 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2534 # categorize write packet sizes +system.physmem.writePktSize::6 2533 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 26902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 26898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -141,7 +141,7 @@ system.physmem.rdQLenPdf::32 0 # Wh system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see @@ -171,264 +171,264 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 68648669 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 822368669 # Sum of mem lat for all requests -system.physmem.totBusLat 109468000 # Total cycles spent in databus access -system.physmem.totBankLat 644252000 # Total cycles spent in bank access -system.physmem.avgQLat 2508.45 # Average queueing delay per request -system.physmem.avgBankLat 23541.20 # Average bank access latency per request +system.physmem.totQLat 67414668 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 820820668 # Sum of mem lat for all requests +system.physmem.totBusLat 109420000 # Total cycles spent in databus access +system.physmem.totBankLat 643986000 # Total cycles spent in bank access +system.physmem.avgQLat 2464.44 # Average queueing delay per request +system.physmem.avgBankLat 23541.80 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30049.65 # Average memory access latency -system.physmem.avgRdBW 2.87 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 30006.24 # Average memory access latency +system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.27 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 9.42 # Average write queue length over time -system.physmem.readRowHits 17709 # Number of row buffer hits during reads -system.physmem.writeRowHits 1083 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 42.74 # Row buffer hit rate for writes -system.physmem.avgGap 20422230.33 # Average gap between requests +system.physmem.avgWrQLen 4.32 # Average write queue length over time +system.physmem.readRowHits 17706 # Number of row buffer hits during reads +system.physmem.writeRowHits 1086 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 42.87 # Row buffer hit rate for writes +system.physmem.avgGap 20317044.06 # Average gap between requests system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1221290247 # number of cpu cycles simulated +system.cpu.numCycles 1214471661 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 153796448 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 153796448 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26699295 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 76444965 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 76044325 # Number of BTB hits +system.cpu.BPredUnit.lookups 158566645 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 158566645 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26386333 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 83466743 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 83279512 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180218290 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1484873312 # Number of instructions fetch has processed -system.cpu.fetch.Branches 153796448 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 76044325 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 400561886 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 92153015 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 574855756 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 434 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 186235545 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9536973 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1220934154 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.078258 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.273787 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 179036467 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1457944289 # Number of instructions fetch has processed +system.cpu.fetch.Branches 158566645 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83279512 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 399021545 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88092537 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 574509498 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 50 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 341 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 186960601 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10940939 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1214117357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.059847 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.253407 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 827594377 67.78% 67.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24117068 1.98% 69.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15648261 1.28% 71.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17796387 1.46% 72.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26716755 2.19% 74.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18183763 1.49% 76.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 28386980 2.33% 78.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39418545 3.23% 81.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 223072018 18.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 822311931 67.73% 67.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26973525 2.22% 69.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 13085420 1.08% 71.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20645432 1.70% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26636403 2.19% 74.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18254688 1.50% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31306986 2.58% 79.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39069186 3.22% 82.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 215833786 17.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1220934154 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.125929 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.215823 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 289407961 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 498246191 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 275145699 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92836570 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 65297733 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2356719721 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 65297733 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 337924282 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 123917110 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2381 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 305534064 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 388258584 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2260509367 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 337 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242606329 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120880984 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2627145665 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5770220684 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5770216108 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4576 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1214117357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130564 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.200476 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 288149545 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 497851788 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 274001581 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92564987 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 61549456 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2343342483 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 61549456 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 336776305 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124136399 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2472 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303957244 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387695481 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2247540252 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 338 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242690737 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120190709 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2617793255 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5721514338 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5721508630 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5708 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895257 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 740250408 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 92 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 92 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 731279841 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542420235 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220423040 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 348990798 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 145234295 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2013682993 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 521 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1784560921 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 286575 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 391758246 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 817229320 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 471 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1220934154 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.461636 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.419528 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 730897998 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 87 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 731315186 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 531685334 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 219218078 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 341957322 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144669482 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1993566712 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1783999852 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 259167 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 371673921 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 759176081 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 236 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1214117357 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.469380 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.421908 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 365719162 29.95% 29.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 365027224 29.90% 59.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234751927 19.23% 79.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141361627 11.58% 90.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60962306 4.99% 95.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39637127 3.25% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10977510 0.90% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1933125 0.16% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 564146 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360157334 29.66% 29.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 364096004 29.99% 59.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234218772 19.29% 78.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141579875 11.66% 90.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60576135 4.99% 95.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39770363 3.28% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11069235 0.91% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2042198 0.17% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 607441 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1220934154 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1214117357 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 457693 15.95% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2209699 77.01% 92.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 202113 7.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 448044 15.51% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2239769 77.53% 93.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 201121 6.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812464 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1065891237 59.73% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 479189352 26.85% 89.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192667868 10.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812236 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065749303 59.74% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 478900937 26.84% 89.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192537376 10.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1784560921 # Type of FU issued -system.cpu.iq.rate 1.461210 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2869505 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001608 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4793211641 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2405618854 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1725377736 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 435 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1480 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 90 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1740617772 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 190 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 209954463 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1783999852 # Type of FU issued +system.cpu.iq.rate 1.468951 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2888934 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001619 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4785264711 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2365417546 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1724692001 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 451 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1804 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1740076331 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 219 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 209988104 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 123378114 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 38587 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 183844 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 32236983 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 112643213 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 39222 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 182717 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31032021 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2078 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2338 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 61 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 65297733 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1143885 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 111744 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2013683514 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63490304 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542420235 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220423040 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 86 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 55193 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2862 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 183844 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2121921 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24727534 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26849455 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766386720 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 474113432 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18174201 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 61549456 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1140639 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 111456 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1993566998 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 62891461 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 531685334 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 219218078 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 82 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 54713 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2863 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 182717 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2045566 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24470672 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26516238 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766182455 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474610807 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17817397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 665931472 # number of memory reference insts executed -system.cpu.iew.exec_branches 110216269 # Number of branches executed -system.cpu.iew.exec_stores 191818040 # Number of stores executed -system.cpu.iew.exec_rate 1.446328 # Inst execution rate -system.cpu.iew.wb_sent 1726595079 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1725377826 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1268018973 # num instructions producing a value -system.cpu.iew.wb_consumers 1829950696 # num instructions consuming a value +system.cpu.iew.exec_refs 666317556 # number of memory reference insts executed +system.cpu.iew.exec_branches 110350315 # Number of branches executed +system.cpu.iew.exec_stores 191706749 # Number of stores executed +system.cpu.iew.exec_rate 1.454281 # Inst execution rate +system.cpu.iew.wb_sent 1725793430 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1724692117 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1267138729 # num instructions producing a value +system.cpu.iew.wb_consumers 1828924593 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.412750 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692925 # average fanout of values written-back +system.cpu.iew.wb_rate 1.420117 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692833 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 392192006 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 372074312 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26699352 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1155636421 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.403118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.832114 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26386383 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1152567901 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.406853 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.830346 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 422545803 36.56% 36.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 413097230 35.75% 72.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87361742 7.56% 79.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122290747 10.58% 90.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24514270 2.12% 92.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22708378 1.97% 94.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18848985 1.63% 96.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12046038 1.04% 97.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32223228 2.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 417955350 36.26% 36.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 415054079 36.01% 72.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86939331 7.54% 79.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122127082 10.60% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24184880 2.10% 92.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25402622 2.20% 94.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16383099 1.42% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12042950 1.04% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32478508 2.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1155636421 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1152567901 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -439,148 +439,290 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32223228 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32478508 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3137099124 # The number of ROB reads -system.cpu.rob.rob_writes 4092706915 # The number of ROB writes -system.cpu.timesIdled 59218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 356093 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3113657630 # The number of ROB reads +system.cpu.rob.rob_writes 4048721682 # The number of ROB writes +system.cpu.timesIdled 59087 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 354304 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.387790 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.387790 # CPI: Total CPI of All Threads -system.cpu.ipc 0.720570 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.720570 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3541569732 # number of integer regfile reads -system.cpu.int_regfile_writes 1975385267 # number of integer regfile writes -system.cpu.fp_regfile_reads 90 # number of floating regfile reads -system.cpu.misc_regfile_reads 910403293 # number of misc regfile reads -system.cpu.icache.replacements 20 # number of replacements -system.cpu.icache.tagsinuse 822.205718 # Cycle average of tags in use -system.cpu.icache.total_refs 186234150 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 202648.694233 # Average number of references to valid blocks. +system.cpu.cpi 1.380042 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.380042 # CPI: Total CPI of All Threads +system.cpu.ipc 0.724616 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.724616 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3542913524 # number of integer regfile reads +system.cpu.int_regfile_writes 1974599259 # number of integer regfile writes +system.cpu.fp_regfile_reads 116 # number of floating regfile reads +system.cpu.misc_regfile_reads 910763104 # number of misc regfile reads +system.cpu.icache.replacements 26 # number of replacements +system.cpu.icache.tagsinuse 814.074374 # Cycle average of tags in use +system.cpu.icache.total_refs 186959214 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 915 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 204327.009836 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 822.205718 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.401468 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.401468 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 186234151 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 186234151 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 186234151 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 186234151 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 186234151 # number of overall hits -system.cpu.icache.overall_hits::total 186234151 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1394 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1394 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1394 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1394 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1394 # number of overall misses -system.cpu.icache.overall_misses::total 1394 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 63295000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 63295000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 63295000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 63295000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 63295000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 63295000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 186235545 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 186235545 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 186235545 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 186235545 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 186235545 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 186235545 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 814.074374 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.397497 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.397497 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 186959220 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 186959220 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 186959220 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 186959220 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 186959220 # number of overall hits +system.cpu.icache.overall_hits::total 186959220 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1381 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1381 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1381 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1381 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1381 # number of overall misses +system.cpu.icache.overall_misses::total 1381 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 63796500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 63796500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 63796500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 63796500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 63796500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 63796500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 186960601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 186960601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 186960601 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 186960601 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 186960601 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 186960601 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45405.308465 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45405.308465 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45405.308465 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45405.308465 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45405.308465 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45405.308465 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46195.872556 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46195.872556 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46195.872556 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46195.872556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46195.872556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46195.872556 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 249 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 472 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 472 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 472 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 472 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 472 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 472 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 459 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 459 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 459 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 459 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 459 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 922 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 922 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 922 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 922 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 922 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 922 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46053000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46053000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46053000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46053000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46053000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46053000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45726500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45726500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45726500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45726500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45726500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45726500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49949.023861 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49949.023861 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49949.023861 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49949.023861 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49949.023861 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49949.023861 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49594.902386 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49594.902386 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49594.902386 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49594.902386 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49594.902386 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49594.902386 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 445401 # number of replacements -system.cpu.dcache.tagsinuse 4092.926016 # Cycle average of tags in use -system.cpu.dcache.total_refs 451884939 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 449497 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1005.312469 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 828056000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4092.926016 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999250 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999250 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 263945150 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 263945150 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187939786 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187939786 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 451884936 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 451884936 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 451884936 # number of overall hits -system.cpu.dcache.overall_hits::total 451884936 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 210668 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 210668 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 246271 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 246271 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 456939 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 456939 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 456939 # number of overall misses -system.cpu.dcache.overall_misses::total 456939 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3009925000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3009925000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4061663000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4061663000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7071588000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7071588000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7071588000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7071588000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264155818 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264155818 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.replacements 2555 # number of replacements +system.cpu.l2cache.tagsinuse 22258.583797 # Cycle average of tags in use +system.cpu.l2cache.total_refs 531214 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24187 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6091750500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6091750500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6091750500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12385.744642 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12385.744642 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14494.049650 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14494.049650 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13540.515859 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13540.515859 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13540.515859 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13540.515859 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12382.792595 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12382.792595 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14489.244715 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14489.244715 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13535.809593 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13535.809593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13535.809593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13535.809593 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22261.498307 # Cycle average of tags in use -system.cpu.l2cache.total_refs 530423 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24197 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.921023 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20782.532445 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 804.542121 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 674.423741 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.634233 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.024553 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020582 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.679367 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 198746 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 198758 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 428512 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 428512 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224294 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 224294 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 423040 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 423052 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 423040 # number of overall hits -system.cpu.l2cache.overall_hits::total 423052 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 907 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4543 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5450 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21917 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21917 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 907 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26460 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27367 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 907 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26460 # number of overall misses -system.cpu.l2cache.overall_misses::total 27367 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44997500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 325370000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 370367500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1079389000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1079389000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 44997500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1404759000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1449756500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 44997500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1404759000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1449756500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 919 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 203289 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 204208 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 428512 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 428512 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246211 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246211 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 919 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 449500 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 450419 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 919 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 449500 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 450419 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.986942 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022347 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.026688 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089017 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.089017 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.986942 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.058865 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060759 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.986942 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.058865 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060759 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49611.356119 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71620.074840 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67957.339450 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49248.939180 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49248.939180 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49611.356119 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53089.909297 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52974.622721 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49611.356119 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53089.909297 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52974.622721 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2534 # number of writebacks -system.cpu.l2cache.writebacks::total 2534 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 907 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4543 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5450 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21917 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21917 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 907 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26460 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27367 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 907 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26460 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27367 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33582421 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 267466906 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301049327 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 797222639 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 797222639 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33582421 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1064689545 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1098271966 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33582421 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1064689545 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1098271966 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022347 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026688 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089017 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089017 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058865 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060759 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058865 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060759 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37025.822492 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58874.511556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55238.408624 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36374.624219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36374.624219 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37025.822492 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40237.700113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40131.251727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37025.822492 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40237.700113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40131.251727 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |