diff options
Diffstat (limited to 'tests/long/se/00.gzip')
9 files changed, 3659 insertions, 3643 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index eaa40425f..01d17fd64 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.271565 # Number of seconds simulated -sim_ticks 271565222500 # Number of ticks simulated -final_tick 271565222500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.269731 # Number of seconds simulated +sim_ticks 269730745500 # Number of ticks simulated +final_tick 269730745500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118122 # Simulator instruction rate (inst/s) -host_op_rate 118122 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53298093 # Simulator tick rate (ticks/s) -host_mem_usage 217868 # Number of bytes of host memory used -host_seconds 5095.21 # Real time elapsed on the host +host_inst_rate 168515 # Simulator instruction rate (inst/s) +host_op_rate 168515 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75522303 # Simulator tick rate (ticks/s) +host_mem_usage 218132 # Number of bytes of host memory used +host_seconds 3571.54 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1620224 # Number of bytes read from this memory -system.physmem.bytes_read::total 1674048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1628992 # Number of bytes read from this memory +system.physmem.bytes_read::total 1682816 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 57024 # Number of bytes written to this memory -system.physmem.bytes_written::total 57024 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 64896 # Number of bytes written to this memory +system.physmem.bytes_written::total 64896 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25316 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory -system.physmem.num_writes::total 891 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 198199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5966243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6164442 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 198199 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 198199 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 209983 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 209983 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 209983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 198199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5966243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6374424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26157 # Total number of read requests seen -system.physmem.writeReqs 891 # Total number of write requests seen -system.physmem.cpureqs 27048 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1674048 # Total number of bytes read from memory -system.physmem.bytesWritten 57024 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1674048 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 57024 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu.data 25453 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 199547 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6039326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6238873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199547 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199547 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 240595 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 240595 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 240595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199547 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6039326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6479469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26294 # Total number of read requests seen +system.physmem.writeReqs 1014 # Total number of write requests seen +system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1682816 # Total number of bytes read from memory +system.physmem.bytesWritten 64896 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1682816 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1710 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1560 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1574 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1699 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1625 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1662 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1553 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1614 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1596 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1666 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 58 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 65 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 65 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 53 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 67 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 71 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 48 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 52 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 41 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 49 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 54 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 60 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1732 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1568 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1581 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1632 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1558 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1618 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1600 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1550 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1652 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1697 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1675 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 76 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 52 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 60 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 81 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 53 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 55 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 58 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 271565170500 # Total gap between requests +system.physmem.totGap 269730693500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26157 # Categorize read packet sizes +system.physmem.readPktSize::6 26294 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 891 # categorize write packet sizes +system.physmem.writePktSize::6 1014 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 22499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 17613 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 129156577 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 809724577 # Sum of mem lat for all requests -system.physmem.totBusLat 104608000 # Total cycles spent in databus access -system.physmem.totBankLat 575960000 # Total cycles spent in bank access -system.physmem.avgQLat 4938.69 # Average queueing delay per request -system.physmem.avgBankLat 22023.55 # Average bank access latency per request +system.physmem.totQLat 360576187 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1020404187 # Sum of mem lat for all requests +system.physmem.totBusLat 105120000 # Total cycles spent in databus access +system.physmem.totBankLat 554708000 # Total cycles spent in bank access +system.physmem.avgQLat 13720.56 # Average queueing delay per request +system.physmem.avgBankLat 21107.61 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30962.24 # Average memory access latency -system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.21 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.21 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38828.17 # Average memory access latency +system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.24 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 7.68 # Average write queue length over time -system.physmem.readRowHits 17269 # Number of row buffer hits during reads -system.physmem.writeRowHits 120 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 13.47 # Row buffer hit rate for writes -system.physmem.avgGap 10040120.18 # Average gap between requests +system.physmem.avgWrQLen 12.19 # Average write queue length over time +system.physmem.readRowHits 17405 # Number of row buffer hits during reads +system.physmem.writeRowHits 51 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes +system.physmem.avgGap 9877350.72 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517787 # DTB read hits +system.cpu.dtb.read_hits 114517567 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520418 # DTB read accesses -system.cpu.dtb.write_hits 39661841 # DTB write hits +system.cpu.dtb.read_accesses 114520198 # DTB read accesses +system.cpu.dtb.write_hits 39453373 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39664143 # DTB write accesses -system.cpu.dtb.data_hits 154179628 # DTB hits +system.cpu.dtb.write_accesses 39455675 # DTB write accesses +system.cpu.dtb.data_hits 153970940 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154184561 # DTB accesses -system.cpu.itb.fetch_hits 25070821 # ITB hits +system.cpu.dtb.data_accesses 153975873 # DTB accesses +system.cpu.itb.fetch_hits 25065868 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25070843 # ITB accesses +system.cpu.itb.fetch_accesses 25065890 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 543130446 # number of cpu cycles simulated +system.cpu.numCycles 539461492 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 86310002 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 81365597 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 36354316 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 52694902 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 34317638 # Number of BTB hits +system.cpu.branch_predictor.lookups 86297721 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 81352852 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36357676 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 52914836 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 34319624 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 65.125158 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 36895088 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49414914 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541552418 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 64.858226 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 36896934 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49400787 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541636673 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005407264 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1005491519 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255071398 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 155051796 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 33757784 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 2591545 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 36349329 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 26198578 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 58.114381 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412334991 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 254989713 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 155053642 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 33759621 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 2593068 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36352689 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 26195221 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.119750 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 412334808 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 538350006 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 535900413 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 387710 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 54025519 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489104927 # Number of cycles cpu stages are processed. -system.cpu.activity 90.052939 # Percentage of cycles cpu is active +system.cpu.timesIdled 295985 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50743768 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 488717724 # Number of cycles cpu stages are processed. +system.cpu.activity 90.593626 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -272,144 +272,144 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.902424 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.896328 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.902424 # CPI: Total CPI of All Threads -system.cpu.ipc 1.108126 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.896328 # CPI: Total CPI of All Threads +system.cpu.ipc 1.115663 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.108126 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 204275308 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338855138 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.389273 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 232303926 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310826520 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.228705 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 201351117 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341779329 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.927669 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 431560271 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111570175 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.542059 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 196153041 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 346977405 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.884727 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.115663 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 200698192 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338763300 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.796568 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 228822575 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310638917 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.583149 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 197865765 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341595727 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.321615 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 428073840 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111387652 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.647934 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 192651610 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346809882 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.288163 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 729.013382 # Cycle average of tags in use -system.cpu.icache.total_refs 25069798 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.083311 # Cycle average of tags in use +system.cpu.icache.total_refs 25064833 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29321.401170 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29315.594152 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 729.013382 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.355964 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.355964 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25069798 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25069798 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25069798 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25069798 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25069798 # number of overall hits -system.cpu.icache.overall_hits::total 25069798 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses -system.cpu.icache.overall_misses::total 1021 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 53787000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 53787000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 53787000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 53787000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 53787000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 53787000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25070819 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25070819 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25070819 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25070819 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25070819 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25070819 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 729.083311 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.355998 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.355998 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25064833 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25064833 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25064833 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25064833 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25064833 # number of overall hits +system.cpu.icache.overall_hits::total 25064833 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1035 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1035 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1035 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1035 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1035 # number of overall misses +system.cpu.icache.overall_misses::total 1035 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 52854000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 52854000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 52854000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 52854000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 52854000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 52854000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25065868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25065868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25065868 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25065868 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25065868 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25065868 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52680.705191 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52680.705191 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52680.705191 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52680.705191 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52680.705191 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52680.705191 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 109 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 36.333333 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51066.666667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51066.666667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51066.666667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51066.666667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51066.666667 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 93.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 180 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 180 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 180 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 180 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 180 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43651000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43651000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43651000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43651000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43651000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43651000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43286500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43286500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43286500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43286500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43286500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43286500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51053.801170 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51053.801170 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51053.801170 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51053.801170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51053.801170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51053.801170 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50627.485380 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50627.485380 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50627.485380 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50627.485380 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.593977 # Cycle average of tags in use -system.cpu.dcache.total_refs 152406549 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4093.419858 # Cycle average of tags in use +system.cpu.dcache.total_refs 151786041 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.668912 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 342752000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.593977 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999413 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999413 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120505 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120505 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38286044 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38286044 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 152406549 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152406549 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152406549 # number of overall hits -system.cpu.dcache.overall_hits::total 152406549 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393537 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393537 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1165277 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1165277 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1558814 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1558814 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1558814 # number of overall misses -system.cpu.dcache.overall_misses::total 1558814 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5631779500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5631779500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16513706000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16513706000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22145485500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22145485500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22145485500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22145485500 # number of overall miss cycles +system.cpu.dcache.avg_refs 333.306341 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.419858 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37665413 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37665413 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 151786041 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 151786041 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 151786041 # number of overall hits +system.cpu.dcache.overall_hits::total 151786041 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1785908 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1785908 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2179322 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2179322 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2179322 # number of overall misses +system.cpu.dcache.overall_misses::total 2179322 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5991589500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5991589500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22875440000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22875440000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28867029500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28867029500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28867029500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28867029500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -418,40 +418,40 @@ system.cpu.dcache.demand_accesses::cpu.data 153965363 # system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029537 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029537 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010124 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010124 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010124 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010124 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14310.673456 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14310.673456 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14171.485406 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14171.485406 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14206.624716 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14206.624716 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14206.624716 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14206.624716 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 44530 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3993200 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3165 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 211455 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.069510 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18.884396 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15229.731275 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15229.731275 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12808.856895 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12808.856895 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13245.876240 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13245.876240 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13245.876240 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 165761 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 544 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5600 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.600179 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 60.444444 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks -system.cpu.dcache.writebacks::total 436902 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192305 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192305 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911114 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 911114 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1103419 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1103419 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1103419 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1103419 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks +system.cpu.dcache.writebacks::total 436887 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531745 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1531745 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1723927 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1723927 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1723927 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1723927 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -460,14 +460,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2467175500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2467175500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3742658000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3742658000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6209833500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6209833500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6209833500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6209833500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645854500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645854500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3731128500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3731128500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6376983000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6376983000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6376983000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6376983000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -476,68 +476,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12260.353721 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12260.353721 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14725.424236 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14725.424236 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13636.147740 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13636.147740 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13636.147740 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13636.147740 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13148.279101 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13148.279101 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14680.061614 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14680.061614 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14003.190637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14003.190637 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 917 # number of replacements -system.cpu.l2cache.tagsinuse 22846.870251 # Cycle average of tags in use -system.cpu.l2cache.total_refs 538836 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.283899 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1042 # number of replacements +system.cpu.l2cache.tagsinuse 22878.552216 # Cycle average of tags in use +system.cpu.l2cache.total_refs 531848 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.846686 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21647.185426 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 719.934202 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 479.750624 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.660620 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021971 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014641 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.697231 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21684.756059 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 718.203653 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 475.592503 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.661766 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021918 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014514 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.698198 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 197087 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 197101 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232992 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232992 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 436887 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 436887 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 232860 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 232860 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 430079 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 430093 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 429942 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 429956 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 430079 # number of overall hits -system.cpu.l2cache.overall_hits::total 430093 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 429942 # number of overall hits +system.cpu.l2cache.overall_hits::total 429956 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1619571500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1661852000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 42280500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1619571500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1661852000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 436887 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 436887 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 254188 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 254188 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses @@ -547,81 +547,81 @@ system.cpu.l2cache.overall_accesses::cpu.inst 855 system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020476 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083387 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083387 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020501 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024577 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083906 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083906 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.055892 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.057631 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50704.518430 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69769.053398 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66537.190083 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54648.447820 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54648.447820 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50704.518430 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57109.219466 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 56903.295485 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50704.518430 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57109.219466 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 56903.295485 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 2538 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50274.078478 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114589.454545 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 103697.543294 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53773.912228 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53773.912228 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 63202.707842 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50274.078478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63629.886457 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 63202.707842 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 230.727273 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 891 # number of writebacks -system.cpu.l2cache.writebacks::total 891 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1014 # number of writebacks +system.cpu.l2cache.writebacks::total 1014 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 841 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4120 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4961 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21196 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21196 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4125 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4966 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21328 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21328 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 841 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 25316 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 26157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 25453 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26294 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32026854 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 234985616 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 267012470 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891005143 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891005143 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32026854 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1125990759 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1158017613 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32026854 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1125990759 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1158017613 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31666859 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 419253922 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 450920781 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 877062534 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 877062534 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31666859 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1296316456 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1327983315 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31666859 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1296316456 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1327983315 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024552 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083387 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083387 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083906 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38081.871581 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57035.343689 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53822.308002 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42036.475892 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42036.475892 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38081.871581 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44477.435574 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44271.805368 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38081.871581 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44477.435574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44271.805368 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37653.815696 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101637.314424 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 90801.607128 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41122.586928 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41122.586928 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37653.815696 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50929.810081 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.184263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37653.815696 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50929.810081 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.184263 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 28d2d6014..82eaca8c6 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133501 # Number of seconds simulated -sim_ticks 133501490500 # Number of ticks simulated -final_tick 133501490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.135739 # Number of seconds simulated +sim_ticks 135738546500 # Number of ticks simulated +final_tick 135738546500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263578 # Simulator instruction rate (inst/s) -host_op_rate 263578 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62218941 # Simulator tick rate (ticks/s) -host_mem_usage 217856 # Number of bytes of host memory used -host_seconds 2145.67 # Real time elapsed on the host +host_inst_rate 149707 # Simulator instruction rate (inst/s) +host_op_rate 149707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35931284 # Simulator tick rate (ticks/s) +host_mem_usage 219152 # Number of bytes of host memory used +host_seconds 3777.73 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1627136 # Number of bytes read from this memory -system.physmem.bytes_read::total 1688448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 58752 # Number of bytes written to this memory -system.physmem.bytes_written::total 58752 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25424 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26382 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 918 # Number of write requests responded to by this memory -system.physmem.num_writes::total 918 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 459261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12188149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12647409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 459261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 459261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 440085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 440085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 440085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 459261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12188149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13087494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26382 # Total number of read requests seen -system.physmem.writeReqs 918 # Total number of write requests seen -system.physmem.cpureqs 27300 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1688448 # Total number of bytes read from memory -system.physmem.bytesWritten 58752 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1688448 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 58752 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636160 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory +system.physmem.bytes_written::total 67072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25565 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26528 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 454049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12053761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12507810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 454049 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 454049 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 494126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 494126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 494126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 454049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12053761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13001937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26528 # Total number of read requests seen +system.physmem.writeReqs 1048 # Total number of write requests seen +system.physmem.cpureqs 27576 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697792 # Total number of bytes read from memory +system.physmem.bytesWritten 67072 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697792 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1716 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1633 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1563 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1614 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1549 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1659 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1668 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 58 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 67 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 52 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 55 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 53 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 67 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 72 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 49 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 52 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 55 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 42 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 53 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 54 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 63 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 60 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1636 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1683 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1681 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1569 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1630 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1617 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1555 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1678 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 78 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 55 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 60 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 75 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 62 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 78 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 83 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 54 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 59 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 80 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 133501465500 # Total gap between requests +system.physmem.totGap 135738512500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26382 # Categorize read packet sizes +system.physmem.readPktSize::6 26528 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 918 # categorize write packet sizes +system.physmem.writePktSize::6 1048 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 5916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1000 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 842096821 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1422758821 # Sum of mem lat for all requests -system.physmem.totBusLat 105516000 # Total cycles spent in databus access -system.physmem.totBankLat 475146000 # Total cycles spent in bank access -system.physmem.avgQLat 31923.00 # Average queueing delay per request -system.physmem.avgBankLat 18012.28 # Average bank access latency per request +system.physmem.totQLat 656768415 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1272742415 # Sum of mem lat for all requests +system.physmem.totBusLat 106052000 # Total cycles spent in databus access +system.physmem.totBankLat 509922000 # Total cycles spent in bank access +system.physmem.avgQLat 24771.56 # Average queueing delay per request +system.physmem.avgBankLat 19232.90 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53935.28 # Average memory access latency -system.physmem.avgRdBW 12.65 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.44 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 12.65 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.44 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 48004.47 # Average memory access latency +system.physmem.avgRdBW 12.51 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.49 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 12.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.49 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.08 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.07 # Average write queue length over time -system.physmem.readRowHits 17947 # Number of row buffer hits during reads -system.physmem.writeRowHits 124 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 13.51 # Row buffer hit rate for writes -system.physmem.avgGap 4890163.57 # Average gap between requests +system.physmem.avgWrQLen 10.03 # Average write queue length over time +system.physmem.readRowHits 18053 # Number of row buffer hits during reads +system.physmem.writeRowHits 56 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 5.34 # Row buffer hit rate for writes +system.physmem.avgGap 4922342.34 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123834550 # DTB read hits -system.cpu.dtb.read_misses 17810 # DTB read misses +system.cpu.dtb.read_hits 123922794 # DTB read hits +system.cpu.dtb.read_misses 28366 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 123852360 # DTB read accesses -system.cpu.dtb.write_hits 40838763 # DTB write hits -system.cpu.dtb.write_misses 27151 # DTB write misses +system.cpu.dtb.read_accesses 123951160 # DTB read accesses +system.cpu.dtb.write_hits 40833980 # DTB write hits +system.cpu.dtb.write_misses 25612 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40865914 # DTB write accesses -system.cpu.dtb.data_hits 164673313 # DTB hits -system.cpu.dtb.data_misses 44961 # DTB misses +system.cpu.dtb.write_accesses 40859592 # DTB write accesses +system.cpu.dtb.data_hits 164756774 # DTB hits +system.cpu.dtb.data_misses 53978 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164718274 # DTB accesses -system.cpu.itb.fetch_hits 66485884 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 164810752 # DTB accesses +system.cpu.itb.fetch_hits 66580671 # ITB hits +system.cpu.itb.fetch_misses 40 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66485922 # ITB accesses +system.cpu.itb.fetch_accesses 66580711 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,245 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267002982 # number of cpu cycles simulated +system.cpu.numCycles 271477094 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78490289 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72847815 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3050228 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42945683 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41640479 # Number of BTB hits +system.cpu.BPredUnit.lookups 78553522 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72909571 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3050106 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42863354 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41672348 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1629196 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68428860 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 710798920 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78490289 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43269675 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119192583 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12919622 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 69466328 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1179 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 66485884 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 944600 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 266949725 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.662670 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.464655 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1629524 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 245 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68542455 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 711581178 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78553522 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43301872 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119313775 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13045820 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73380337 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 247 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1305 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 7 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66580671 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 946763 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 271202747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.623798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454049 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 147757142 55.35% 55.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10366639 3.88% 59.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11845375 4.44% 63.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10612007 3.98% 67.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6988496 2.62% 70.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2666505 1.00% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3491309 1.31% 72.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3106869 1.16% 73.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70115383 26.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 151888972 56.01% 56.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10373570 3.83% 59.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11841110 4.37% 64.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10622549 3.92% 68.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7004922 2.58% 70.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2671761 0.99% 71.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3503178 1.29% 72.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3113300 1.15% 74.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70183385 25.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 266949725 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.293968 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.662139 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85457793 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 53956348 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104522021 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13153880 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9859683 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3909548 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1132 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 702023291 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5115 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9859683 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93690944 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11427696 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1077 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104202524 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 47767801 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 690131281 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 37133482 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4417196 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527277904 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 906836279 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 906833414 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2865 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 271202747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.289356 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.621146 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 86023061 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57429003 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104152322 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13634796 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9963565 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3909126 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1128 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 702760367 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4141 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9963565 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 94304341 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12784998 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1531 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104174044 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49974268 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 690768624 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 416 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38037873 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5669894 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527681051 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 907529781 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 907526811 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2970 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63423015 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 63826162 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 100 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 107 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 106239657 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 128990605 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42428237 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14728779 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9525532 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626440684 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608386027 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 332535 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60195764 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33399973 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 74 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 266949725 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.279028 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.823675 # Number of insts issued each cycle +system.cpu.rename.skidInsts 112138467 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 129142032 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42466663 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14842304 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10368291 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626932339 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 92 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608621790 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 344229 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60678365 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33855512 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 271202747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.244158 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.828491 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52346454 19.61% 19.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 53679990 20.11% 39.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53956371 20.21% 59.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 37644200 14.10% 74.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31434632 11.78% 85.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23774675 8.91% 94.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10171294 3.81% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3315844 1.24% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 626265 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55518105 20.47% 20.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55264401 20.38% 40.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53914091 19.88% 60.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 37013789 13.65% 74.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31720099 11.70% 86.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23689667 8.74% 94.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10003906 3.69% 98.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3493839 1.29% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 584850 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 266949725 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 271202747 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2688356 76.19% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 516717 14.64% 90.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 323442 9.17% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2803923 71.85% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 36 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 717323 18.38% 90.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 381401 9.77% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441007420 72.49% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7412 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126109044 20.73% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41262108 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441148473 72.48% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7331 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126212456 20.74% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41253487 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608386027 # Type of FU issued -system.cpu.iq.rate 2.278574 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3528520 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005800 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1487578943 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 686639010 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598810761 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3891 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2383 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1718 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 611912593 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1954 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12176241 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 608621790 # Type of FU issued +system.cpu.iq.rate 2.241890 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3902683 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006412 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1492689315 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 687613743 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598990581 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3924 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2505 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1722 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 612522503 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1970 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12211500 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14476563 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33526 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4894 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2976916 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14627990 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 32965 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5519 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3015342 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6758 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 144 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6777 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 53391 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9859683 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 765668 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 16511 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 670353065 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1690084 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 128990605 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42428237 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6929 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3539 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4894 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1348243 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2207087 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3555330 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602565477 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 123852464 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5820550 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9963565 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1456092 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 187737 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 670933978 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1716868 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 129142032 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42466663 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 92 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 140012 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7404 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5519 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1345446 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2210203 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3555649 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602801961 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 123951309 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5819829 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 43912290 # number of nop insts executed -system.cpu.iew.exec_refs 164735376 # number of memory reference insts executed -system.cpu.iew.exec_branches 67003758 # Number of branches executed -system.cpu.iew.exec_stores 40882912 # Number of stores executed -system.cpu.iew.exec_rate 2.256774 # Inst execution rate -system.cpu.iew.wb_sent 600054937 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598812479 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417702193 # num instructions producing a value -system.cpu.iew.wb_consumers 531441219 # num instructions consuming a value +system.cpu.iew.exec_nop 44001547 # number of nop insts executed +system.cpu.iew.exec_refs 164826908 # number of memory reference insts executed +system.cpu.iew.exec_branches 67037045 # Number of branches executed +system.cpu.iew.exec_stores 40875599 # Number of stores executed +system.cpu.iew.exec_rate 2.220452 # Inst execution rate +system.cpu.iew.wb_sent 600240253 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598992303 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417488059 # num instructions producing a value +system.cpu.iew.wb_consumers 532706701 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.242718 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.785980 # average fanout of values written-back +system.cpu.iew.wb_rate 2.206419 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.783711 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 68328005 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 68955725 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3049164 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 257090042 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.341036 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.706336 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3049050 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 261239182 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.303854 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.691353 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 78450782 30.51% 30.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72765387 28.30% 58.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 26309862 10.23% 69.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7783958 3.03% 72.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10791645 4.20% 76.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20794996 8.09% 84.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6257040 2.43% 86.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3054798 1.19% 87.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30881574 12.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82351408 31.52% 31.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72672063 27.82% 59.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25867656 9.90% 69.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8932880 3.42% 72.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10297113 3.94% 76.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20861196 7.99% 84.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6530231 2.50% 87.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3837950 1.47% 88.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29888685 11.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 257090042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 261239182 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,358 +475,368 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 30881574 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29888685 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 896329047 # The number of ROB reads -system.cpu.rob.rob_writes 1350251983 # The number of ROB writes -system.cpu.timesIdled 964 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 53257 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 902098796 # The number of ROB reads +system.cpu.rob.rob_writes 1351611788 # The number of ROB writes +system.cpu.timesIdled 34221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 274347 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.472110 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.472110 # CPI: Total CPI of All Threads -system.cpu.ipc 2.118150 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.118150 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848643813 # number of integer regfile reads -system.cpu.int_regfile_writes 492723889 # number of integer regfile writes -system.cpu.fp_regfile_reads 378 # number of floating regfile reads +system.cpu.cpi 0.480021 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.480021 # CPI: Total CPI of All Threads +system.cpu.ipc 2.083242 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.083242 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848885274 # number of integer regfile reads +system.cpu.int_regfile_writes 492863541 # number of integer regfile writes +system.cpu.fp_regfile_reads 396 # number of floating regfile reads system.cpu.fp_regfile_writes 49 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 45 # number of replacements -system.cpu.icache.tagsinuse 826.583116 # Cycle average of tags in use -system.cpu.icache.total_refs 66484511 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67910.634321 # Average number of references to valid blocks. +system.cpu.icache.replacements 43 # number of replacements +system.cpu.icache.tagsinuse 832.109405 # Cycle average of tags in use +system.cpu.icache.total_refs 66579220 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 984 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67661.808943 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 826.583116 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.403605 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.403605 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66484511 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66484511 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66484511 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66484511 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66484511 # number of overall hits -system.cpu.icache.overall_hits::total 66484511 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1373 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1373 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1373 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1373 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1373 # number of overall misses -system.cpu.icache.overall_misses::total 1373 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50434500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50434500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50434500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50434500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50434500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50434500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66485884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66485884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66485884 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66485884 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66485884 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66485884 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36733.066278 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36733.066278 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36733.066278 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36733.066278 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36733.066278 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36733.066278 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 832.109405 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.406303 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.406303 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66579220 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66579220 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66579220 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66579220 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66579220 # number of overall hits +system.cpu.icache.overall_hits::total 66579220 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1449 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1449 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1449 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1449 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1449 # number of overall misses +system.cpu.icache.overall_misses::total 1449 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 74643000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 74643000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 74643000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 74643000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 74643000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 74643000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66580669 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66580669 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66580669 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66580669 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66580669 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66580669 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51513.457557 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51513.457557 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51513.457557 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51513.457557 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51513.457557 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51513.457557 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 293 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 73.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 394 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 394 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 394 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 394 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 394 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 394 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 979 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 979 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 979 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 979 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 979 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 979 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36994000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36994000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36994000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36994000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36994000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36994000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 465 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 465 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 465 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 465 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 465 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 984 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 984 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 984 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 984 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 984 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 984 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52158000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 52158000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52158000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 52158000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52158000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 52158000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37787.538304 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37787.538304 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37787.538304 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37787.538304 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37787.538304 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37787.538304 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53006.097561 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53006.097561 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53006.097561 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53006.097561 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53006.097561 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53006.097561 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460592 # number of replacements -system.cpu.dcache.tagsinuse 4091.681579 # Cycle average of tags in use -system.cpu.dcache.total_refs 149616636 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 464688 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 321.972239 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 272105000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4091.681579 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998946 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998946 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 111082260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 111082260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 38534319 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 38534319 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 149616579 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 149616579 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 149616579 # number of overall hits -system.cpu.dcache.overall_hits::total 149616579 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 569184 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 569184 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 917002 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 917002 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1486186 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1486186 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1486186 # number of overall misses -system.cpu.dcache.overall_misses::total 1486186 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5325915500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5325915500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10007471913 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10007471913 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15333387413 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15333387413 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15333387413 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15333387413 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 111651444 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 111651444 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 460800 # number of replacements +system.cpu.dcache.tagsinuse 4090.940281 # Cycle average of tags in use +system.cpu.dcache.total_refs 148282429 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 464896 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 318.958281 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 305241000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4090.940281 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998765 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998765 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 110633165 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 110633165 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37649215 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37649215 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 49 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 49 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 148282380 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 148282380 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 148282380 # number of overall hits +system.cpu.dcache.overall_hits::total 148282380 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1026018 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1026018 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1802106 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1802106 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2828124 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2828124 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2828124 # number of overall misses +system.cpu.dcache.overall_misses::total 2828124 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15421055000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15421055000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25889922656 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25889922656 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 28500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 28500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41310977656 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41310977656 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41310977656 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41310977656 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111659183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111659183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 151102765 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 151102765 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 151102765 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 151102765 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005098 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.005098 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.023244 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.023244 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009836 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009836 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009836 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009836 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9357.106841 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9357.106841 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10913.249822 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10913.249822 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10317.273486 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10317.273486 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10317.273486 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10317.273486 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1070 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 182 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 91 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.758242 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.750000 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151110504 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151110504 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151110504 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151110504 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009189 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009189 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045679 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045679 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057692 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057692 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018716 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018716 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018716 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018716 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.004347 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.004347 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14366.481581 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14366.481581 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14607.201684 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14607.201684 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14607.201684 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14607.201684 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 279576 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 531 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17250 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.207304 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 44.250000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 444845 # number of writebacks -system.cpu.dcache.writebacks::total 444845 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359021 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 359021 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 662477 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 662477 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1021498 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1021498 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1021498 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1021498 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210163 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210163 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254525 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254525 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 464688 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 464688 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 464688 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 464688 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 841779000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 841779000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1751356497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1751356497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2593135497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 2593135497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2593135497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 2593135497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001882 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001882 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003075 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003075 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003075 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003075 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4005.362504 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4005.362504 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 6880.882023 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 6880.882023 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 5580.379732 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 5580.379732 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 5580.379732 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 5580.379732 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 445038 # number of writebacks +system.cpu.dcache.writebacks::total 445038 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 815637 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 815637 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1547591 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1547591 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2363228 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2363228 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2363228 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2363228 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210381 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210381 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254515 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254515 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464896 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464896 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464896 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464896 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2700521500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2700521500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4051961986 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4051961986 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6752483486 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6752483486 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6752483486 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6752483486 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001884 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001884 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003077 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003077 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003077 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003077 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12836.337407 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12836.337407 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15920.326841 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15920.326841 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14524.718402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14524.718402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14524.718402 # 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Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21489.572206 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 820.765317 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 613.487588 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.655810 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.025048 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.018722 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.699580 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21483.752454 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 824.475298 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 621.403243 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.655632 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38838509 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1558816959 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1597655468 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020392 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024853 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083590 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083590 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.056942 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.978659 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.056942 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40330.746625 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 85739.226807 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77414.770988 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55980.995347 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55980.995347 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40330.746625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60974.651242 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60225.251357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40330.746625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60974.651242 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60225.251357 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index cd0e43aa8..f1f52256e 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.762398 # Number of seconds simulated -sim_ticks 762397656000 # Number of ticks simulated -final_tick 762397656000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.762403 # Number of seconds simulated +sim_ticks 762403375000 # Number of ticks simulated +final_tick 762403375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1514073 # Simulator instruction rate (inst/s) -host_op_rate 1514073 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1917939864 # Simulator tick rate (ticks/s) -host_mem_usage 219440 # Number of bytes of host memory used -host_seconds 397.51 # Real time elapsed on the host +host_inst_rate 2059312 # Simulator instruction rate (inst/s) +host_op_rate 2059312 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2608636387 # Simulator tick rate (ticks/s) +host_mem_usage 217100 # Number of bytes of host memory used +host_seconds 292.26 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1620160 # Number of bytes read from this memory -system.physmem.bytes_read::total 1670272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1628864 # Number of bytes read from this memory +system.physmem.bytes_read::total 1678976 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 56512 # Number of bytes written to this memory -system.physmem.bytes_written::total 56512 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 64384 # Number of bytes written to this memory +system.physmem.bytes_written::total 64384 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25315 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory -system.physmem.num_writes::total 883 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 25451 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26234 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1006 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1006 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 65729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2125085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2190815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2136486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2202215 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 65729 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 65729 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 74124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 74124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 74124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 84449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 84449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 84449 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 65729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2125085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2264939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2136486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2286664 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 1524795312 # number of cpu cycles simulated +system.cpu.numCycles 1524806750 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 601856964 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 153970296 # nu system.cpu.num_load_insts 114516673 # Number of load instructions system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1524795312 # Number of busy cycles +system.cpu.num_busy_cycles 1524806750 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 673.382950 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.381157 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 673.382950 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.328800 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.328800 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 673.381157 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.328799 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.328799 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 795 # n system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses system.cpu.icache.overall_misses::total 795 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 43221000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 43221000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 43221000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 43221000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 43221000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 43221000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 43222000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 43222000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 43222000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 43222000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 43222000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 43222000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54366.037736 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54366.037736 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54366.037736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54366.037736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54366.037736 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54367.295597 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54367.295597 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54367.295597 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54367.295597 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54367.295597 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54367.295597 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,32 +148,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 795 system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41632000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41632000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41632000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41632000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41632000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41632000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52367.295597 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52367.295597 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52367.295597 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52367.295597 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52367.295597 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52367.295597 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.202421 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.203488 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 563489000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.202421 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 563363000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.203488 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 455395 # n system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses system.cpu.dcache.overall_misses::total 455395 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789140000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2789140000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4194225000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4194225000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6983365000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6983365000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6983365000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6983365000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789356000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2789356000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4199727000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4199727000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6989083000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6989083000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6989083000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6989083000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13860.320426 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13860.320426 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16502.106916 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16502.106916 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15334.742367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15334.742367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15334.742367 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13861.393814 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13861.393814 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16523.754441 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16523.754441 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15347.298499 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15347.298499 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks -system.cpu.dcache.writebacks::total 436902 # number of writebacks +system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks +system.cpu.dcache.writebacks::total 436887 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386892000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386892000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3691401000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3691401000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078293000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6078293000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078293000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6078293000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11861.393814 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11861.393814 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14523.754441 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14523.754441 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 903 # number of replacements -system.cpu.l2cache.tagsinuse 22842.908958 # Cycle average of tags in use -system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1028 # number of replacements +system.cpu.l2cache.tagsinuse 22854.086849 # Cycle average of tags in use +system.cpu.l2cache.total_refs 531883 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23221 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.905258 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21649.670438 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 668.334752 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 524.903769 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.660696 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.020396 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016019 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.697110 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21662.155591 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 666.530347 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 525.400911 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.661077 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.020341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016034 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.697451 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 197110 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 197122 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232970 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232970 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 197105 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 197117 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 436887 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 436887 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 232839 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 232839 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 12 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 430080 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 430092 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 429944 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 429956 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 12 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 430080 # number of overall hits -system.cpu.l2cache.overall_hits::total 430092 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 429944 # number of overall hits +system.cpu.l2cache.overall_hits::total 429956 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 783 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4122 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4905 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21193 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21193 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 4127 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4910 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21324 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21324 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 783 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 25315 # 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number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1316380000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1357096000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 40716000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1316380000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1357096000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 25451 # number of overall misses +system.cpu.l2cache.overall_misses::total 26234 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40717000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214610000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 255327000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1108848000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1108848000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 40717000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1323458000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1364175000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 40717000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1323458000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1364175000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 795 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201232 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202027 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 436887 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 436887 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses @@ -329,27 +329,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 795 system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984906 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020484 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.024279 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083383 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.083383 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020509 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.024304 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083899 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.083899 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984906 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.055589 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.057209 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.055888 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.057507 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984906 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.055589 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.057209 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.055888 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.057507 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52001.277139 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.453841 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.425662 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52001.277139 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.235747 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.266829 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52001.277139 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.235747 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.266829 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -358,52 +358,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 883 # number of writebacks -system.cpu.l2cache.writebacks::total 883 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1006 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020484 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024279 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083383 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083383 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020509 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024304 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083899 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083899 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055589 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.057209 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055888 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057507 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055589 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.057209 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055888 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.057507 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.277139 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.453841 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.425662 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.277139 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.235747 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.266829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.277139 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.235747 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.266829 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 6dfebbc39..ec201586b 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.163308 # Number of seconds simulated -sim_ticks 163308075000 # Number of ticks simulated -final_tick 163308075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.165181 # Number of seconds simulated +sim_ticks 165180822000 # Number of ticks simulated +final_tick 165180822000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134720 # Simulator instruction rate (inst/s) -host_op_rate 142356 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38594530 # Simulator tick rate (ticks/s) -host_mem_usage 233164 # Number of bytes of host memory used -host_seconds 4231.38 # Real time elapsed on the host -sim_insts 570052710 # Number of instructions simulated -sim_ops 602360916 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1771456 # Number of bytes read from this memory -system.physmem.bytes_read::total 1819968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 204864 # Number of bytes written to this memory -system.physmem.bytes_written::total 204864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27679 # Number of read requests responded to by this memory -system.physmem.num_reads::total 28437 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 3201 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3201 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 297058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10847326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11144385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 297058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 297058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1254463 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1254463 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1254463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 297058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10847326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12398848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 28438 # Total number of read requests seen -system.physmem.writeReqs 3201 # Total number of write requests seen -system.physmem.cpureqs 31639 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1819968 # Total number of bytes read from memory -system.physmem.bytesWritten 204864 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1819968 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 204864 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 110 # Number of read reqs serviced by write Q +host_inst_rate 196230 # Simulator instruction rate (inst/s) +host_op_rate 207352 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56860513 # Simulator tick rate (ticks/s) +host_mem_usage 233444 # Number of bytes of host memory used +host_seconds 2905.02 # Real time elapsed on the host +sim_insts 570052720 # Number of instructions simulated +sim_ops 602360926 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 46976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1702592 # Number of bytes read from this memory +system.physmem.bytes_read::total 1749568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 46976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 46976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory +system.physmem.bytes_written::total 162368 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26603 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27337 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 284391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10307444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10591835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 284391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 284391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 982971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 982971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 982971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 284391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10307444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11574806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27339 # Total number of read requests seen +system.physmem.writeReqs 2537 # Total number of write requests seen +system.physmem.cpureqs 29876 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1749568 # Total number of bytes read from memory +system.physmem.bytesWritten 162368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1749568 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1839 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1814 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1805 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1796 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1898 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1731 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1725 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1752 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1846 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1720 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1705 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1738 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1679 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1720 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1741 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1670 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1719 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 1759 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1677 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 220 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 240 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 223 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 185 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 230 # Track writes on a per bank basis +system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 204 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 229 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 177 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 166 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 173 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 163308062000 # Total gap between requests +system.physmem.totGap 165180805000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 28438 # Categorize read packet sizes +system.physmem.readPktSize::6 27339 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 3201 # categorize write packet sizes +system.physmem.writePktSize::6 2537 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 743 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,60 +138,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1146806136 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1807266136 # Sum of mem lat for all requests -system.physmem.totBusLat 113312000 # Total cycles spent in databus access -system.physmem.totBankLat 547148000 # Total cycles spent in bank access -system.physmem.avgQLat 40483.13 # Average queueing delay per request -system.physmem.avgBankLat 19314.74 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 63797.87 # Average memory access latency -system.physmem.avgRdBW 11.14 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.25 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 11.14 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.25 # Average consumed write bandwidth in MB/s +system.physmem.totQLat 952476989 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1656324989 # Sum of mem lat for all requests +system.physmem.totBusLat 109352000 # Total cycles spent in databus access +system.physmem.totBankLat 594496000 # Total cycles spent in bank access +system.physmem.avgQLat 34839.50 # Average queueing delay per request +system.physmem.avgBankLat 21745.35 # Average bank access latency per request +system.physmem.avgBusLat 3999.85 # Average bus latency per request +system.physmem.avgMemAccLat 60584.70 # Average memory access latency +system.physmem.avgRdBW 10.59 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 10.59 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.98 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.08 # Data bus utilization in percentage +system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 8.45 # Average write queue length over time -system.physmem.readRowHits 18527 # Number of row buffer hits during reads -system.physmem.writeRowHits 1851 # Number of row buffer hits during writes -system.physmem.readRowHitRate 65.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.83 # Row buffer hit rate for writes -system.physmem.avgGap 5161606.31 # Average gap between requests +system.physmem.avgWrQLen 5.90 # Average write queue length over time +system.physmem.readRowHits 17775 # Number of row buffer hits during reads +system.physmem.writeRowHits 1102 # Number of row buffer hits during writes +system.physmem.readRowHitRate 65.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 43.44 # Row buffer hit rate for writes +system.physmem.avgGap 5528879.54 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,141 +235,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 326616151 # number of cpu cycles simulated +system.cpu.numCycles 330361645 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85529383 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80327419 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2411594 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47239817 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46868068 # Number of BTB hits +system.cpu.BPredUnit.lookups 85614942 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80408346 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2411110 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47313103 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46933261 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1438897 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 976 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68850265 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669456795 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85529383 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48306965 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130031029 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13412588 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 115987741 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1438558 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1082 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68875257 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669940715 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85614942 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48371819 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130120406 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13468606 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119373897 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 596 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67404301 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 787271 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 325854018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.189155 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.204154 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 577 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67426910 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 785892 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 329401870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.167030 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.195227 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 195823205 60.10% 60.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20926796 6.42% 66.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4974411 1.53% 68.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14401150 4.42% 72.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8914958 2.74% 75.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9439818 2.90% 78.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4393851 1.35% 79.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5794662 1.78% 81.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61185167 18.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 199281685 60.50% 60.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20931796 6.35% 66.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4976114 1.51% 68.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14405737 4.37% 72.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8916437 2.71% 75.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9491769 2.88% 78.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4395407 1.33% 79.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5797990 1.76% 81.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61204935 18.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 325854018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.261865 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.049674 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 92909986 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 93274931 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108737205 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19949035 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10982861 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4721514 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 329401870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.259155 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.027901 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93386530 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96217512 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108381185 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20386445 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11030198 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4725688 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 1634 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 705778363 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5683 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10982861 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107200735 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12803432 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 41316 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114329497 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80496177 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697076108 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 75 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59278982 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 18940548 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 607 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723768936 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3240980671 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3240980543 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 706212594 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6047 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11030198 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107646383 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14427218 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 44142 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114436491 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81817438 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697478243 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59322145 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20349848 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 693 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 724191424 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3242851069 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3242850941 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627419173 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96349763 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2017 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1967 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169248841 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172890049 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80617622 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21466789 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 27949042 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 681898631 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3279 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646738917 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1408601 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79369513 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197745870 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 350 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 325854018 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.984750 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.743125 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96772235 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2137 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2090 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 170767366 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172981751 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80655031 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21643688 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28602277 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 682247714 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3351 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646916263 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1413678 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79713119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 198676272 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 420 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 329401870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.963912 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.726446 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 67303060 20.65% 20.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 84497277 25.93% 46.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 74959252 23.00% 69.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40290304 12.36% 81.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28820123 8.84% 90.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15118844 4.64% 95.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5732215 1.76% 97.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6879322 2.11% 99.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2253621 0.69% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68982651 20.94% 20.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85413517 25.93% 46.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75907397 23.04% 69.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40996794 12.45% 82.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28857883 8.76% 91.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14995240 4.55% 95.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5624116 1.71% 97.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6449034 1.96% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2175238 0.66% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 325854018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 329401870 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 205105 5.40% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2822579 74.31% 79.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 770924 20.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 209715 5.57% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2699537 71.67% 77.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 857291 22.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403867506 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6566 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403968416 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6570 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -397,468 +397,468 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166069409 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76795433 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166149452 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76791822 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646738917 # Type of FU issued -system.cpu.iq.rate 1.980119 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3798608 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005873 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624539025 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761282766 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638466372 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646916263 # Type of FU issued +system.cpu.iq.rate 1.958206 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3766543 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005822 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1628414581 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761976266 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638610282 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650537505 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650682786 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30381283 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30415737 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23937231 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 124667 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11589 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10396384 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 24028931 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 122816 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12363 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10433791 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12749 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 16530 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12786 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 32242 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10982861 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 283658 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 42314 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 681905072 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 702708 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172890049 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80617622 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1929 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10939 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4841 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11589 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1389637 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1521620 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2911257 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642548978 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163933240 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4189939 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11030198 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 797335 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 96405 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 682254196 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 711562 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172981751 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80655031 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2002 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 33535 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 20290 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12363 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1389918 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1519621 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2909539 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642699172 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163997886 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4217091 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3162 # number of nop insts executed -system.cpu.iew.exec_refs 239931847 # number of memory reference insts executed -system.cpu.iew.exec_branches 74717690 # Number of branches executed -system.cpu.iew.exec_stores 75998607 # Number of stores executed -system.cpu.iew.exec_rate 1.967291 # Inst execution rate -system.cpu.iew.wb_sent 639936452 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638466388 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420738662 # num instructions producing a value -system.cpu.iew.wb_consumers 656063471 # num instructions consuming a value +system.cpu.iew.exec_nop 3131 # number of nop insts executed +system.cpu.iew.exec_refs 239992833 # number of memory reference insts executed +system.cpu.iew.exec_branches 74738268 # Number of branches executed +system.cpu.iew.exec_stores 75994947 # Number of stores executed +system.cpu.iew.exec_rate 1.945441 # Inst execution rate +system.cpu.iew.wb_sent 640075541 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638610298 # cumulative count of insts written-back +system.cpu.iew.wb_producers 419218635 # num instructions producing a value +system.cpu.iew.wb_consumers 650818648 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.954791 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.641308 # average fanout of values written-back +system.cpu.iew.wb_rate 1.933064 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644140 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 79553511 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2929 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2410069 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 314871158 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.913040 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.240132 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 79903729 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2409576 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 318371673 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.892006 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.234894 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91119458 28.94% 28.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103740730 32.95% 61.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42921464 13.63% 75.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8973909 2.85% 78.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25553482 8.12% 86.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13492783 4.29% 90.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7636973 2.43% 93.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1102971 0.35% 93.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20329388 6.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93985379 29.52% 29.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104446341 32.81% 62.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43081844 13.53% 75.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8825548 2.77% 78.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25971107 8.16% 86.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12926353 4.06% 90.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7575563 2.38% 93.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1171571 0.37% 93.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20387967 6.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 314871158 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570052761 # Number of instructions committed -system.cpu.commit.committedOps 602360967 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 318371673 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570052771 # Number of instructions committed +system.cpu.commit.committedOps 602360977 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219174056 # Number of memory references committed -system.cpu.commit.loads 148952818 # Number of loads committed +system.cpu.commit.refs 219174060 # Number of memory references committed +system.cpu.commit.loads 148952820 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70892749 # Number of branches committed +system.cpu.commit.branches 70892751 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533523531 # Number of committed integer instructions. +system.cpu.commit.int_insts 533523539 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20329388 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20387967 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 976455636 # The number of ROB reads -system.cpu.rob.rob_writes 1374843243 # The number of ROB writes -system.cpu.timesIdled 13781 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 762133 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570052710 # Number of Instructions Simulated -system.cpu.committedOps 602360916 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570052710 # Number of Instructions Simulated -system.cpu.cpi 0.572958 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.572958 # CPI: Total CPI of All Threads -system.cpu.ipc 1.745329 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.745329 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3209817028 # number of integer regfile reads -system.cpu.int_regfile_writes 664078534 # number of integer regfile writes +system.cpu.rob.rob_reads 980247800 # The number of ROB reads +system.cpu.rob.rob_writes 1375591081 # The number of ROB writes +system.cpu.timesIdled 40973 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 959775 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570052720 # Number of Instructions Simulated +system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated +system.cpu.cpi 0.579528 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.579528 # CPI: Total CPI of All Threads +system.cpu.ipc 1.725541 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.725541 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210576810 # number of integer regfile reads +system.cpu.int_regfile_writes 664235164 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 904771120 # number of misc regfile reads -system.cpu.misc_regfile_writes 3106 # number of misc regfile writes -system.cpu.icache.replacements 68 # number of replacements -system.cpu.icache.tagsinuse 692.511005 # Cycle average of tags in use -system.cpu.icache.total_refs 67403190 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 831 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 81110.938628 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 905305467 # number of misc regfile reads +system.cpu.misc_regfile_writes 3110 # number of misc regfile writes +system.cpu.icache.replacements 62 # number of replacements +system.cpu.icache.tagsinuse 692.874511 # Cycle average of tags in use +system.cpu.icache.total_refs 67425756 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 825 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 81728.189091 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 692.511005 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.338140 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.338140 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67403190 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67403190 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67403190 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67403190 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67403190 # number of overall hits -system.cpu.icache.overall_hits::total 67403190 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1111 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1111 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1111 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1111 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1111 # number of overall misses -system.cpu.icache.overall_misses::total 1111 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39508000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39508000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39508000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39508000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39508000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39508000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67404301 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67404301 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67404301 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67404301 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67404301 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67404301 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35560.756076 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35560.756076 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35560.756076 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35560.756076 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35560.756076 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35560.756076 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 692.874511 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.338318 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.338318 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67425756 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67425756 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67425756 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67425756 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67425756 # number of overall hits +system.cpu.icache.overall_hits::total 67425756 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses +system.cpu.icache.overall_misses::total 1154 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44126.949740 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44126.949740 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 247 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10174.921337 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10174.921337 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9863.636364 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9863.636364 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10222.756075 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10222.756075 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10222.756075 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10222.756075 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 57181 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3033 # 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average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15068.031490 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12011.493011 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12011.493011 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17630.434783 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17630.434783 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12295.132513 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12295.132513 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12295.132513 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12295.132513 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 131789 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4871 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.055841 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421155 # number of writebacks -system.cpu.dcache.writebacks::total 421155 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 18984 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 18984 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1043965 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1043965 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # 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number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444660 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1126335500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1126335500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1838542063 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1838542063 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2964877563 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 2964877563 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2964877563 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 2964877563 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001493 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001493 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 421553 # number of writebacks +system.cpu.dcache.writebacks::total 421553 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144386 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 144386 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3094637 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3094637 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 23 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 23 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3239023 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3239023 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3239023 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3239023 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197441 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197441 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247111 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247111 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444552 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444552 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444552 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444552 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2877099000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2877099000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4061335300 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4061335300 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6938434300 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6938434300 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6938434300 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6938434300 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001492 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001492 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002204 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 6667.740663 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14571.943011 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14571.943011 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16435.267147 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16435.267147 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15607.700112 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15607.700112 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15607.700112 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15607.700112 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # 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miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.059869 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.061413 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49812.075984 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 151157.752902 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 137726.398130 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70835.092469 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70835.092469 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49812.075984 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85393.668984 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84434.922492 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49812.075984 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85393.668984 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84434.922492 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 2973 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 9.459469 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 3201 # number of writebacks -system.cpu.l2cache.writebacks::total 3201 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 2537 # number of writebacks +system.cpu.l2cache.writebacks::total 2537 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 758 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 5500 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 6258 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22180 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 22180 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 758 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 27680 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 28438 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 758 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 27680 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 28438 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25719146 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 701873552 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 727592698 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1275833198 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1275833198 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25719146 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1977706750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2003425896 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25719146 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1977706750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2003425896 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027844 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031549 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089750 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089750 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062250 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063835 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.912154 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062250 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063835 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33930.271768 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 127613.373091 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 116266.011186 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57521.785302 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57521.785302 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33930.271768 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71448.943280 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70448.902736 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33930.271768 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71448.943280 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70448.902736 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4814 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5548 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21791 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21791 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26605 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27339 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26605 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27339 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27102664 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668415074 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695517738 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1272078673 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1272078673 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27102664 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1940493747 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1967596411 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27102664 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1940493747 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1967596411 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.888620 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024382 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027983 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088182 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088182 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.888620 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059847 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061384 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.888620 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059847 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061384 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36924.610354 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 138848.166597 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125363.687455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58376.333027 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58376.333027 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36924.610354 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72937.182748 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71970.313874 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36924.610354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72937.182748 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71970.313874 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index e1fc6c299..3042021d4 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.793710 # Number of seconds simulated -sim_ticks 793709507000 # Number of ticks simulated -final_tick 793709507000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.793670 # Number of seconds simulated +sim_ticks 793670137000 # Number of ticks simulated +final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1083083 # Simulator instruction rate (inst/s) -host_op_rate 1143775 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1512037928 # Simulator tick rate (ticks/s) -host_mem_usage 233820 # Number of bytes of host memory used -host_seconds 524.93 # Real time elapsed on the host +host_inst_rate 897110 # Simulator instruction rate (inst/s) +host_op_rate 947381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1252348386 # Simulator tick rate (ticks/s) +host_mem_usage 231392 # Number of bytes of host memory used +host_seconds 633.75 # Real time elapsed on the host sim_insts 568539335 # Number of instructions simulated sim_ops 600398272 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1735040 # Number of bytes read from this memory -system.physmem.bytes_read::total 1774144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 39104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 39104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 194752 # Number of bytes written to this memory -system.physmem.bytes_written::total 194752 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 611 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27110 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27721 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 3043 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3043 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 49267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2185989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2235256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 49267 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 49267 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 245369 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 245369 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 245369 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 49267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2185989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2480625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1675072 # Number of bytes read from this memory +system.physmem.bytes_read::total 1713664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 38592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 38592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 159552 # Number of bytes written to this memory +system.physmem.bytes_written::total 159552 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 603 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26173 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26776 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2493 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2493 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 48625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2110539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2159164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 48625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 48625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 201031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 201031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 201031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 48625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2110539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2360195 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1587419014 # number of cpu cycles simulated +system.cpu.numCycles 1587340274 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 568539335 # Number of instructions committed @@ -96,16 +96,16 @@ system.cpu.num_mem_refs 219173606 # nu system.cpu.num_load_insts 148952593 # Number of load instructions system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1587419014 # Number of busy cycles +system.cpu.num_busy_cycles 1587340274 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 12 # number of replacements -system.cpu.icache.tagsinuse 577.773227 # Cycle average of tags in use +system.cpu.icache.tagsinuse 577.773656 # Cycle average of tags in use system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 577.773227 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 577.773656 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.282116 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.282116 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 643 # n system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses system.cpu.icache.overall_misses::total 643 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34021000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34021000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34021000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34021000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34021000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34021000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33685000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33685000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33685000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33685000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33685000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33685000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52909.797823 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52909.797823 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52909.797823 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52909.797823 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52909.797823 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52909.797823 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52387.247278 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52387.247278 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52387.247278 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52387.247278 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52387.247278 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52387.247278 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,32 +158,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 643 system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32735000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32735000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32735000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32735000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32735000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32735000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32399000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32399000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32399000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32399000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32399000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32399000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50909.797823 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50909.797823 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50387.247278 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50387.247278 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 433468 # number of replacements -system.cpu.dcache.tagsinuse 4094.242161 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.241219 # Cycle average of tags in use system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 529482000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.242161 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 529622000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.241219 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 437564 # n system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses system.cpu.dcache.overall_misses::total 437564 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2675478000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2675478000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4151654000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4151654000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6827132000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6827132000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6827132000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6827132000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2650304000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2650304000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4137794000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4137794000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6788098000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6788098000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6788098000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6788098000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14095.113162 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14095.113162 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16757.568174 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16757.568174 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15602.590707 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15602.590707 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15602.590707 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15602.590707 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13962.489990 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13962.489990 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16701.624231 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16701.624231 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15513.383185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15513.383185 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 418219 # number of writebacks -system.cpu.dcache.writebacks::total 418219 # number of writebacks +system.cpu.dcache.writebacks::writebacks 418626 # number of writebacks +system.cpu.dcache.writebacks::total 418626 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 437564 system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2295846000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2295846000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3656158000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3656158000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5952004000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5952004000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5952004000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5952004000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2270672000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2270672000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3642298000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3642298000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5912970000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5912970000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5912970000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5912970000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12095.113162 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12095.113162 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14757.568174 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14757.568174 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13602.590707 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13602.590707 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13602.590707 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13602.590707 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11962.489990 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11962.489990 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14701.624231 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14701.624231 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 3963 # number of replacements -system.cpu.l2cache.tagsinuse 21582.814171 # Cycle average of tags in use -system.cpu.l2cache.total_refs 495400 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24559 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 20.171831 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2512 # number of replacements +system.cpu.l2cache.tagsinuse 22024.775302 # Cycle average of tags in use +system.cpu.l2cache.total_refs 506990 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23599 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.483537 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20943.692003 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 130.073000 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 509.049168 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.639151 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.015535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.658655 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 184871 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 184903 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 418219 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 418219 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 225583 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 225583 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 410454 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 410486 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 410454 # number of overall hits -system.cpu.l2cache.overall_hits::total 410486 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 611 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4945 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5556 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 22165 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 22165 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 611 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 27110 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27721 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 611 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 27110 # number of overall misses -system.cpu.l2cache.overall_misses::total 27721 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31772000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 257320000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 289092000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1152580000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1152580000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 31772000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1409900000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1441672000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 31772000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1409900000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1441672000 # number of overall miss cycles +system.cpu.l2cache.occ_blocks::writebacks 20978.651717 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 539.196236 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 506.927350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.640218 # 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number of overall misses +system.cpu.l2cache.overall_misses::total 26776 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31356000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 226076000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 257432000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1135420000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1135420000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 31356000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1361496000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1392852000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 31356000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1361496000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1392852000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 418219 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 418219 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 418626 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 418626 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses @@ -346,28 +346,28 @@ system.cpu.l2cache.demand_accesses::total 438207 # n system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.950233 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026052 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.029172 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089466 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.089466 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.950233 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.061957 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063260 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.950233 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.061957 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063260 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.937792 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022854 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.025943 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088134 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.088134 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.937792 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.059815 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.061104 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.937792 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.059815 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.061104 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.400404 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52032.397408 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52115.260489 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52101.194090 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52006.639616 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52006.493272 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52019.103656 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52018.673439 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52006.639616 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52006.493272 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52019.103656 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52018.673439 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -376,52 +376,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 3043 # number of writebacks -system.cpu.l2cache.writebacks::total 3043 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 611 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4945 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5556 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22165 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 22165 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 611 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 27110 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27721 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 611 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 27110 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27721 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 197980000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222420000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 886600000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 886600000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1084580000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1109020000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1084580000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1109020000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026052 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.029172 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089466 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089466 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063260 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063260 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 2493 # number of writebacks +system.cpu.l2cache.writebacks::total 2493 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 603 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4338 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4941 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21835 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21835 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 603 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 26776 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 603 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26173 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 26776 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 174020000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198140000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 873400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 873400000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1047420000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1071540000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1047420000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1071540000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022854 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025943 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088134 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088134 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059815 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061104 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.937792 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059815 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061104 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40036.400404 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40032.397408 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40115.260489 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40101.194090 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40006.639616 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40006.493272 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40006.639616 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40006.493272 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 532c2f1d1..ef06efc76 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387215 # Number of seconds simulated -sim_ticks 387214915500 # Number of ticks simulated -final_tick 387214915500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.389228 # Number of seconds simulated +sim_ticks 389227542000 # Number of ticks simulated +final_tick 389227542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118034 # Simulator instruction rate (inst/s) -host_op_rate 118406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32618299 # Simulator tick rate (ticks/s) -host_mem_usage 226848 # Number of bytes of host memory used -host_seconds 11871.09 # Real time elapsed on the host +host_inst_rate 219415 # Simulator instruction rate (inst/s) +host_op_rate 220107 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60950012 # Simulator tick rate (ticks/s) +host_mem_usage 227096 # Number of bytes of host memory used +host_seconds 6386.01 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 78656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678976 # Number of bytes read from this memory -system.physmem.bytes_read::total 1757632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 78656 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 78656 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 163392 # Number of bytes written to this memory -system.physmem.bytes_written::total 163392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26234 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27463 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2553 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2553 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 203133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4336031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4539164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 203133 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 203133 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 421967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 421967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 421967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 203133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4336031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4961131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27464 # Total number of read requests seen -system.physmem.writeReqs 2553 # Total number of write requests seen -system.physmem.cpureqs 30017 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1757632 # Total number of bytes read from memory -system.physmem.bytesWritten 163392 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1757632 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 163392 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 4 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 76992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678464 # Number of bytes read from this memory +system.physmem.bytes_read::total 1755456 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory +system.physmem.bytes_written::total 162112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1203 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26226 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27429 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 197807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4312295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4510102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 416497 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 416497 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 416497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4312295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4926599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27430 # Total number of read requests seen +system.physmem.writeReqs 2533 # Total number of write requests seen +system.physmem.cpureqs 29963 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1755456 # Total number of bytes read from memory +system.physmem.bytesWritten 162112 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1755456 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1716 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1734 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1804 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1715 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1733 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1803 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1696 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1697 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1679 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1746 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1678 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1745 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1758 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1754 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1713 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1623 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 172 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 166 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 161 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 160 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387214887500 # Total gap between requests +system.physmem.totGap 389227514000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27464 # Categorize read packet sizes +system.physmem.readPktSize::6 27430 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2553 # categorize write packet sizes +system.physmem.writePktSize::6 2533 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 6398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12553 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 8259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,32 +138,32 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see @@ -171,161 +171,162 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 916617704 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1530569704 # Sum of mem lat for all requests -system.physmem.totBusLat 109840000 # Total cycles spent in databus access -system.physmem.totBankLat 504112000 # Total cycles spent in bank access -system.physmem.avgQLat 33380.11 # Average queueing delay per request -system.physmem.avgBankLat 18358.05 # Average bank access latency per request +system.physmem.totQLat 723930803 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1405746803 # Sum of mem lat for all requests +system.physmem.totBusLat 109720000 # Total cycles spent in databus access +system.physmem.totBankLat 572096000 # Total cycles spent in bank access +system.physmem.avgQLat 26391.94 # Average queueing delay per request +system.physmem.avgBankLat 20856.58 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 55738.15 # Average memory access latency -system.physmem.avgRdBW 4.54 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 51248.52 # Average memory access latency +system.physmem.avgRdBW 4.51 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 4.54 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 4.51 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.42 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 12.78 # Average write queue length over time -system.physmem.readRowHits 18350 # Number of row buffer hits during reads -system.physmem.writeRowHits 1423 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 55.74 # Row buffer hit rate for writes -system.physmem.avgGap 12899853.00 # Average gap between requests +system.physmem.avgWrQLen 17.21 # Average write queue length over time +system.physmem.readRowHits 18327 # Number of row buffer hits during reads +system.physmem.writeRowHits 1092 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 43.11 # Row buffer hit rate for writes +system.physmem.avgGap 12990271.80 # Average gap between requests system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774429832 # number of cpu cycles simulated +system.cpu.numCycles 778455085 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98185573 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88408048 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3782090 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 66047653 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65662573 # Number of BTB hits +system.cpu.BPredUnit.lookups 98229199 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88445613 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3785118 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 66042302 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65687206 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1362 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 165872466 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648691883 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98185573 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65663935 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330391084 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21655373 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 260441698 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2775 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 162813824 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 754521 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774378524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.134915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.150373 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1416 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 222 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 165941423 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1649243289 # Number of instructions fetch has processed +system.cpu.fetch.Branches 98229199 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65688622 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330524246 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21752869 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 264030512 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 127 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 3232 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 162872893 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 756309 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 778243541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.125156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146469 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 443987440 57.33% 57.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74371964 9.60% 66.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37979457 4.90% 71.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9083058 1.17% 73.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28156651 3.64% 76.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18823006 2.43% 79.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11516280 1.49% 80.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3872547 0.50% 81.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146588121 18.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 447719295 57.53% 57.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74411347 9.56% 67.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37980792 4.88% 71.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9095898 1.17% 73.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28164996 3.62% 76.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18829907 2.42% 79.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11517848 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3875799 0.50% 81.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146647659 18.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774378524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126784 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.128911 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 216878479 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 211680769 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285325834 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42823062 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17670380 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1642440106 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17670380 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 240852826 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34201656 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 51873963 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 303043152 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126736547 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1631096404 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 30920192 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73688032 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3125584 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1360785655 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2755532793 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2721694232 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33838561 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 778243541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126185 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.118611 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 217164629 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 215069073 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285415505 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42850333 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 17744001 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1642995255 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 17744001 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 241214952 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36881220 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52262769 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303103685 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 127036914 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1631617640 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 159 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30927214 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 74044181 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3148431 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1361239803 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2756565281 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2722455578 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34109703 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 116015216 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2681563 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2696177 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 272664149 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 438656145 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 180228164 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 255185830 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83164069 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1516867754 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2636658 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1460784709 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 45870 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 113563441 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 136393501 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 392987 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774378524 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.886396 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.429689 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 116469364 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2680762 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2695576 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 273321719 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 438834936 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 180276836 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 255914047 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 82184887 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1517277053 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2635551 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1461048176 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 49743 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 113961410 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 136888972 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 391880 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 778243541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.877366 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.430181 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 144522601 18.66% 18.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 185174960 23.91% 42.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210422651 27.17% 69.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131027562 16.92% 86.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70858421 9.15% 95.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20344015 2.63% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7836220 1.01% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4026070 0.52% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 166024 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 147640445 18.97% 18.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 185782276 23.87% 42.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210767336 27.08% 69.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131005887 16.83% 86.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70732163 9.09% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20418483 2.62% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7758324 1.00% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3966460 0.51% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 172167 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774378524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 778243541 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112088 6.69% 6.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 98938 5.90% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1079860 64.44% 77.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 384872 22.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 96825 5.83% 5.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95727 5.76% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1146892 69.00% 80.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 322714 19.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 867100758 59.36% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 867232738 59.36% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2647457 0.18% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2645576 0.18% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued @@ -351,84 +352,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419766221 28.74% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171270273 11.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419895345 28.74% 88.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171274517 11.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1460784709 # Type of FU issued -system.cpu.iq.rate 1.886271 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1675758 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001147 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3679920663 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1624205262 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1444366362 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17748907 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9099237 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8557399 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453373806 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9086661 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215387676 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1461048176 # Type of FU issued +system.cpu.iq.rate 1.876856 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1662158 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001138 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3684211603 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1624908064 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1444562282 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17840191 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9203552 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8548837 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1453579294 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9131040 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215356561 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36143302 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 55137 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 245231 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 13380022 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36322093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 55076 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 245947 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 13428694 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3602 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3648 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 92141 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17670380 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1032740 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 13152 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1613687741 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4121479 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 438656145 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 180228164 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2550792 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8203 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 245231 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2357183 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1559022 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3916205 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1455236393 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 417044165 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5548316 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 17744001 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3080372 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 245510 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1614123458 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4140274 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 438834936 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 180276836 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2549819 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 147701 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1738 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 245947 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2356068 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1563417 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3919485 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1455490088 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 417172237 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5558088 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 94183329 # number of nop insts executed -system.cpu.iew.exec_refs 587622922 # number of memory reference insts executed -system.cpu.iew.exec_branches 89108958 # Number of branches executed -system.cpu.iew.exec_stores 170578757 # Number of stores executed -system.cpu.iew.exec_rate 1.879107 # Inst execution rate -system.cpu.iew.wb_sent 1453841644 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1452923761 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154329978 # num instructions producing a value -system.cpu.iew.wb_consumers 1205560357 # num instructions consuming a value +system.cpu.iew.exec_nop 94210854 # number of nop insts executed +system.cpu.iew.exec_refs 587755640 # number of memory reference insts executed +system.cpu.iew.exec_branches 89119477 # Number of branches executed +system.cpu.iew.exec_stores 170583403 # Number of stores executed +system.cpu.iew.exec_rate 1.869716 # Inst execution rate +system.cpu.iew.wb_sent 1454027442 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1453111119 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1154511485 # num instructions producing a value +system.cpu.iew.wb_consumers 1205709259 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.876121 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957505 # average fanout of values written-back +system.cpu.iew.wb_rate 1.866660 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957537 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 124055997 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 124505734 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3782090 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 756708755 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.968423 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.506505 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3785118 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 760500151 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.958610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.504084 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 238213555 31.48% 31.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276540536 36.55% 68.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43021375 5.69% 73.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54822808 7.24% 80.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19645378 2.60% 83.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13385764 1.77% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30553973 4.04% 89.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10565526 1.40% 90.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69959840 9.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 241986025 31.82% 31.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276568961 36.37% 68.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42982436 5.65% 73.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54874417 7.22% 81.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19672131 2.59% 83.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13330795 1.75% 85.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30549094 4.02% 89.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10561201 1.39% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69975091 9.20% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 756708755 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 760500151 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -439,374 +440,374 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69959840 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69975091 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2300263324 # The number of ROB reads -system.cpu.rob.rob_writes 3244852707 # The number of ROB writes -system.cpu.timesIdled 1017 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 51308 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2304489206 # The number of ROB reads +system.cpu.rob.rob_writes 3245826636 # The number of ROB writes +system.cpu.timesIdled 25902 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 211544 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552695 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552695 # CPI: Total CPI of All Threads -system.cpu.ipc 1.809317 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.809317 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1980527314 # number of integer regfile reads -system.cpu.int_regfile_writes 1276211568 # number of integer regfile writes -system.cpu.fp_regfile_reads 16969770 # number of floating regfile reads -system.cpu.fp_regfile_writes 10498210 # number of floating regfile writes -system.cpu.misc_regfile_reads 593297660 # number of misc regfile reads +system.cpu.cpi 0.555568 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.555568 # CPI: Total CPI of All Threads +system.cpu.ipc 1.799961 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.799961 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1980833855 # number of integer regfile reads +system.cpu.int_regfile_writes 1276392600 # number of integer regfile writes +system.cpu.fp_regfile_reads 16967472 # number of floating regfile reads +system.cpu.fp_regfile_writes 10493116 # number of floating regfile writes +system.cpu.misc_regfile_reads 593429000 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 217 # number of replacements -system.cpu.icache.tagsinuse 1045.896866 # Cycle average of tags in use -system.cpu.icache.total_refs 162811965 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1366 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 119188.846999 # Average number of references to valid blocks. +system.cpu.icache.replacements 221 # number of replacements +system.cpu.icache.tagsinuse 1044.865694 # Cycle average of tags in use +system.cpu.icache.total_refs 162870916 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1368 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 119057.687135 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1045.896866 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.510692 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.510692 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 162811965 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 162811965 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 162811965 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 162811965 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 162811965 # number of overall hits -system.cpu.icache.overall_hits::total 162811965 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1859 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1859 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1859 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1859 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1859 # number of overall misses -system.cpu.icache.overall_misses::total 1859 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 53339000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 53339000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 53339000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 53339000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 53339000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 53339000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162813824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162813824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162813824 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162813824 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162813824 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162813824 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000011 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000011 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000011 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000011 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000011 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000011 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28692.307692 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28692.307692 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28692.307692 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28692.307692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28692.307692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28692.307692 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1044.865694 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.510188 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.510188 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 162870916 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 162870916 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 162870916 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 162870916 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 162870916 # number of overall hits +system.cpu.icache.overall_hits::total 162870916 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1977 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1977 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1977 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1977 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1977 # number of overall misses +system.cpu.icache.overall_misses::total 1977 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 82311500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 82311500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 82311500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 82311500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 82311500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 82311500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162872893 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162872893 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162872893 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162872893 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162872893 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162872893 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41634.547294 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41634.547294 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41634.547294 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41634.547294 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41634.547294 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41634.547294 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 492 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 492 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 492 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 492 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 492 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 492 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1367 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1367 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1367 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1367 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1367 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1367 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 40091000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 40091000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 40091000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 40091000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 40091000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 40091000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 608 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 608 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 608 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 608 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 608 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 608 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1369 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1369 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1369 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1369 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1369 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1369 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60349500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 60349500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60349500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 60349500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60349500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 60349500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29327.724945 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29327.724945 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29327.724945 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29327.724945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29327.724945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29327.724945 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44082.907232 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44082.907232 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44082.907232 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 44082.907232 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44082.907232 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 44082.907232 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 458245 # number of replacements -system.cpu.dcache.tagsinuse 4094.164833 # Cycle average of tags in use -system.cpu.dcache.total_refs 365848378 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 462341 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 791.295555 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 304049000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.164833 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999552 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999552 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200718396 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200718396 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 165128663 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 165128663 # number of WriteReq hits +system.cpu.dcache.replacements 458014 # number of replacements +system.cpu.dcache.tagsinuse 4093.836666 # Cycle average of tags in use +system.cpu.dcache.total_refs 365740775 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 462110 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 791.458257 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 344026000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.836666 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999472 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999472 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 200780850 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200780850 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164958606 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164958606 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # 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number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 929575 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 929575 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1888210 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1888210 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2611785 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2611785 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2611785 # number of overall misses -system.cpu.dcache.overall_misses::total 2611785 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6936484000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6936484000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15815722499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15815722499 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 50000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 50000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22752206499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22752206499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22752206499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22752206499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201612028 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201612028 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2817785 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2817785 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2817785 # number of overall misses +system.cpu.dcache.overall_misses::total 2817785 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14994299000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14994299000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31871156950 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31871156950 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 122000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 122000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46865455950 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46865455950 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46865455950 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46865455950 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201710425 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201710425 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 368458844 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 368458844 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 368458844 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 368458844 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004432 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004432 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010298 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010298 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368557241 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368557241 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368557241 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368557241 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004608 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004608 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011317 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011317 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007088 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007088 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007088 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007088 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7762.125797 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 7762.125797 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9205.072249 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9205.072249 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 7142.857143 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 7142.857143 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8711.362727 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8711.362727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8711.362727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8711.362727 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.007645 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007645 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007645 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007645 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16130.273512 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16130.273512 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16879.031967 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16879.031967 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 17428.571429 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 17428.571429 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16632.019813 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16632.019813 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16632.019813 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16632.019813 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 577430 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 18 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35655 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.194924 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443162 # number of writebacks -system.cpu.dcache.writebacks::total 443162 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 693399 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 693399 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1456052 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1456052 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2149451 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2149451 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2149451 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2149451 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200233 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200233 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262101 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262101 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 442964 # number of writebacks +system.cpu.dcache.writebacks::total 442964 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 729519 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 729519 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1626163 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1626163 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2355682 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2355682 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2355682 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2355682 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200056 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200056 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262047 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262047 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 462334 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 462334 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 462334 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 462334 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 847043500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 847043500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1875854500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1875854500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 36000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 36000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2722898000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 2722898000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2722898000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 2722898000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000993 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 462103 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 462103 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 462103 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 462103 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2627957000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2627957000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4314187000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4314187000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 108000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 108000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942144000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6942144000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942144000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6942144000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001571 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001255 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001255 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001255 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001255 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4230.289213 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4230.289213 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7156.991007 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7156.991007 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 5142.857143 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 5142.857143 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 5889.460866 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 5889.460866 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 5889.460866 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 5889.460866 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001254 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13136.106890 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13136.106890 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16463.409236 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16463.409236 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 15428.571429 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 15428.571429 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15022.936445 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15022.936445 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15022.936445 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15022.936445 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2679 # number of replacements -system.cpu.l2cache.tagsinuse 22378.512464 # Cycle average of tags in use -system.cpu.l2cache.total_refs 542084 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24310 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.298807 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2556 # number of replacements +system.cpu.l2cache.tagsinuse 22458.024259 # Cycle average of tags in use +system.cpu.l2cache.total_refs 548899 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24278 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.608905 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20735.512523 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 999.090351 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 643.909590 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.632798 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.030490 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019651 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.682938 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 137 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 195795 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 195932 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 443162 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 443162 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 240312 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 240312 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 137 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 436107 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 436244 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 137 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 436107 # number of overall hits -system.cpu.l2cache.overall_hits::total 436244 # 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mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059183 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35016.580565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 93514.280840 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 81004.293073 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58523.308945 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58523.308945 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35016.580565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64428.519103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63137.524790 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35016.580565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64428.519103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63137.524790 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index c111732e8..d4dde6ec1 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.061067 # Number of seconds simulated -sim_ticks 2061066683000 # Number of ticks simulated -final_tick 2061066683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.061066 # Number of seconds simulated +sim_ticks 2061066313000 # Number of ticks simulated +final_tick 2061066313000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1352034 # Simulator instruction rate (inst/s) -host_op_rate 1356054 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1876383782 # Simulator tick rate (ticks/s) -host_mem_usage 222536 # Number of bytes of host memory used -host_seconds 1098.43 # Real time elapsed on the host +host_inst_rate 632829 # Simulator instruction rate (inst/s) +host_op_rate 634711 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 878254717 # Simulator tick rate (ticks/s) +host_mem_usage 225052 # Number of bytes of host memory used +host_seconds 2346.78 # Real time elapsed on the host sim_insts 1485108088 # Number of instructions simulated sim_ops 1489523282 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1672576 # Number of bytes read from this memory -system.physmem.bytes_read::total 1738304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 161472 # Number of bytes written to this memory -system.physmem.bytes_written::total 161472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1027 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26134 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27161 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2523 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2523 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 31890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 811510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 843400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 31890 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 31890 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 78344 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 78344 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 78344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 31890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 811510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 921744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1672512 # Number of bytes read from this memory +system.physmem.bytes_read::total 1737728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 161152 # Number of bytes written to this memory +system.physmem.bytes_written::total 161152 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26133 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27152 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2518 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2518 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 31642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 811479 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 843121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 31642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 31642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 78189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 78189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 78189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 31642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 811479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 921310 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 4122133366 # number of cpu cycles simulated +system.cpu.numCycles 4122132626 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1485108088 # Number of instructions committed @@ -54,16 +54,16 @@ system.cpu.num_mem_refs 569365766 # nu system.cpu.num_load_insts 402515345 # Number of load instructions system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4122133366 # Number of busy cycles +system.cpu.num_busy_cycles 4122132626 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 118 # number of replacements -system.cpu.icache.tagsinuse 906.468708 # Cycle average of tags in use +system.cpu.icache.tagsinuse 906.468716 # Cycle average of tags in use system.cpu.icache.total_refs 1485111892 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1341564.491418 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 906.468708 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 906.468716 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.442612 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.442612 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1485111892 # number of ReadReq hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 1107 # n system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses system.cpu.icache.overall_misses::total 1107 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 57527000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 57527000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 57527000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 57527000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 57527000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 57527000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 57199000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 57199000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 57199000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 57199000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 57199000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 57199000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1485112999 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1485112999 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1485112999 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51966.576332 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51966.576332 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51966.576332 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51966.576332 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51966.576332 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51966.576332 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51670.280036 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51670.280036 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51670.280036 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51670.280036 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51670.280036 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51670.280036 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,32 +116,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1107 system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55313000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 55313000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55313000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 55313000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55313000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 55313000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54985000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 54985000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54985000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 54985000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54985000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 54985000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49966.576332 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49966.576332 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49966.576332 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49966.576332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49966.576332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49966.576332 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49670.280036 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49670.280036 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements -system.cpu.dcache.tagsinuse 4095.236029 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.236014 # Cycle average of tags in use system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 559332000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.236029 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 559340000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.236014 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999813 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits @@ -166,14 +166,14 @@ system.cpu.dcache.overall_misses::cpu.data 453214 # system.cpu.dcache.overall_misses::total 453214 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 2694826000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 2694826000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294542000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4294542000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294500000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4294500000 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 133000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 133000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6989368000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6989368000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6989368000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6989368000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6989326000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6989326000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6989326000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6989326000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) @@ -196,14 +196,14 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13927.757047 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.767141 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.767141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.605433 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.605433 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 19000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.783087 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15421.783087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.783087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15421.783087 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15421.690416 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15421.690416 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -226,14 +226,14 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 453214 system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775086000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775086000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775044000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775044000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082940000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6082940000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082940000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6082940000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082898000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6082898000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082898000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6082898000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses @@ -246,63 +246,63 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.767141 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.767141 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.605433 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.605433 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2614 # number of replacements -system.cpu.l2cache.tagsinuse 22187.209427 # Cycle average of tags in use -system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2539 # number of replacements +system.cpu.l2cache.tagsinuse 22253.549915 # Cycle average of tags in use +system.cpu.l2cache.total_refs 534785 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23989 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.292926 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20830.496331 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 857.499465 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 499.213631 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.635696 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.026169 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.015235 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.677100 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 80 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 20839.325928 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 913.017348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 501.206640 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.635966 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.027863 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.015296 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.679124 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 88 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 189212 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 189292 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 189300 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 435341 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 435341 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 237875 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 237875 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 80 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 427087 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 427167 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 80 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 427087 # number of overall hits -system.cpu.l2cache.overall_hits::total 427167 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1027 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 237876 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 237876 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 88 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 427088 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 427176 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 88 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 427088 # number of overall hits +system.cpu.l2cache.overall_hits::total 427176 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 4274 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5301 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21860 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21860 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1027 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26134 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27161 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1027 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26134 # number of overall misses -system.cpu.l2cache.overall_misses::total 27161 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53406000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_misses::total 5293 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 21859 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 21859 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 26133 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 27152 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1019 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 26133 # number of overall misses +system.cpu.l2cache.overall_misses::total 27152 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 52998000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 222248000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 275654000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1136720000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1136720000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 53406000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1358968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1412374000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 53406000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1358968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1412374000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 275246000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1136668000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1136668000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 52998000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1358916000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1411914000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 52998000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1358916000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1411914000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses) @@ -316,28 +316,28 @@ system.cpu.l2cache.demand_accesses::total 454328 # n system.cpu.l2cache.overall_accesses::cpu.inst 1107 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 453221 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.927733 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.920506 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022089 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.027241 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.084163 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.084163 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.927733 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.057663 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059783 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.927733 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.057663 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059783 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52001.947420 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_miss_rate::total 0.027200 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.084159 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.084159 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.920506 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.057661 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059763 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.920506 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.057661 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059763 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52009.813543 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.377287 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.889288 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52001.947420 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52009.813543 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.073635 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52001.947420 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.368297 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52009.813543 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.073635 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.368297 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,52 +346,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2523 # number of writebacks -system.cpu.l2cache.writebacks::total 2523 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1027 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 2518 # number of writebacks +system.cpu.l2cache.writebacks::total 2518 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4274 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5301 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21860 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21860 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1027 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26134 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27161 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1027 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26134 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27161 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41082000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_misses::total 5293 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21859 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21859 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26133 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27152 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26133 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27152 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40770000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 170960000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212042000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 874400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 874400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41082000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1045360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1086442000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41082000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1045360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1086442000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 211730000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 874360000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 874360000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40770000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1045320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1086090000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40770000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1045320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1086090000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022089 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027241 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.084163 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.084163 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059783 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059783 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.947420 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.084159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.084159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.057661 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059763 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.920506 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057661 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059763 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40009.813543 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.377287 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.889288 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.947420 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40009.813543 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.073635 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.947420 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40009.813543 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.073635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 24127a6e1..43ee6670c 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.609434 # Number of seconds simulated -sim_ticks 609433847500 # Number of ticks simulated -final_tick 609433847500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.610645 # Number of seconds simulated +sim_ticks 610645123000 # Number of ticks simulated +final_tick 610645123000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61609 # Simulator instruction rate (inst/s) -host_op_rate 113518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42665232 # Simulator tick rate (ticks/s) -host_mem_usage 229588 # Number of bytes of host memory used -host_seconds 14284.09 # Real time elapsed on the host +host_inst_rate 90668 # Simulator instruction rate (inst/s) +host_op_rate 167061 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62914134 # Simulator tick rate (ticks/s) +host_mem_usage 229848 # Number of bytes of host memory used +host_seconds 9706.01 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493925 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 58176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1694272 # Number of bytes read from this memory -system.physmem.bytes_read::total 1752448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 58176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 58176 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162816 # Number of bytes written to this memory -system.physmem.bytes_written::total 162816 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 909 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26473 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27382 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2544 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2544 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2780075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2875534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95459 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95459 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 267159 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 267159 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 267159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2780075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3142694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27384 # Total number of read requests seen -system.physmem.writeReqs 2544 # Total number of write requests seen -system.physmem.cpureqs 29928 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1752448 # Total number of bytes read from memory -system.physmem.bytesWritten 162816 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1752448 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162816 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 13 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 58048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1693312 # Number of bytes read from this memory +system.physmem.bytes_read::total 1751360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 58048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 58048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162176 # Number of bytes written to this memory +system.physmem.bytes_written::total 162176 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26458 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27365 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2534 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2534 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 95060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2772989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2868049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 95060 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 95060 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 265581 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 265581 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 265581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 95060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2772989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3133630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27367 # Total number of read requests seen +system.physmem.writeReqs 2534 # Total number of write requests seen +system.physmem.cpureqs 29901 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1751360 # Total number of bytes read from memory +system.physmem.bytesWritten 162176 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1751360 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162176 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1748 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1754 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1781 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1776 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1711 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1756 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1780 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1777 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1811 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1712 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1638 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1637 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1661 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1666 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1692 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 155 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 166 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 167 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 158 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 154 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 156 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 609433834000 # Total gap between requests +system.physmem.totGap 610645109000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27384 # Categorize read packet sizes +system.physmem.readPktSize::6 27367 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2544 # categorize write packet sizes +system.physmem.writePktSize::6 2534 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,13 +105,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 26904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 26902 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -142,16 +142,16 @@ system.physmem.wrQLenPdf::0 111 # Wh system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see @@ -171,264 +171,264 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 56299249 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 811057249 # Sum of mem lat for all requests -system.physmem.totBusLat 109484000 # Total cycles spent in databus access -system.physmem.totBankLat 645274000 # Total cycles spent in bank access -system.physmem.avgQLat 2056.89 # Average queueing delay per request -system.physmem.avgBankLat 23575.10 # Average bank access latency per request +system.physmem.totQLat 68648669 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 822368669 # Sum of mem lat for all requests +system.physmem.totBusLat 109468000 # Total cycles spent in databus access +system.physmem.totBankLat 644252000 # Total cycles spent in bank access +system.physmem.avgQLat 2508.45 # Average queueing delay per request +system.physmem.avgBankLat 23541.20 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29631.99 # Average memory access latency -system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 30049.65 # Average memory access latency +system.physmem.avgRdBW 2.87 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.27 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 8.89 # Average write queue length over time -system.physmem.readRowHits 17700 # Number of row buffer hits during reads -system.physmem.writeRowHits 1376 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 54.09 # Row buffer hit rate for writes -system.physmem.avgGap 20363333.13 # Average gap between requests +system.physmem.avgWrQLen 9.42 # Average write queue length over time +system.physmem.readRowHits 17709 # Number of row buffer hits during reads +system.physmem.writeRowHits 1083 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 42.74 # Row buffer hit rate for writes +system.physmem.avgGap 20422230.33 # Average gap between requests system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1218867696 # number of cpu cycles simulated +system.cpu.numCycles 1221290247 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 154233173 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 154233173 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 26682976 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 75825299 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 75424108 # Number of BTB hits +system.cpu.BPredUnit.lookups 153796448 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 153796448 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 26699295 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 76444965 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 76044325 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180166559 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1483545531 # Number of instructions fetch has processed -system.cpu.fetch.Branches 154233173 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 75424108 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 400496189 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 91879143 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 573121383 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 424 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 185204471 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8524885 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1218826768 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.080610 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.274340 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180218290 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1484873312 # Number of instructions fetch has processed +system.cpu.fetch.Branches 153796448 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 76044325 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 400561886 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 92153015 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 574855756 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 434 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 186235545 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 9536973 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1220934154 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.078258 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.273787 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 825549489 67.73% 67.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24308401 1.99% 69.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15365270 1.26% 70.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17994568 1.48% 72.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26708645 2.19% 74.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18181975 1.49% 76.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 28608277 2.35% 78.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39394925 3.23% 81.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 222715218 18.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 827594377 67.78% 67.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24117068 1.98% 69.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15648261 1.28% 71.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17796387 1.46% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26716755 2.19% 74.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18183763 1.49% 76.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 28386980 2.33% 78.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39418545 3.23% 81.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 223072018 18.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1218826768 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126538 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.217151 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 289191573 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 496681660 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 275162301 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92749072 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 65042162 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2356227760 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 65042162 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 337598744 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 122716382 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1927 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 305616336 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 387851217 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2259951612 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 313 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242131587 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 121014894 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2627036833 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5767802630 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5767798158 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4472 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1220934154 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.125929 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.215823 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 289407961 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 498246191 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 275145699 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92836570 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 65297733 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2356719721 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 65297733 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 337924282 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 123917110 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2381 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 305534064 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 388258584 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2260509367 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 337 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242606329 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120880984 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2627145665 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5770220684 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5770216108 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4576 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895257 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 740141576 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 82 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 82 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 730432949 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 541717387 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220348120 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 348120905 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144711749 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2012299347 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 522 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1784417764 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 261262 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 390397150 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 813518141 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 472 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1218826768 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.464045 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.419425 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 740250408 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 92 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 92 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 731279841 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542420235 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220423040 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 348990798 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 145234295 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2013682993 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 521 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1784560921 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 286575 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 391758246 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 817229320 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 471 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1220934154 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.461636 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.419528 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 363571086 29.83% 29.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 365294377 29.97% 59.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234631055 19.25% 79.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141184624 11.58% 90.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60758407 4.98% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 40069639 3.29% 98.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10832423 0.89% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1950212 0.16% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 534945 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 365719162 29.95% 29.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 365027224 29.90% 59.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234751927 19.23% 79.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141361627 11.58% 90.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60962306 4.99% 95.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39637127 3.25% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10977510 0.90% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1933125 0.16% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 564146 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1218826768 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1220934154 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 467444 16.32% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2152766 75.14% 91.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 244877 8.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 457693 15.95% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2209699 77.01% 92.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 202113 7.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46817146 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1065882672 59.73% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 479009051 26.84% 89.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192708895 10.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812464 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065891237 59.73% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 479189352 26.85% 89.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192667868 10.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1784417764 # Type of FU issued -system.cpu.iq.rate 1.463996 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2865087 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001606 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4790788107 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2402871988 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1725236233 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 538 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1508 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1740465474 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 209679766 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1784560921 # Type of FU issued +system.cpu.iq.rate 1.461210 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2869505 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001608 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4793211641 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2405618854 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1725377736 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 435 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1480 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 90 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1740617772 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 190 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 209954463 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 122675266 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 38585 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 181440 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 32162063 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 123378114 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 38587 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 183844 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 32236983 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2083 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2078 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 65042162 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 152720 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 14367 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2012299869 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63596984 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 541717387 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220348120 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6821 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 181440 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2121622 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24710303 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26831925 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766440348 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 474226114 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 17977416 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 65297733 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1143885 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 111744 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2013683514 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63490304 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 542420235 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220423040 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 86 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 55193 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2862 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 183844 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2121921 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24727534 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26849455 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766386720 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474113432 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 18174201 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 666063645 # number of memory reference insts executed -system.cpu.iew.exec_branches 110217721 # Number of branches executed -system.cpu.iew.exec_stores 191837531 # Number of stores executed -system.cpu.iew.exec_rate 1.449247 # Inst execution rate -system.cpu.iew.wb_sent 1726559885 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1725236341 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1267696731 # num instructions producing a value -system.cpu.iew.wb_consumers 1828647298 # num instructions consuming a value +system.cpu.iew.exec_refs 665931472 # number of memory reference insts executed +system.cpu.iew.exec_branches 110216269 # Number of branches executed +system.cpu.iew.exec_stores 191818040 # Number of stores executed +system.cpu.iew.exec_rate 1.446328 # Inst execution rate +system.cpu.iew.wb_sent 1726595079 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1725377826 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1268018973 # num instructions producing a value +system.cpu.iew.wb_consumers 1829950696 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.415442 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.693243 # average fanout of values written-back +system.cpu.iew.wb_rate 1.412750 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692925 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 390808265 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 392192006 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26683034 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1153784606 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.405370 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.832544 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26699352 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1155636421 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.403118 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.832114 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 420543726 36.45% 36.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 413309390 35.82% 72.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87337007 7.57% 79.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122231111 10.59% 90.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24478385 2.12% 92.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22989251 1.99% 94.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18567232 1.61% 96.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12074031 1.05% 97.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32254473 2.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 422545803 36.56% 36.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 413097230 35.75% 72.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 87361742 7.56% 79.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122290747 10.58% 90.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24514270 2.12% 92.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22708378 1.97% 94.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18848985 1.63% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12046038 1.04% 97.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32223228 2.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1153784606 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1155636421 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -439,298 +439,302 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32254473 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32223228 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3133832323 # The number of ROB reads -system.cpu.rob.rob_writes 4089684452 # The number of ROB writes -system.cpu.timesIdled 614 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 40928 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3137099124 # The number of ROB reads +system.cpu.rob.rob_writes 4092706915 # The number of ROB writes +system.cpu.timesIdled 59218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 356093 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.385037 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.385037 # CPI: Total CPI of All Threads -system.cpu.ipc 0.722002 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.722002 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3541814029 # number of integer regfile reads -system.cpu.int_regfile_writes 1975313076 # number of integer regfile writes -system.cpu.fp_regfile_reads 108 # number of floating regfile reads -system.cpu.misc_regfile_reads 910517303 # number of misc regfile reads -system.cpu.icache.replacements 21 # number of replacements -system.cpu.icache.tagsinuse 817.668717 # Cycle average of tags in use -system.cpu.icache.total_refs 185203176 # Total number of references to valid blocks. +system.cpu.cpi 1.387790 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.387790 # CPI: Total CPI of All Threads +system.cpu.ipc 0.720570 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.720570 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3541569732 # number of integer regfile reads +system.cpu.int_regfile_writes 1975385267 # number of integer regfile writes +system.cpu.fp_regfile_reads 90 # number of floating regfile reads +system.cpu.misc_regfile_reads 910403293 # number of misc regfile reads +system.cpu.icache.replacements 20 # number of replacements +system.cpu.icache.tagsinuse 822.205718 # Cycle average of tags in use +system.cpu.icache.total_refs 186234150 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 201526.850925 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 202648.694233 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 817.668717 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.399252 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.399252 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 185203176 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 185203176 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 185203176 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 185203176 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 185203176 # number of overall hits -system.cpu.icache.overall_hits::total 185203176 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1295 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1295 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1295 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1295 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1295 # number of overall misses -system.cpu.icache.overall_misses::total 1295 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39388000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39388000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39388000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39388000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39388000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39388000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 185204471 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 185204471 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 185204471 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 185204471 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 185204471 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 185204471 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 822.205718 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.401468 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.401468 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 186234151 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 186234151 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 186234151 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 186234151 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 186234151 # number of overall hits +system.cpu.icache.overall_hits::total 186234151 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1394 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1394 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1394 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1394 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1394 # number of overall misses +system.cpu.icache.overall_misses::total 1394 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 63295000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 63295000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 63295000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 63295000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 63295000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 63295000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 186235545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 186235545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 186235545 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 186235545 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 186235545 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 186235545 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30415.444015 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30415.444015 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30415.444015 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30415.444015 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30415.444015 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30415.444015 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45405.308465 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45405.308465 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45405.308465 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45405.308465 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45405.308465 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45405.308465 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 376 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 376 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 376 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 376 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 376 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 919 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 919 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 919 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 919 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30110000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 30110000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30110000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 30110000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30110000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 30110000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 472 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 472 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 472 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 472 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 472 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 472 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 922 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 922 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 922 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 922 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 922 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 922 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46053000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46053000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46053000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46053000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46053000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46053000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32763.873776 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32763.873776 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32763.873776 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 32763.873776 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32763.873776 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 32763.873776 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49949.023861 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49949.023861 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49949.023861 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49949.023861 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49949.023861 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49949.023861 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 445574 # number of replacements -system.cpu.dcache.tagsinuse 4093.370170 # Cycle average of tags in use -system.cpu.dcache.total_refs 452274995 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 449670 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1005.793126 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 737045000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.370170 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999358 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999358 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 264335239 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 264335239 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187939756 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187939756 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 452274995 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 452274995 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 452274995 # number of overall hits -system.cpu.dcache.overall_hits::total 452274995 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 208073 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 208073 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 246301 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 246301 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 454374 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 454374 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 454374 # number of overall misses -system.cpu.dcache.overall_misses::total 454374 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1068376500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1068376500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1644748000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1644748000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 2713124500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 2713124500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 2713124500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 2713124500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264543312 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264543312 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 445401 # number of replacements +system.cpu.dcache.tagsinuse 4092.926016 # Cycle average of tags in use +system.cpu.dcache.total_refs 451884939 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 449497 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1005.312469 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 828056000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4092.926016 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999250 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999250 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 263945150 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 263945150 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939786 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939786 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 451884936 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 451884936 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 451884936 # number of overall hits +system.cpu.dcache.overall_hits::total 451884936 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 210668 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 210668 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246271 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246271 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 456939 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 456939 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 456939 # number of overall misses +system.cpu.dcache.overall_misses::total 456939 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3009925000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3009925000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4061663000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4061663000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7071588000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7071588000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7071588000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7071588000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264155818 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264155818 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 452729369 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 452729369 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 452729369 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 452729369 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000787 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000787 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 452341875 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452341875 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452341875 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452341875 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001309 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.001004 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001004 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.001004 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001004 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5134.623425 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 5134.623425 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 6677.796680 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 6677.796680 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 5971.126209 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 5971.126209 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 5971.126209 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 5971.126209 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.001010 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001010 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001010 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001010 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14287.528243 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14287.528243 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16492.656464 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16492.656464 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15476.000079 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15476.000079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15476.000079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15476.000079 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 339 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.162162 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428583 # number of writebacks -system.cpu.dcache.writebacks::total 428583 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4687 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4687 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4702 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4702 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4702 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4702 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203386 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203386 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246286 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246286 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 449672 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 449672 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 449672 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 449672 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 641587500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 641587500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1151947500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1151947500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1793535000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1793535000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1793535000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1793535000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000769 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000769 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000993 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000993 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000993 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 3154.531285 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 3154.531285 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 4677.275606 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 4677.275606 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3988.540536 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 3988.540536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3988.540536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 3988.540536 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 428512 # number of writebacks +system.cpu.dcache.writebacks::total 428512 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7369 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7369 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 67 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 67 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7436 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7436 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7436 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7436 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203299 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203299 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246204 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246204 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 449503 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 449503 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 449503 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 449503 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2518009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2518009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3568493000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3568493000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6086502500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6086502500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6086502500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6086502500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12385.744642 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12385.744642 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14494.049650 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14494.049650 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13540.515859 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13540.515859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13540.515859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13540.515859 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2659 # number of replacements -system.cpu.l2cache.tagsinuse 22184.156099 # Cycle average of tags in use -system.cpu.l2cache.total_refs 517708 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24213 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.381407 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2556 # number of replacements +system.cpu.l2cache.tagsinuse 22261.498307 # Cycle average of tags in use +system.cpu.l2cache.total_refs 530423 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24197 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.921023 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20787.169449 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 726.088351 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 670.898299 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.634374 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.022158 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020474 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.677007 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 10 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 198821 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 198831 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 428583 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 428583 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224376 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 224376 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 10 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 423197 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 423207 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 10 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 423197 # number of overall hits -system.cpu.l2cache.overall_hits::total 423207 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 909 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 4554 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 5463 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 21921 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 21921 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 909 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 26475 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 27384 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 909 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 26475 # number of overall misses -system.cpu.l2cache.overall_misses::total 27384 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 29166500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 237800500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 266967000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 681146000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 681146000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 29166500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 918946500 # 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Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 198746 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 198758 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 428512 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 428512 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 224294 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 224294 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 423040 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 423052 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12 # 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number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44997500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 325370000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 370367500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1079389000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1079389000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 44997500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1404759000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1449756500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 44997500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1404759000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1449756500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 919 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 203375 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 204294 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 428583 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 428583 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246297 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246297 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 203289 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 204208 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 428512 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 428512 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246211 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246211 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 919 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 449672 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 450591 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 449500 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 450419 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 919 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 449672 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 450591 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.989119 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022392 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.026741 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089002 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.089002 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.989119 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.058876 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060774 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.989119 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.058876 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060774 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 32086.358636 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52217.940272 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48868.204283 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 31072.761279 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 31072.761279 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 32086.358636 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34709.971671 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34622.881975 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 32086.358636 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34709.971671 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34622.881975 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 449500 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 450419 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.986942 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022347 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.026688 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089017 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.089017 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.986942 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.058865 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060759 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.986942 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.058865 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060759 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49611.356119 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71620.074840 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67957.339450 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49248.939180 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49248.939180 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49611.356119 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53089.909297 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52974.622721 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49611.356119 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53089.909297 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52974.622721 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -739,52 +743,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2544 # number of writebacks -system.cpu.l2cache.writebacks::total 2544 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 909 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4554 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5463 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21921 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21921 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 909 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27384 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 909 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26475 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27384 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25917391 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 220807955 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 246725346 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 596009194 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 596009194 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25917391 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 816817149 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 842734540 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25917391 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 816817149 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 842734540 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.989119 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022392 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026741 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089002 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089002 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.989119 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058876 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060774 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.989119 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058876 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060774 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28511.981298 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48486.595301 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45162.977485 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 27188.960084 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 27188.960084 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28511.981298 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 30852.394674 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30774.705668 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28511.981298 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 30852.394674 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30774.705668 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 2534 # number of writebacks +system.cpu.l2cache.writebacks::total 2534 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 907 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4543 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5450 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21917 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21917 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 907 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26460 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27367 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 907 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26460 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27367 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33582421 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 267466906 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301049327 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 797222639 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 797222639 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33582421 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1064689545 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1098271966 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33582421 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1064689545 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1098271966 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022347 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026688 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089017 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089017 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058865 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060759 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986942 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058865 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060759 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37025.822492 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58874.511556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55238.408624 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36374.624219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36374.624219 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37025.822492 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40237.700113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40131.251727 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37025.822492 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40237.700113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40131.251727 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index e35ba34dd..ea680ba75 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.800193 # Number of seconds simulated -sim_ticks 1800193072000 # Number of ticks simulated -final_tick 1800193072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1800193396000 # Number of ticks simulated +final_tick 1800193396000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 480678 # Simulator instruction rate (inst/s) -host_op_rate 885676 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 983283018 # Simulator tick rate (ticks/s) -host_mem_usage 228792 # Number of bytes of host memory used -host_seconds 1830.80 # Real time elapsed on the host +host_inst_rate 332254 # Simulator instruction rate (inst/s) +host_op_rate 612196 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 679663607 # Simulator tick rate (ticks/s) +host_mem_usage 227800 # Number of bytes of host memory used +host_seconds 2648.65 # Real time elapsed on the host sim_insts 880025278 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory @@ -16,26 +16,26 @@ system.physmem.bytes_read::cpu.data 1682368 # Nu system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 160640 # Number of bytes written to this memory -system.physmem.bytes_written::total 160640 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 160704 # Number of bytes written to this memory +system.physmem.bytes_written::total 160704 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 26287 # Number of read requests responded to by this memory system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2510 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2510 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 2511 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2511 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 25668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 934549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 934548 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 960217 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 25668 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 25668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 89235 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 89235 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 89235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 89270 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 89270 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 89270 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 934549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1049452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 3600386144 # number of cpu cycles simulated +system.cpu.numCycles 3600386792 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 880025278 # Number of instructions committed @@ -54,16 +54,16 @@ system.cpu.num_mem_refs 607228178 # nu system.cpu.num_load_insts 419042121 # Number of load instructions system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3600386144 # Number of busy cycles +system.cpu.num_busy_cycles 3600386792 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 660.197374 # Cycle average of tags in use +system.cpu.icache.tagsinuse 660.197306 # Cycle average of tags in use system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 660.197374 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 660.197306 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.322362 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.322362 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 722 # n system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses system.cpu.icache.overall_misses::total 722 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39710000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39710000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39710000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39710000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39710000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39710000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39712000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39712000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39712000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39712000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39712000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39712000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1186516696 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1186516696 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1186516696 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55002.770083 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55002.770083 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55002.770083 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55002.770083 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55002.770083 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55002.770083 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,32 +116,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 722 system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38266000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38266000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38266000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38266000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38268000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38268000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38268000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38268000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38268000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38268000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53002.770083 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53002.770083 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements -system.cpu.dcache.tagsinuse 4094.905905 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.905744 # Cycle average of tags in use system.cpu.dcache.total_refs 606786130 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 1372.670230 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 771462000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.905905 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 771786000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.905744 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits @@ -162,12 +162,12 @@ system.cpu.dcache.overall_misses::cpu.data 442048 # system.cpu.dcache.overall_misses::total 442048 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 2746552000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4104707000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4104707000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6851259000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6851259000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6851259000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6851259000 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4105029000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4105029000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6851581000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6851581000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses) @@ -186,12 +186,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16772.938273 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16772.938273 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15498.902834 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15498.902834 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15498.902834 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15498.902834 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16774.254052 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16774.254052 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15499.631262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15499.631262 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,12 +212,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 442048 system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615263000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615263000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967163000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5967163000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967163000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5967163000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615585000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615585000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967485000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5967485000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967485000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5967485000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses @@ -228,26 +228,26 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14772.938273 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14772.938273 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13498.902834 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13498.902834 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13498.902834 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13498.902834 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14774.254052 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14774.254052 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2581 # number of replacements -system.cpu.l2cache.tagsinuse 22163.399604 # Cycle average of tags in use -system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks. +system.cpu.l2cache.replacements 2532 # number of replacements +system.cpu.l2cache.tagsinuse 22211.029339 # Cycle average of tags in use +system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 21.788687 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21020.012941 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 596.858262 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 546.528401 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.641480 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.018215 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21021.301366 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 643.199216 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 546.528757 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.641519 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.019629 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.016679 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.676373 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.677827 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 193009 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 193009 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits @@ -269,17 +269,17 @@ system.cpu.l2cache.demand_misses::total 27009 # nu system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 26287 # number of overall misses system.cpu.l2cache.overall_misses::total 27009 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37544000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37546000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 224484000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 262028000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1143021000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1143021000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 37544000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1367505000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1405049000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 37544000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1367505000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1405049000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 262030000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1143343000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1143343000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 37546000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1367827000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1405373000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37546000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1367827000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1405373000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses) @@ -304,17 +304,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.061000 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.059466 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.061000 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.770083 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52026.445152 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52026.445152 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52022.102180 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52021.511348 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52022.102180 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52021.511348 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.396904 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52041.101502 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52041.101502 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.770083 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52034.351581 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52033.507349 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.770083 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52034.351581 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52033.507349 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,8 +323,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 2510 # number of writebacks -system.cpu.l2cache.writebacks::total 2510 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 2511 # number of writebacks +system.cpu.l2cache.writebacks::total 2511 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4317 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 5039 # number of ReadReq MSHR misses @@ -336,17 +336,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27009 system.cpu.l2cache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26287 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27009 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28882000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201560000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 879381000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 879381000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1052061000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1080941000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1052061000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1080941000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201562000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 879703000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 879703000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28882000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1052383000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1081265000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28882000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1052383000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1081265000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021878 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025443 # mshr miss rate for ReadReq accesses @@ -358,17 +358,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.061000 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059466 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.061000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.770083 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40026.445152 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40026.445152 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40022.102180 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40021.511348 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40022.102180 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40021.511348 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.396904 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40041.101502 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40041.101502 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.770083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.770083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |