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-rw-r--r--tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini57
-rwxr-xr-xtests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout8
-rw-r--r--tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt27
-rw-r--r--tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini57
-rwxr-xr-xtests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt27
-rw-r--r--tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini21
-rwxr-xr-xtests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini68
-rwxr-xr-xtests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout12
-rw-r--r--tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt210
-rw-r--r--tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini37
-rwxr-xr-xtests/long/se/00.gzip/ref/arm/linux/o3-timing/simout10
-rw-r--r--tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt27
-rw-r--r--tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini34
-rwxr-xr-xtests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout8
-rw-r--r--tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini87
-rwxr-xr-xtests/long/se/00.gzip/ref/arm/linux/simple-timing/simout10
-rw-r--r--tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt226
-rw-r--r--tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini37
-rwxr-xr-xtests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout8
-rw-r--r--tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt27
-rw-r--r--tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini17
-rwxr-xr-xtests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout8
-rw-r--r--tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini64
-rwxr-xr-xtests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout10
-rw-r--r--tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt250
-rw-r--r--tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini37
-rwxr-xr-xtests/long/se/00.gzip/ref/x86/linux/o3-timing/simout8
-rw-r--r--tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt27
-rw-r--r--tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini10
-rwxr-xr-xtests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout4
-rw-r--r--tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini27
-rwxr-xr-xtests/long/se/00.gzip/ref/x86/linux/simple-timing/simout4
-rw-r--r--tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt210
39 files changed, 893 insertions, 837 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
index 8c8aecb35..5dbf49847 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,18 +31,13 @@ system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
@@ -57,17 +53,9 @@ dtb=system.cpu.dtb
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -76,11 +64,11 @@ memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
@@ -88,6 +76,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -95,21 +101,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -126,21 +127,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -163,21 +159,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -204,7 +195,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
index 5289b243e..fa0d94e1a 100755
--- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 11:21:21
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:19:12
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
index e8752c3e3..722ef4fea 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.269661 # Nu
sim_ticks 269661304500 # Number of ticks simulated
final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 125304 # Simulator instruction rate (inst/s)
-host_op_rate 125304 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56142087 # Simulator tick rate (ticks/s)
-host_mem_usage 214336 # Number of bytes of host memory used
-host_seconds 4803.19 # Real time elapsed on the host
+host_inst_rate 98682 # Simulator instruction rate (inst/s)
+host_op_rate 98682 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44214559 # Simulator tick rate (ticks/s)
+host_mem_usage 273520 # Number of bytes of host memory used
+host_seconds 6098.93 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
@@ -192,6 +192,15 @@ system.physmem.writeRowHits 51 # Nu
system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes
system.physmem.avgGap 9874807.84 # Average gap between requests
+system.cpu.branchPred.lookups 86405274 # Number of BP lookups
+system.cpu.branchPred.condPredicted 81476244 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 36343014 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 44773910 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 34660000 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 77.411153 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -228,14 +237,6 @@ system.cpu.workload.num_syscalls 17 # Nu
system.cpu.numCycles 539322610 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 86405274 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 81476244 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 36343014 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 44773910 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 34660000 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 77.411153 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index ba863cc04..daf1db8c9 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -56,7 +53,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -116,6 +103,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -125,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -132,21 +138,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -426,21 +427,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -463,21 +459,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -504,7 +495,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
index 396a60755..043586087 100755
--- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 11:21:56
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:43:44
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index 759350e06..393ed8f87 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.133779 # Nu
sim_ticks 133778696500 # Number of ticks simulated
final_tick 133778696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 208111 # Simulator instruction rate (inst/s)
-host_op_rate 208111 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 49227708 # Simulator tick rate (ticks/s)
-host_mem_usage 215496 # Number of bytes of host memory used
-host_seconds 2717.55 # Real time elapsed on the host
+host_inst_rate 160169 # Simulator instruction rate (inst/s)
+host_op_rate 160169 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37887208 # Simulator tick rate (ticks/s)
+host_mem_usage 273648 # Number of bytes of host memory used
+host_seconds 3530.97 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
sim_ops 565552443 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory
@@ -192,6 +192,15 @@ system.physmem.writeRowHits 53 # Nu
system.physmem.readRowHitRate 68.08 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 5.06 # Row buffer hit rate for writes
system.physmem.avgGap 4852854.06 # Average gap between requests
+system.cpu.branchPred.lookups 76440222 # Number of BP lookups
+system.cpu.branchPred.condPredicted 70864810 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2706098 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 43060392 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 41933015 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 97.381870 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1604413 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -228,14 +237,6 @@ system.cpu.workload.num_syscalls 17 # Nu
system.cpu.numCycles 267557394 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 76440222 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 70864810 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2706098 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 43060392 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 41933015 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1604413 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 67119409 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 699052842 # Number of instructions fetch has processed
system.cpu.fetch.Branches 76440222 # Number of branches that fetch encountered
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
index 352fd32f4..7721bd66e 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,17 +44,18 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -82,7 +88,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -99,14 +105,15 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
index a4781a82f..251ff8bcc 100755
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 14:03:38
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:29:25
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
index 7df2c8121..0780eabd0 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.300931 # Nu
sim_ticks 300930958000 # Number of ticks simulated
final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3871430 # Simulator instruction rate (inst/s)
-host_op_rate 3871429 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1935730316 # Simulator tick rate (ticks/s)
-host_mem_usage 206040 # Number of bytes of host memory used
-host_seconds 155.46 # Real time elapsed on the host
+host_inst_rate 2641824 # Simulator instruction rate (inst/s)
+host_op_rate 2641824 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1320922836 # Simulator tick rate (ticks/s)
+host_mem_usage 264040 # Number of bytes of host memory used
+host_seconds 227.82 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index a9c226ca1..8bc6aea44 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -41,15 +43,16 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,21 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -90,21 +90,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -113,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -120,23 +120,20 @@ size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -145,10 +142,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -158,12 +155,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -181,13 +178,14 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
index fcee711f2..3c503ab1f 100755
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:30:56
-gem5 started Jul 2 2012 09:11:02
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:50:54
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@@ -39,4 +41,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 764109115000 because target called exit()
+Exiting @ tick 762403375000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
index f1f52256e..19cf772df 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.762403 # Nu
sim_ticks 762403375000 # Number of ticks simulated
final_tick 762403375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2059312 # Simulator instruction rate (inst/s)
-host_op_rate 2059312 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2608636387 # Simulator tick rate (ticks/s)
-host_mem_usage 217100 # Number of bytes of host memory used
-host_seconds 292.26 # Real time elapsed on the host
+host_inst_rate 1151537 # Simulator instruction rate (inst/s)
+host_op_rate 1151537 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1458711281 # Simulator tick rate (ticks/s)
+host_mem_usage 272496 # Number of bytes of host memory used
+host_seconds 522.66 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
@@ -167,106 +167,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52367.295597
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52367.295597 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52367.295597 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 451299 # number of replacements
-system.cpu.dcache.tagsinuse 4094.203488 # Cycle average of tags in use
-system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 563363000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.203488 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 39197158 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 153509968 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 153509968 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 153509968 # number of overall hits
-system.cpu.dcache.overall_hits::total 153509968 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 201232 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 201232 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 254163 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 254163 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 455395 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses
-system.cpu.dcache.overall_misses::total 455395 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789356000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2789356000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4199727000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4199727000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 6989083000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 6989083000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 6989083000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 6989083000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.001757 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.006442 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13861.393814 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13861.393814 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16523.754441 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 16523.754441 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15347.298499 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15347.298499 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
-system.cpu.dcache.writebacks::total 436887 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386892000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386892000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3691401000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3691401000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078293000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6078293000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078293000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6078293000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11861.393814 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11861.393814 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14523.754441 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14523.754441 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1028 # number of replacements
system.cpu.l2cache.tagsinuse 22854.086849 # Cycle average of tags in use
system.cpu.l2cache.total_refs 531883 # Total number of references to valid blocks.
@@ -405,5 +305,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.277139
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.235747 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.266829 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 451299 # number of replacements
+system.cpu.dcache.tagsinuse 4094.203488 # Cycle average of tags in use
+system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 563363000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4094.203488 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 39197158 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 153509968 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 153509968 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 153509968 # number of overall hits
+system.cpu.dcache.overall_hits::total 153509968 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 201232 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 201232 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 254163 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 254163 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 455395 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses
+system.cpu.dcache.overall_misses::total 455395 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789356000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 2789356000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4199727000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4199727000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 6989083000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 6989083000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 6989083000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 6989083000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.001757 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.006442 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13861.393814 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13861.393814 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16523.754441 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 16523.754441 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15347.298499 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15347.298499 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
+system.cpu.dcache.writebacks::total 436887 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386892000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386892000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3691401000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3691401000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078293000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6078293000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078293000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6078293000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11861.393814 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11861.393814 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14523.754441 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14523.754441 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
index 358021124..67f052df7 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -522,7 +527,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/arm/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
index afe1d756a..385dec7c7 100755
--- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:34:09
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:48:55
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -38,4 +40,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 164568389500 because target called exit()
+Exiting @ tick 164543008000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
index 3adbcac4f..08bc3f5b4 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.164543 # Nu
sim_ticks 164543008000 # Number of ticks simulated
final_tick 164543008000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 153982 # Simulator instruction rate (inst/s)
-host_op_rate 162709 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44446364 # Simulator tick rate (ticks/s)
-host_mem_usage 244392 # Number of bytes of host memory used
-host_seconds 3702.06 # Real time elapsed on the host
+host_inst_rate 116480 # Simulator instruction rate (inst/s)
+host_op_rate 123082 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33621508 # Simulator tick rate (ticks/s)
+host_mem_usage 289348 # Number of bytes of host memory used
+host_seconds 4893.98 # Real time elapsed on the host
sim_insts 570051585 # Number of instructions simulated
sim_ops 602359791 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46912 # Number of bytes read from this memory
@@ -192,6 +192,15 @@ system.physmem.writeRowHits 1096 # Nu
system.physmem.readRowHitRate 64.99 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 43.15 # Row buffer hit rate for writes
system.physmem.avgGap 5511958.73 # Average gap between requests
+system.cpu.branchPred.lookups 85130885 # Number of BP lookups
+system.cpu.branchPred.condPredicted 79914937 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2339051 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 47115734 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 46860934 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 99.459204 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1427305 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 879 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -238,14 +247,6 @@ system.cpu.workload.num_syscalls 48 # Nu
system.cpu.numCycles 329086017 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 85130885 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 79914937 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2339051 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 47115734 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 46860934 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1427305 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 879 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 68482650 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 666733796 # Number of instructions fetch has processed
system.cpu.fetch.Branches 85130885 # Number of branches that fetch encountered
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
index c50a349bb..69cb08fc5 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -68,7 +71,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@@ -76,6 +79,23 @@ port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -84,7 +104,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@@ -100,7 +120,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -124,7 +144,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
index 21bacf71f..4b045d847 100755
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:41:05
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:49:37
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
index b109fcbb9..0212f6dff 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.301191 # Nu
sim_ticks 301191365000 # Number of ticks simulated
final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2514683 # Simulator instruction rate (inst/s)
-host_op_rate 2657205 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1328652667 # Simulator tick rate (ticks/s)
-host_mem_usage 218896 # Number of bytes of host memory used
-host_seconds 226.69 # Real time elapsed on the host
+host_inst_rate 1714897 # Simulator instruction rate (inst/s)
+host_op_rate 1812090 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 906079333 # Simulator tick rate (ticks/s)
+host_mem_usage 278712 # Number of bytes of host memory used
+host_seconds 332.41 # Real time elapsed on the host
sim_insts 570051636 # Number of instructions simulated
sim_ops 602359842 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
index e485b6133..d0ef21f1f 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,23 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -91,7 +89,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -101,23 +99,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -126,6 +119,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -134,7 +144,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -142,25 +152,20 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -169,10 +174,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -187,7 +192,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -211,7 +216,7 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
index 2c7022400..a939cde5a 100755
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:37:42
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:54:17
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -38,4 +40,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 795270546000 because target called exit()
+Exiting @ tick 793670137000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
index 3042021d4..42a2fd6fd 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.793670 # Nu
sim_ticks 793670137000 # Number of ticks simulated
final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 897110 # Simulator instruction rate (inst/s)
-host_op_rate 947381 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1252348386 # Simulator tick rate (ticks/s)
-host_mem_usage 231392 # Number of bytes of host memory used
-host_seconds 633.75 # Real time elapsed on the host
+host_inst_rate 904187 # Simulator instruction rate (inst/s)
+host_op_rate 954854 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1262227313 # Simulator tick rate (ticks/s)
+host_mem_usage 287296 # Number of bytes of host memory used
+host_seconds 628.79 # Real time elapsed on the host
sim_insts 568539335 # Number of instructions simulated
sim_ops 600398272 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory
@@ -177,114 +177,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50387.247278
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 433468 # number of replacements
-system.cpu.dcache.tagsinuse 4094.241219 # Cycle average of tags in use
-system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 529622000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.241219 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 216771818 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 216771818 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 216771818 # number of overall hits
-system.cpu.dcache.overall_hits::total 216771818 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
-system.cpu.dcache.overall_misses::total 437564 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2650304000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2650304000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4137794000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4137794000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 6788098000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 6788098000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 6788098000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 6788098000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 217209382 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 217209382 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 217209382 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 217209382 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13962.489990 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13962.489990 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16701.624231 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 16701.624231 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15513.383185 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15513.383185 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 418626 # number of writebacks
-system.cpu.dcache.writebacks::total 418626 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2270672000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2270672000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3642298000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3642298000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5912970000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 5912970000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5912970000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 5912970000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11962.489990 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11962.489990 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14701.624231 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14701.624231 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2512 # number of replacements
system.cpu.l2cache.tagsinuse 22024.775302 # Cycle average of tags in use
system.cpu.l2cache.total_refs 506990 # Total number of references to valid blocks.
@@ -423,5 +315,113 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 433468 # number of replacements
+system.cpu.dcache.tagsinuse 4094.241219 # Cycle average of tags in use
+system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 529622000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4094.241219 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 216771818 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 216771818 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 216771818 # number of overall hits
+system.cpu.dcache.overall_hits::total 216771818 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
+system.cpu.dcache.overall_misses::total 437564 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 2650304000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 2650304000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4137794000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4137794000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 6788098000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 6788098000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 6788098000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 6788098000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 217209382 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 217209382 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 217209382 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 217209382 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13962.489990 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13962.489990 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16701.624231 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 16701.624231 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15513.383185 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15513.383185 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 418626 # number of writebacks
+system.cpu.dcache.writebacks::total 418626 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2270672000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2270672000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3642298000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3642298000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5912970000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 5912970000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5912970000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 5912970000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11962.489990 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11962.489990 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14701.624231 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14701.624231 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
index a8742bbf7..a9b3fe841 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -490,7 +495,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/sparc/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
index 4ff3426c2..1884422eb 100755
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:16:54
-gem5 started Jan 4 2013 22:00:02
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 15:52:06
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index 14b499f19..6eebaa49a 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.387280 # Nu
sim_ticks 387279743500 # Number of ticks simulated
final_tick 387279743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 70741 # Simulator instruction rate (inst/s)
-host_op_rate 70964 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 19552386 # Simulator tick rate (ticks/s)
-host_mem_usage 225936 # Number of bytes of host memory used
-host_seconds 19807.29 # Real time elapsed on the host
+host_inst_rate 131929 # Simulator instruction rate (inst/s)
+host_op_rate 132344 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 36464205 # Simulator tick rate (ticks/s)
+host_mem_usage 283820 # Number of bytes of host memory used
+host_seconds 10620.82 # Real time elapsed on the host
sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 76416 # Number of bytes read from this memory
@@ -192,18 +192,19 @@ system.physmem.writeRowHits 1098 # Nu
system.physmem.readRowHitRate 66.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 43.35 # Row buffer hit rate for writes
system.physmem.avgGap 12929580.19 # Average gap between requests
+system.cpu.branchPred.lookups 97757265 # Number of BP lookups
+system.cpu.branchPred.condPredicted 88048400 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 3615880 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 65812942 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 65493412 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 99.514488 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1346 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 774559488 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 97757265 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 88048400 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 3615880 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 65812942 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 65493412 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1346 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 164857001 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1642241879 # Number of instructions fetch has processed
system.cpu.fetch.Branches 97757265 # Number of branches that fetch encountered
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
index bd29989f9..1cdc6be7c 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,17 +44,18 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -82,7 +88,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -105,8 +111,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
index a424ec0a0..e021ad978 100755
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:13:47
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:12:25
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
index 4e5a83c19..9073b6f33 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.744764 # Nu
sim_ticks 744764112500 # Number of ticks simulated
final_tick 744764112500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3155762 # Simulator instruction rate (inst/s)
-host_op_rate 3165144 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1582576951 # Simulator tick rate (ticks/s)
-host_mem_usage 222108 # Number of bytes of host memory used
-host_seconds 470.60 # Real time elapsed on the host
+host_inst_rate 2243211 # Simulator instruction rate (inst/s)
+host_op_rate 2249879 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1124943447 # Simulator tick rate (ticks/s)
+host_mem_usage 273192 # Number of bytes of host memory used
+host_seconds 662.05 # Real time elapsed on the host
sim_insts 1485108088 # Number of instructions simulated
sim_ops 1489523282 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 5940451992 # Number of bytes read from this memory
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
index cd17d9d73..aa371f8c0 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -41,15 +43,16 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,21 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -90,21 +90,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -113,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -120,23 +120,20 @@ size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -145,10 +142,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -163,7 +160,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -186,8 +183,9 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
index 7275352c5..c3ba5bf5e 100755
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:13:49
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 15:49:34
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -38,4 +40,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2063177737000 because target called exit()
+Exiting @ tick 2061066313000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index d4dde6ec1..226830c92 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 2.061066 # Nu
sim_ticks 2061066313000 # Number of ticks simulated
final_tick 2061066313000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 632829 # Simulator instruction rate (inst/s)
-host_op_rate 634711 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 878254717 # Simulator tick rate (ticks/s)
-host_mem_usage 225052 # Number of bytes of host memory used
-host_seconds 2346.78 # Real time elapsed on the host
+host_inst_rate 1083437 # Simulator instruction rate (inst/s)
+host_op_rate 1086658 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1503618533 # Simulator tick rate (ticks/s)
+host_mem_usage 281644 # Number of bytes of host memory used
+host_seconds 1370.74 # Real time elapsed on the host
sim_insts 1485108088 # Number of instructions simulated
sim_ops 1489523282 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
@@ -135,126 +135,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 49670.280036
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 449125 # number of replacements
-system.cpu.dcache.tagsinuse 4095.236014 # Cycle average of tags in use
-system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 559340000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4095.236014 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999813 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data 568906445 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 568906445 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 568906445 # number of overall hits
-system.cpu.dcache.overall_hits::total 568906445 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 259728 # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
-system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data 453214 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses
-system.cpu.dcache.overall_misses::total 453214 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2694826000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2694826000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294500000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4294500000 # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data 133000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total 133000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 6989326000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 6989326000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 6989326000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 6989326000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 569359659 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 569359659 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 569359659 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 569359659 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.001557 # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13927.757047 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.605433 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.605433 # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 19000 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15421.690416 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15421.690416 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 435341 # number of writebacks
-system.cpu.dcache.writebacks::total 435341 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 259728 # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 453214 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775044000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775044000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082898000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6082898000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082898000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6082898000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001557 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.605433 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.605433 # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2539 # number of replacements
system.cpu.l2cache.tagsinuse 22253.549915 # Cycle average of tags in use
system.cpu.l2cache.total_refs 534785 # Total number of references to valid blocks.
@@ -393,5 +273,125 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40009.813543
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 449125 # number of replacements
+system.cpu.dcache.tagsinuse 4095.236014 # Cycle average of tags in use
+system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 559340000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4095.236014 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999813 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data 568906445 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 568906445 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 568906445 # number of overall hits
+system.cpu.dcache.overall_hits::total 568906445 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 259728 # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses
+system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses
+system.cpu.dcache.demand_misses::cpu.data 453214 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses
+system.cpu.dcache.overall_misses::total 453214 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 2694826000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 2694826000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4294500000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4294500000 # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data 133000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total 133000 # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 6989326000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 6989326000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 6989326000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 6989326000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 569359659 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 569359659 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 569359659 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 569359659 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.001557 # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13927.757047 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.605433 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.605433 # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 19000 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15421.690416 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15421.690416 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 435341 # number of writebacks
+system.cpu.dcache.writebacks::total 435341 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 259728 # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 453214 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775044000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775044000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082898000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6082898000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082898000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6082898000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001557 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.605433 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.605433 # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
index 0e20d1517..96720c6a8 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -514,7 +519,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/x86/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
index c000af4ff..a29e79bee 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:20:54
-gem5 started Jan 4 2013 22:11:32
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:48:34
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
index 6e46a8347..3548dbe1a 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.607446 # Nu
sim_ticks 607445544000 # Number of ticks simulated
final_tick 607445544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 35384 # Simulator instruction rate (inst/s)
-host_op_rate 65197 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 24424271 # Simulator tick rate (ticks/s)
-host_mem_usage 239876 # Number of bytes of host memory used
-host_seconds 24870.57 # Real time elapsed on the host
+host_inst_rate 56942 # Simulator instruction rate (inst/s)
+host_op_rate 104918 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 39304494 # Simulator tick rate (ticks/s)
+host_mem_usage 295872 # Number of bytes of host memory used
+host_seconds 15454.86 # Real time elapsed on the host
sim_insts 880025277 # Number of instructions simulated
sim_ops 1621493926 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 57728 # Number of bytes read from this memory
@@ -192,18 +192,19 @@ system.physmem.writeRowHits 1084 # Nu
system.physmem.readRowHitRate 64.68 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 42.78 # Row buffer hit rate for writes
system.physmem.avgGap 20320661.36 # Average gap between requests
+system.cpu.branchPred.lookups 158385701 # Number of BP lookups
+system.cpu.branchPred.condPredicted 158385701 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 26390414 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 84292336 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 84079165 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 99.747105 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1214891089 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 158385701 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 158385701 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 26390414 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 84292336 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 84079165 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 179135725 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1458430747 # Number of instructions fetch has processed
system.cpu.fetch.Branches 158385701 # Number of branches that fetch encountered
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
index 6f8b69a5a..8a8a24651 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -15,6 +15,7 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -83,6 +86,9 @@ int_master=system.membus.slave[5]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
index c175f0374..6792b9773 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:35:29
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:52:14
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index 5647e6e6c..a1cb93ee9 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.963993 # Nu
sim_ticks 963992671500 # Number of ticks simulated
final_tick 963992671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 908989 # Simulator instruction rate (inst/s)
-host_op_rate 1674860 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 995719480 # Simulator tick rate (ticks/s)
-host_mem_usage 267620 # Number of bytes of host memory used
-host_seconds 968.14 # Real time elapsed on the host
+host_inst_rate 911190 # Simulator instruction rate (inst/s)
+host_op_rate 1678916 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 998130396 # Simulator tick rate (ticks/s)
+host_mem_usage 284224 # Number of bytes of host memory used
+host_seconds 965.80 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
sim_ops 1621493927 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
index 156174801..5736b9341 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -63,21 +66,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -102,21 +100,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -133,6 +126,9 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
@@ -152,21 +148,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
index ad62c8d74..5f5879b0d 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timin
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:35:29
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:22:44
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
index 87bad38e6..088aad8da 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 1.800193 # Nu
sim_ticks 1800193397000 # Number of ticks simulated
final_tick 1800193397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 477976 # Simulator instruction rate (inst/s)
-host_op_rate 880696 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 977754272 # Simulator tick rate (ticks/s)
-host_mem_usage 276196 # Number of bytes of host memory used
-host_seconds 1841.15 # Real time elapsed on the host
+host_inst_rate 575805 # Simulator instruction rate (inst/s)
+host_op_rate 1060952 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1177876462 # Simulator tick rate (ticks/s)
+host_mem_usage 292800 # Number of bytes of host memory used
+host_seconds 1528.34 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
sim_ops 1621493927 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
@@ -135,106 +135,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53002.770083
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 437952 # number of replacements
-system.cpu.dcache.tagsinuse 4094.905742 # Cycle average of tags in use
-system.cpu.dcache.total_refs 606786131 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 1372.670233 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 771787000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.905742 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615585000 # number of WriteReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 5967485000 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses
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-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14774.254052 # average WriteReq mshr miss latency
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
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-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2532 # number of replacements
system.cpu.l2cache.tagsinuse 22211.029327 # Cycle average of tags in use
system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks.
@@ -370,5 +270,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.770083
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------