diff options
Diffstat (limited to 'tests/long/se/00.gzip')
9 files changed, 612 insertions, 597 deletions
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index 3e3a921c2..9953e7dde 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -157,8 +159,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -430,16 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -461,8 +465,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -471,16 +475,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=false -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=2097152 subblock_size=0 system=system @@ -507,12 +513,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -530,13 +536,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 71d01f629..21a8a9bfd 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:22:13 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:54:44 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 164812294500 because target called exit() +Exiting @ tick 164735271500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index c74978b2c..3e2378b89 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164804 # Number of seconds simulated -sim_ticks 164803697500 # Number of ticks simulated -final_tick 164803697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164735 # Number of seconds simulated +sim_ticks 164735271500 # Number of ticks simulated +final_tick 164735271500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 225505 # Simulator instruction rate (inst/s) -host_op_rate 238286 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65194032 # Simulator tick rate (ticks/s) -host_mem_usage 234780 # Number of bytes of host memory used -host_seconds 2527.90 # Real time elapsed on the host -sim_insts 570052730 # Number of instructions simulated -sim_ops 602360936 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1769280 # Number of bytes read from this memory -system.physmem.bytes_read::total 1816896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 202944 # Number of bytes written to this memory -system.physmem.bytes_written::total 202944 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27645 # Number of read requests responded to by this memory -system.physmem.num_reads::total 28389 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 3171 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3171 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 288926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10735681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11024607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 288926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 288926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1231429 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1231429 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1231429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 288926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10735681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12256036 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 151833 # Simulator instruction rate (inst/s) +host_op_rate 160438 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43876980 # Simulator tick rate (ticks/s) +host_mem_usage 229232 # Number of bytes of host memory used +host_seconds 3754.48 # Real time elapsed on the host +sim_insts 570052715 # Number of instructions simulated +sim_ops 602360921 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1771392 # Number of bytes read from this memory +system.physmem.bytes_read::total 1819904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 204096 # Number of bytes written to this memory +system.physmem.bytes_written::total 204096 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27678 # Number of read requests responded to by this memory +system.physmem.num_reads::total 28436 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 3189 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3189 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 294485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10752961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11047446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 294485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 294485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1238933 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1238933 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1238933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 294485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10752961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12286379 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,141 +77,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329607396 # number of cpu cycles simulated +system.cpu.numCycles 329470544 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85521262 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80324005 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2361364 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47163773 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46836425 # Number of BTB hits +system.cpu.BPredUnit.lookups 85543194 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80343428 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2410851 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47247808 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46879382 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1442496 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 971 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68931742 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669855776 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85521262 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48278921 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130072968 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13495551 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119465420 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1438508 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 957 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68858387 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669531966 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85543194 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48317890 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130053558 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13436601 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119467619 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 697 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67497575 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 806206 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 329517095 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.166390 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.195660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 664 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67410579 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 785974 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 329380053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.166154 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.195076 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 199444353 60.53% 60.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20947099 6.36% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4950101 1.50% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14318334 4.35% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8976585 2.72% 75.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9434873 2.86% 78.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4385962 1.33% 79.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5814434 1.76% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61245354 18.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 199326735 60.52% 60.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20925869 6.35% 66.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4976270 1.51% 68.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14401478 4.37% 72.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8915823 2.71% 75.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9447821 2.87% 78.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4394131 1.33% 79.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5797396 1.76% 81.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61194530 18.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 329517095 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259464 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.032284 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93615293 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96153951 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108189677 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20513543 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11044631 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4783839 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1715 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 706162861 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6102 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11044631 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107837587 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14124315 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49845 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114419609 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82041108 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697343102 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59702950 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20121716 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723953896 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3241969745 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3241969617 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 329380053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.259638 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.032145 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93515183 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96161670 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108196547 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20508331 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10998322 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4720780 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1591 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 705885224 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5921 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10998322 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107743564 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14112964 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 43222 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114413091 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82068890 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697152675 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 157 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59727344 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20123270 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 641 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723862465 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3241326776 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241326648 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627419205 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96534691 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6461 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6411 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169960309 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172942863 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80636505 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21738448 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28392401 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 682081084 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4755 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646873471 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1427255 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79546312 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 198336630 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1822 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 329517095 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.963095 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.726025 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627419181 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96443284 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2057 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2011 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169978483 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172921644 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80622072 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21488970 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28010178 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 681988292 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3275 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646797787 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1412727 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79459503 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 198007283 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 345 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 329380053 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.963682 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.727918 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 69073062 20.96% 20.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85428169 25.93% 46.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 76011979 23.07% 69.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40983157 12.44% 82.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28619491 8.69% 91.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15088313 4.58% 95.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5676552 1.72% 97.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6597944 2.00% 99.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2038428 0.62% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 69019799 20.95% 20.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85512996 25.96% 46.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75829369 23.02% 69.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 41034711 12.46% 82.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28570777 8.67% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15062101 4.57% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5699719 1.73% 97.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6474655 1.97% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2175926 0.66% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 329517095 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 329380053 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 205689 5.35% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2625601 68.27% 73.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1014507 26.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 206481 5.38% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2616685 68.13% 73.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1017800 26.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403948716 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6566 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403890666 62.44% 62.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6567 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -239,157 +239,157 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166134463 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76783723 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166105526 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76795025 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646873471 # Type of FU issued -system.cpu.iq.rate 1.962558 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3845797 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005945 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1628537053 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761643882 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638542497 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646797787 # Type of FU issued +system.cpu.iq.rate 1.963143 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3840966 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005938 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1628229284 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761462946 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638497717 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650719248 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650638733 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30433842 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30397502 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23990041 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 126515 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11992 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10415263 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23968825 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 126112 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12134 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10400833 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12768 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 35443 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12732 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 35377 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11044631 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 670742 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 80165 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 682151912 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 669326 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172942863 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80636505 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3402 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 21938 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3947 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11992 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1313002 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1582154 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2895156 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642705109 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 164002272 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4168362 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10998322 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 671065 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 80095 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 681994740 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 717531 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172921644 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80622072 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1925 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 21947 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3973 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12134 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1389665 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1520287 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2909952 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642597340 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163964037 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4200447 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 66073 # number of nop insts executed -system.cpu.iew.exec_refs 239994615 # number of memory reference insts executed -system.cpu.iew.exec_branches 74670654 # Number of branches executed -system.cpu.iew.exec_stores 75992343 # Number of stores executed -system.cpu.iew.exec_rate 1.949911 # Inst execution rate -system.cpu.iew.wb_sent 640039570 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638542513 # cumulative count of insts written-back -system.cpu.iew.wb_producers 419139421 # num instructions producing a value -system.cpu.iew.wb_consumers 650719166 # num instructions consuming a value +system.cpu.iew.exec_nop 3173 # number of nop insts executed +system.cpu.iew.exec_refs 239958391 # number of memory reference insts executed +system.cpu.iew.exec_branches 74720339 # Number of branches executed +system.cpu.iew.exec_stores 75994354 # Number of stores executed +system.cpu.iew.exec_rate 1.950394 # Inst execution rate +system.cpu.iew.wb_sent 639963641 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638497733 # cumulative count of insts written-back +system.cpu.iew.wb_producers 419111890 # num instructions producing a value +system.cpu.iew.wb_consumers 650388459 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937282 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644117 # average fanout of values written-back +system.cpu.iew.wb_rate 1.937951 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644402 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 79800581 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2933 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2421751 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 318472465 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.891407 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.233429 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 79643282 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2930 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2409350 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 318381732 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.891946 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.233867 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93877002 29.48% 29.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104551194 32.83% 62.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43288621 13.59% 75.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8793504 2.76% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 26039044 8.18% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12759663 4.01% 90.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7570973 2.38% 93.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1268002 0.40% 93.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20324462 6.38% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93812247 29.47% 29.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104551370 32.84% 62.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43266938 13.59% 75.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8778657 2.76% 78.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 26036096 8.18% 86.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12762730 4.01% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7569326 2.38% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1269179 0.40% 93.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20335189 6.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 318472465 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570052781 # Number of instructions committed -system.cpu.commit.committedOps 602360987 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 318381732 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570052766 # Number of instructions committed +system.cpu.commit.committedOps 602360972 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219174064 # Number of memory references committed -system.cpu.commit.loads 148952822 # Number of loads committed +system.cpu.commit.refs 219174058 # Number of memory references committed +system.cpu.commit.loads 148952819 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828829 # Number of branches committed +system.cpu.commit.branches 70892750 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533523547 # Number of committed integer instructions. +system.cpu.commit.int_insts 533523535 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20324462 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20335189 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 980308959 # The number of ROB reads -system.cpu.rob.rob_writes 1375400190 # The number of ROB writes -system.cpu.timesIdled 6717 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 90301 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570052730 # Number of Instructions Simulated -system.cpu.committedOps 602360936 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570052730 # Number of Instructions Simulated -system.cpu.cpi 0.578205 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.578205 # CPI: Total CPI of All Threads -system.cpu.ipc 1.729490 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.729490 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210477235 # number of integer regfile reads -system.cpu.int_regfile_writes 664240650 # number of integer regfile writes +system.cpu.rob.rob_reads 980050185 # The number of ROB reads +system.cpu.rob.rob_writes 1375038514 # The number of ROB writes +system.cpu.timesIdled 6612 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 90491 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570052715 # Number of Instructions Simulated +system.cpu.committedOps 602360921 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570052715 # Number of Instructions Simulated +system.cpu.cpi 0.577965 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.577965 # CPI: Total CPI of All Threads +system.cpu.ipc 1.730208 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.730208 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210034168 # number of integer regfile reads +system.cpu.int_regfile_writes 664124835 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 905174301 # number of misc regfile reads -system.cpu.misc_regfile_writes 3114 # number of misc regfile writes -system.cpu.icache.replacements 52 # number of replacements -system.cpu.icache.tagsinuse 687.184912 # Cycle average of tags in use -system.cpu.icache.total_refs 67496491 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 806 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 83742.544665 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 904851739 # number of misc regfile reads +system.cpu.misc_regfile_writes 3108 # number of misc regfile writes +system.cpu.icache.replacements 59 # number of replacements +system.cpu.icache.tagsinuse 698.555131 # Cycle average of tags in use +system.cpu.icache.total_refs 67409471 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 828 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 81412.404589 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 687.184912 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.335540 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.335540 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67496491 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67496491 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67496491 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67496491 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67496491 # number of overall hits -system.cpu.icache.overall_hits::total 67496491 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1084 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1084 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1084 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1084 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1084 # number of overall misses -system.cpu.icache.overall_misses::total 1084 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38240500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38240500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38240500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38240500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 38240500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 38240500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67497575 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67497575 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67497575 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67497575 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67497575 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67497575 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 698.555131 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.341091 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.341091 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67409471 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67409471 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67409471 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67409471 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67409471 # number of overall hits +system.cpu.icache.overall_hits::total 67409471 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1108 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1108 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1108 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1108 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1108 # number of overall misses +system.cpu.icache.overall_misses::total 1108 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 38972000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38972000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 38972000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38972000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 38972000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38972000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67410579 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67410579 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67410579 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67410579 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67410579 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67410579 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35277.214022 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35277.214022 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35277.214022 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35277.214022 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35277.214022 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35277.214022 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35173.285199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35173.285199 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35173.285199 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35173.285199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35173.285199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35173.285199 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,146 +398,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1553 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1553 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201726220 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201726220 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201726220 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201726220 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002278 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002278 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.036905 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.036905 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012331 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012331 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014194 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014194 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014194 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014194 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12258.808478 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12258.808478 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15792.333580 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 15792.333580 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 11404.761905 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 11404.761905 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15420.458071 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15420.458071 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15420.458071 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15420.458071 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30335630 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.036889 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.036889 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012739 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012739 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014188 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014188 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014188 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014188 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12251.183883 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12251.183883 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15795.642625 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15795.642625 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10886.363636 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10886.363636 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15422.463033 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15422.463033 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15422.463033 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15422.463033 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30346130 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 47000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2896 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10475.010359 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10478.636050 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 23500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 420959 # number of writebacks -system.cpu.dcache.writebacks::total 420959 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104056 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104056 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2314755 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2314755 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 21 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 21 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2418811 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2418811 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2418811 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2418811 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197273 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197273 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4299529629 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4299529629 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4299529629 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 420958 # number of writebacks +system.cpu.dcache.writebacks::total 420958 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104059 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104059 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2313654 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2313654 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2417713 # 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mshr miss rate for WriteReq accesses @@ -546,161 +546,161 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002203 system.cpu.dcache.demand_mshr_miss_rate::total 0.002203 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002203 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002203 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7839.511743 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7839.511743 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11140.584865 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11140.584865 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9675.170412 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 9675.170412 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031534 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089787 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089787 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.915459 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062281 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063868 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.915459 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062281 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063868 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32802.110818 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31962.652578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32064.510965 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37799.823561 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37799.823561 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32802.110818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36642.217104 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36539.853882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32802.110818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36642.217104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36539.853882 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini index ad449ce69..c50a349bb 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,8 +68,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -84,8 +84,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -95,12 +95,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -117,14 +117,15 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout index 2afc8e322..21bacf71f 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:38:20 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:41:05 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index d2a90d0bb..b109fcbb9 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.301191 # Nu sim_ticks 301191365000 # Number of ticks simulated final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3330708 # Simulator instruction rate (inst/s) -host_op_rate 3519478 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1759805795 # Simulator tick rate (ticks/s) -host_mem_usage 224176 # Number of bytes of host memory used -host_seconds 171.15 # Real time elapsed on the host +host_inst_rate 2514683 # Simulator instruction rate (inst/s) +host_op_rate 2657205 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1328652667 # Simulator tick rate (ticks/s) +host_mem_usage 218896 # Number of bytes of host memory used +host_seconds 226.69 # Real time elapsed on the host sim_insts 570051636 # Number of instructions simulated sim_ops 602359842 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory @@ -84,7 +84,7 @@ system.cpu.committedOps 602359842 # Nu system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1995305 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67017094 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 67050634 # number of instructions that are conditional controls system.cpu.num_int_insts 533522631 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 2770242967 # number of times the integer registers were read diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini index a10276e4b..e485b6133 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,16 +61,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -89,8 +91,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -99,16 +101,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -130,8 +134,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -140,16 +144,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=2097152 subblock_size=0 system=system @@ -176,12 +182,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -199,13 +205,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout index 149dba9b1..2c7022400 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:28:47 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:37:42 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 79ebe936b..7bce23d96 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.795271 # Nu sim_ticks 795270546000 # Number of ticks simulated final_tick 795270546000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 873454 # Simulator instruction rate (inst/s) -host_op_rate 922399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1221783566 # Simulator tick rate (ticks/s) -host_mem_usage 232680 # Number of bytes of host memory used -host_seconds 650.91 # Real time elapsed on the host +host_inst_rate 1274959 # Simulator instruction rate (inst/s) +host_op_rate 1346403 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1783406999 # Simulator tick rate (ticks/s) +host_mem_usage 227740 # Number of bytes of host memory used +host_seconds 445.93 # Real time elapsed on the host sim_insts 568539335 # Number of instructions simulated sim_ops 600398272 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory @@ -85,7 +85,7 @@ system.cpu.committedOps 600398272 # Nu system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1995305 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67017094 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 67050634 # number of instructions that are conditional controls system.cpu.num_int_insts 533522631 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 3212467067 # number of times the integer registers were read |