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-rw-r--r--tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini8
-rwxr-xr-xtests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr1
-rwxr-xr-xtests/long/se/00.gzip/ref/x86/linux/o3-timing/simout10
-rw-r--r--tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt1166
-rw-r--r--tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout6
-rw-r--r--tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt62
-rw-r--r--tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini45
-rwxr-xr-xtests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/se/00.gzip/ref/x86/linux/simple-timing/simout6
-rw-r--r--tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt74
12 files changed, 695 insertions, 697 deletions
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
index f6f519501..e5a53f4f2 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
@@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -78,7 +78,6 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
-isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -465,9 +464,6 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
-[system.cpu.isa]
-type=X86ISA
-
[system.cpu.itb]
type=X86TLB
children=walker
@@ -528,7 +524,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
index ac4ad20a5..f5691fd64 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
index 48eb9aa0f..22f96a7fe 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:14:29
-gem5 started Oct 30 2012 16:17:19
-gem5 executing on u200540-lin
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:35:30
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -40,4 +42,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 607235830000 because target called exit()
+Exiting @ tick 607445544000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
index 74f46e926..63873cca1 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -1,63 +1,63 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.607236 # Number of seconds simulated
-sim_ticks 607235830000 # Number of ticks simulated
-final_tick 607235830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.607446 # Number of seconds simulated
+sim_ticks 607445544000 # Number of ticks simulated
+final_tick 607445544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 71722 # Simulator instruction rate (inst/s)
-host_op_rate 132152 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 49489751 # Simulator tick rate (ticks/s)
-host_mem_usage 226812 # Number of bytes of host memory used
-host_seconds 12269.93 # Real time elapsed on the host
+host_inst_rate 57635 # Simulator instruction rate (inst/s)
+host_op_rate 106195 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 39782943 # Simulator tick rate (ticks/s)
+host_mem_usage 279268 # Number of bytes of host memory used
+host_seconds 15268.99 # Real time elapsed on the host
sim_insts 880025277 # Number of instructions simulated
-sim_ops 1621493925 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 57472 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1693120 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1750592 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 57472 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 57472 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory
-system.physmem.bytes_written::total 162112 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 898 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 26455 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 27353 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 94645 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2788241 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2882887 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 94645 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 94645 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 266967 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 266967 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 266967 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 94645 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2788241 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3149854 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 27355 # Total number of read requests seen
-system.physmem.writeReqs 2533 # Total number of write requests seen
-system.physmem.cpureqs 29888 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1750592 # Total number of bytes read from memory
-system.physmem.bytesWritten 162112 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1750592 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize()
+sim_ops 1621493926 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 57728 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1693184 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1750912 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 57728 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 57728 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 162176 # Number of bytes written to this memory
+system.physmem.bytes_written::total 162176 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 902 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 26456 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 27358 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 2534 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2534 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 95034 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2787384 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2882418 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 95034 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 95034 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 266980 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 266980 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 266980 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 95034 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2787384 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3149398 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 27359 # Total number of read requests seen
+system.physmem.writeReqs 2534 # Total number of write requests seen
+system.physmem.cpureqs 29893 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1750912 # Total number of bytes read from memory
+system.physmem.bytesWritten 162176 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1750912 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 162176 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1747 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 1689 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1686 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 1672 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1754 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1754 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1753 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1755 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1779 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1777 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 1808 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1776 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1809 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 1712 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 1664 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 1638 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 1660 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1666 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1668 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1691 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1661 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1667 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1672 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1692 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 162 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis
@@ -72,19 +72,19 @@ system.physmem.perBankWrReqs::9 158 # Tr
system.physmem.perBankWrReqs::10 154 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 154 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 154 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 156 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 156 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 607235813000 # Total gap between requests
+system.physmem.totGap 607445529000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 27355 # Categorize read packet sizes
+system.physmem.readPktSize::6 27359 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 2533 # categorize write packet sizes
+system.physmem.writePktSize::6 2534 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -105,9 +105,9 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 26898 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 336 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 95 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 26894 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 94 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -141,7 +141,7 @@ system.physmem.rdQLenPdf::32 0 # Wh
system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see
@@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 67414668 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 820820668 # Sum of mem lat for all requests
-system.physmem.totBusLat 109420000 # Total cycles spent in databus access
-system.physmem.totBankLat 643986000 # Total cycles spent in bank access
-system.physmem.avgQLat 2464.44 # Average queueing delay per request
-system.physmem.avgBankLat 23541.80 # Average bank access latency per request
+system.physmem.totQLat 68456169 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 822256169 # Sum of mem lat for all requests
+system.physmem.totBusLat 109436000 # Total cycles spent in databus access
+system.physmem.totBankLat 644364000 # Total cycles spent in bank access
+system.physmem.avgQLat 2502.14 # Average queueing delay per request
+system.physmem.avgBankLat 23552.18 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 30006.24 # Average memory access latency
+system.physmem.avgMemAccLat 30054.32 # Average memory access latency
system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s
@@ -186,593 +186,451 @@ system.physmem.avgConsumedWrBW 0.27 # Av
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 4.32 # Average write queue length over time
-system.physmem.readRowHits 17706 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1086 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 64.73 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 42.87 # Row buffer hit rate for writes
-system.physmem.avgGap 20317044.06 # Average gap between requests
+system.physmem.avgWrQLen 6.29 # Average write queue length over time
+system.physmem.readRowHits 17697 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1084 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 64.68 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 42.78 # Row buffer hit rate for writes
+system.physmem.avgGap 20320661.33 # Average gap between requests
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 1214471661 # number of cpu cycles simulated
+system.cpu.numCycles 1214891089 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 158566645 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 158566645 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 26386333 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 83466743 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 83279512 # Number of BTB hits
+system.cpu.BPredUnit.lookups 158385701 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 158385701 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 26390414 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 84292336 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 84079165 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 179036467 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1457944289 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 158566645 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 83279512 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 399021545 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 88092537 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 574509498 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 50 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 341 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 186960601 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10940939 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1214117357 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.059847 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.253407 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 179135724 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1458430747 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 158385701 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 84079165 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 399080479 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 88232216 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 574634439 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 381 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 187842502 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 11743850 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1214538068 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.059666 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.253312 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 822311931 67.73% 67.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 26973525 2.22% 69.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 13085420 1.08% 71.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 20645432 1.70% 72.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 26636403 2.19% 74.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 18254688 1.50% 76.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 31306986 2.58% 79.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 39069186 3.22% 82.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 215833786 17.78% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 822675210 67.74% 67.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 26883309 2.21% 69.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 13192065 1.09% 71.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 20566257 1.69% 72.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 26639433 2.19% 74.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 18282936 1.51% 76.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 31338155 2.58% 79.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 39109954 3.22% 82.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 215850749 17.77% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1214117357 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.130564 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.200476 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 288149545 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 497851788 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 274001581 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 92564987 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 61549456 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2343342483 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 61549456 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 336776305 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 124136399 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2472 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 303957244 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 387695481 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2247540252 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 338 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 242690737 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 120190709 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2617793255 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5721514338 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 5721508630 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 5708 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1886895257 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 730897998 # Number of HB maps that are undone due to squashing
+system.cpu.fetch.rateDist::total 1214538068 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.130370 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.200462 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 288247470 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 497953946 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 274080522 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 92569137 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 61686993 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2343830219 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 61686993 # Number of cycles rename is squashing
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+system.cpu.rename.BlockCycles 124143934 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2487 # count of cycles rename stalled for serializing inst
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+system.cpu.rename.UnblockCycles 387759824 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2248180627 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 354 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 242798221 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 120202889 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2618438730 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5723603734 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5723598334 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 5400 # Number of floating rename lookups
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+system.cpu.rename.UndoneMaps 731543472 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 87 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 731315186 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 531685334 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 219218078 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 341957322 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 144669482 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1993566712 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1783999852 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 259167 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 371673921 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 759176081 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 236 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1214117357 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.469380 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.421908 # Number of insts issued each cycle
+system.cpu.rename.skidInsts 731379517 # count of insts added to the skid buffer
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+system.cpu.iq.iqInstsAdded 1994506429 # Number of instructions added to the IQ (excludes non-spec)
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+system.cpu.iq.iqSquashedInstsExamined 372613756 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::2 234218772 19.29% 78.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 141579875 11.66% 90.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 60576135 4.99% 95.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 39770363 3.28% 98.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 11069235 0.91% 99.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 2042198 0.17% 99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 607441 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 360345167 29.67% 29.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 364336445 30.00% 59.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 234287346 19.29% 78.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 141446603 11.65% 90.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 60702765 5.00% 95.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 39742301 3.27% 98.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 11032116 0.91% 99.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 2048046 0.17% 99.95% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::total 1214117357 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1214538068 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 448044 15.51% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 15.51% # attempts to use FU when none available
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-system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2239769 77.53% 93.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 201121 6.96% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 437572 15.09% 15.09% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 15.09% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.09% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2259609 77.90% 92.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 203424 7.01% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 46812236 2.62% 2.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1065749303 59.74% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 478900937 26.84% 89.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 192537376 10.79% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 46812462 2.62% 2.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1065847679 59.74% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 478866421 26.84% 89.21% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 192554199 10.79% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1783999852 # Type of FU issued
-system.cpu.iq.rate 1.468951 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2888934 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001619 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4785264711 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2365417546 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1724692001 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 451 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1804 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 116 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1740076331 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 219 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 209988104 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1784080761 # Type of FU issued
+system.cpu.iq.rate 1.468511 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2900605 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001626 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4785843295 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2367295034 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1724820361 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 350 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1704 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1740168733 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 171 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 209903028 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 112643213 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 39222 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 182717 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 31032021 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 113016880 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 39297 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 180469 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 31115283 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2338 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 61 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2481 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 68 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 61549456 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1140639 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 111456 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1993566998 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 62891461 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 531685334 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 219218078 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 82 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 54713 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2863 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 182717 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 2045566 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 24470672 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 26516238 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1766182455 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 474610807 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 17817397 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 61686993 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1142263 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 110648 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1994506717 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 63004482 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 532059001 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 219301341 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 80 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 54039 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 2855 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 180469 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 2045569 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 24474359 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 26519928 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1766291934 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 474573600 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 17788827 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 666317556 # number of memory reference insts executed
-system.cpu.iew.exec_branches 110350315 # Number of branches executed
-system.cpu.iew.exec_stores 191706749 # Number of stores executed
-system.cpu.iew.exec_rate 1.454281 # Inst execution rate
-system.cpu.iew.wb_sent 1725793430 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1724692117 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1267138729 # num instructions producing a value
-system.cpu.iew.wb_consumers 1828924593 # num instructions consuming a value
+system.cpu.iew.exec_refs 666299746 # number of memory reference insts executed
+system.cpu.iew.exec_branches 110359604 # Number of branches executed
+system.cpu.iew.exec_stores 191726146 # Number of stores executed
+system.cpu.iew.exec_rate 1.453869 # Inst execution rate
+system.cpu.iew.wb_sent 1725940615 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1724820453 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1267203875 # num instructions producing a value
+system.cpu.iew.wb_consumers 1829107615 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.420117 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.692833 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.419733 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.692799 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 372074312 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 26386383 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1152567901 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.406853 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.830346 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 373014217 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 26390469 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1152851075 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.406508 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.830012 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 417955350 36.26% 36.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 415054079 36.01% 72.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 86939331 7.54% 79.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 122127082 10.60% 90.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 24184880 2.10% 92.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 25402622 2.20% 94.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 16383099 1.42% 96.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 12042950 1.04% 97.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 32478508 2.82% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 418199685 36.28% 36.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 415017727 36.00% 72.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 87014149 7.55% 79.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 122172880 10.60% 90.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 24164674 2.10% 92.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 25337442 2.20% 94.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 16460362 1.43% 96.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 12052065 1.05% 97.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 32432091 2.81% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1152567901 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1152851075 # Number of insts commited each cycle
system.cpu.commit.committedInsts 880025277 # Number of instructions committed
-system.cpu.commit.committedOps 1621493925 # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps 1621493926 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 607228178 # Number of memory references committed
+system.cpu.commit.refs 607228179 # Number of memory references committed
system.cpu.commit.loads 419042121 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 107161574 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1621354435 # Number of committed integer instructions.
+system.cpu.commit.int_insts 1621354437 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 32478508 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 32432091 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3113657630 # The number of ROB reads
-system.cpu.rob.rob_writes 4048721682 # The number of ROB writes
-system.cpu.timesIdled 59087 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 354304 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3114927127 # The number of ROB reads
+system.cpu.rob.rob_writes 4050738571 # The number of ROB writes
+system.cpu.timesIdled 58873 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 353021 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 880025277 # Number of Instructions Simulated
-system.cpu.committedOps 1621493925 # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps 1621493926 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated
-system.cpu.cpi 1.380042 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.380042 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.724616 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.724616 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3542913524 # number of integer regfile reads
-system.cpu.int_regfile_writes 1974599259 # number of integer regfile writes
-system.cpu.fp_regfile_reads 116 # number of floating regfile reads
-system.cpu.misc_regfile_reads 910763104 # number of misc regfile reads
-system.cpu.icache.replacements 26 # number of replacements
-system.cpu.icache.tagsinuse 814.074374 # Cycle average of tags in use
-system.cpu.icache.total_refs 186959214 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 915 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 204327.009836 # Average number of references to valid blocks.
+system.cpu.cpi 1.380518 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.380518 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.724366 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.724366 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3542903494 # number of integer regfile reads
+system.cpu.int_regfile_writes 1974699145 # number of integer regfile writes
+system.cpu.fp_regfile_reads 92 # number of floating regfile reads
+system.cpu.misc_regfile_reads 910807256 # number of misc regfile reads
+system.cpu.icache.replacements 17 # number of replacements
+system.cpu.icache.tagsinuse 815.551450 # Cycle average of tags in use
+system.cpu.icache.total_refs 187841113 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 206418.805495 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 814.074374 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.397497 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.397497 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 186959220 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 186959220 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 186959220 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 186959220 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 186959220 # number of overall hits
-system.cpu.icache.overall_hits::total 186959220 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1381 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1381 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1381 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1381 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1381 # number of overall misses
-system.cpu.icache.overall_misses::total 1381 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 63796500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 63796500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 63796500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 63796500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 63796500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 63796500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 186960601 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 186960601 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 186960601 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 186960601 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 186960601 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 186960601 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 815.551450 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.398218 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.398218 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 187841119 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 187841119 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 187841119 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 187841119 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 187841119 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1383 # number of ReadReq misses
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+system.cpu.icache.demand_misses::total 1383 # number of demand (read+write) misses
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+system.cpu.icache.overall_misses::total 1383 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 64282500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 64282500 # number of ReadReq miss cycles
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+system.cpu.icache.overall_miss_latency::total 64282500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 187842502 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::total 187842502 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46195.872556 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 46195.872556 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 46195.872556 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 46195.872556 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 46195.872556 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 46195.872556 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 249 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46480.477223 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 46480.477223 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 46480.477223 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 46480.477223 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 46480.477223 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 46480.477223 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 203 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 49.800000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 40.600000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 459 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 459 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 459 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 459 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 459 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 922 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 922 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 922 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 922 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 922 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 922 # number of overall MSHR misses
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991209 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058778 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.060659 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991209 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058778 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.060659 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37430.080931 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58702.949123 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55189.926950 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36381.974791 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36381.974791 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37430.080931 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40229.109498 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40136.828210 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37430.080931 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40229.109498 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40136.828210 # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
index 065406dee..6f8b69a5a 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -68,13 +68,13 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -91,7 +91,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[3]
@@ -129,9 +129,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
index ac4ad20a5..f5691fd64 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
index 128fee1f8..c175f0374 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:29:07
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:35:29
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@@ -41,4 +41,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 963992671000 because target called exit()
+Exiting @ tick 963992671500 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index bf8fc96e2..5647e6e6c 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.963993 # Number of seconds simulated
-sim_ticks 963992671000 # Number of ticks simulated
-final_tick 963992671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 963992671500 # Number of ticks simulated
+final_tick 963992671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 939514 # Simulator instruction rate (inst/s)
-host_op_rate 1731105 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1029157174 # Simulator tick rate (ticks/s)
-host_mem_usage 266280 # Number of bytes of host memory used
-host_seconds 936.68 # Real time elapsed on the host
+host_inst_rate 908989 # Simulator instruction rate (inst/s)
+host_op_rate 1674860 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 995719480 # Simulator tick rate (ticks/s)
+host_mem_usage 267620 # Number of bytes of host memory used
+host_seconds 968.14 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
-sim_ops 1621493926 # Number of ops (including micro ops) simulated
+sim_ops 1621493927 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1842452909 # Number of bytes read from this memory
system.physmem.bytes_read::total 11334586469 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 9492133560 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 9492133560 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 864451000 # Number of bytes written to this memory
-system.physmem.bytes_written::total 864451000 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 864451002 # Number of bytes written to this memory
+system.physmem.bytes_written::total 864451002 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1186516695 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 419042121 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1605558816 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 188186057 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 188186057 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 9846686438 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1911272735 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 11757959173 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 9846686438 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 9846686438 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 896740220 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 896740220 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 9846686438 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2808012955 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 12654699393 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::cpu.data 188186058 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 188186058 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 9846686433 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1911272734 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 11757959167 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 9846686433 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 9846686433 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 896740222 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 896740222 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 9846686433 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2808012956 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 12654699389 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 1927985343 # number of cpu cycles simulated
+system.cpu.numCycles 1927985344 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 880025278 # Number of instructions committed
-system.cpu.committedOps 1621493926 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1621354436 # Number of integer alu accesses
+system.cpu.committedOps 1621493927 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1621354438 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1621354436 # number of integer instructions
+system.cpu.num_int_insts 1621354438 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 4204103507 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1886895257 # number of times the integer registers were written
+system.cpu.num_int_register_reads 4204103512 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1886895258 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 607228178 # number of memory refs
+system.cpu.num_mem_refs 607228179 # number of memory refs
system.cpu.num_load_insts 419042121 # Number of load instructions
-system.cpu.num_store_insts 188186057 # Number of store instructions
+system.cpu.num_store_insts 188186058 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 1927985343 # Number of busy cycles
+system.cpu.num_busy_cycles 1927985344 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
index fe83ea738..156174801 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -61,21 +61,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=262144
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -90,7 +91,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[3]
@@ -99,21 +100,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=131072
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -122,7 +124,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -139,30 +141,31 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -172,10 +175,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -213,9 +216,9 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
index ac4ad20a5..f5691fd64 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
index 02ca976d3..ad62c8d74 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timin
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:43:43
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:35:29
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@@ -41,4 +41,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 1801979679000 because target called exit()
+Exiting @ tick 1800193397000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
index ea680ba75..87bad38e6 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.800193 # Number of seconds simulated
-sim_ticks 1800193396000 # Number of ticks simulated
-final_tick 1800193396000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 1800193397000 # Number of ticks simulated
+final_tick 1800193397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 332254 # Simulator instruction rate (inst/s)
-host_op_rate 612196 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 679663607 # Simulator tick rate (ticks/s)
-host_mem_usage 227800 # Number of bytes of host memory used
-host_seconds 2648.65 # Real time elapsed on the host
+host_inst_rate 477976 # Simulator instruction rate (inst/s)
+host_op_rate 880696 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 977754272 # Simulator tick rate (ticks/s)
+host_mem_usage 276196 # Number of bytes of host memory used
+host_seconds 1841.15 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
-sim_ops 1621493926 # Number of ops (including micro ops) simulated
+sim_ops 1621493927 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory
system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory
@@ -35,26 +35,26 @@ system.physmem.bw_total::cpu.inst 25668 # To
system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 3600386792 # number of cpu cycles simulated
+system.cpu.numCycles 3600386794 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 880025278 # Number of instructions committed
-system.cpu.committedOps 1621493926 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1621354436 # Number of integer alu accesses
+system.cpu.committedOps 1621493927 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1621354438 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1621354436 # number of integer instructions
+system.cpu.num_int_insts 1621354438 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 4204103507 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1886895257 # number of times the integer registers were written
+system.cpu.num_int_register_reads 4204103512 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1886895258 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 607228178 # number of memory refs
+system.cpu.num_mem_refs 607228179 # number of memory refs
system.cpu.num_load_insts 419042121 # Number of load instructions
-system.cpu.num_store_insts 188186057 # Number of store instructions
+system.cpu.num_store_insts 188186058 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 3600386792 # Number of busy cycles
+system.cpu.num_busy_cycles 3600386794 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 4 # number of replacements
@@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083
system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 437952 # number of replacements
-system.cpu.dcache.tagsinuse 4094.905744 # Cycle average of tags in use
-system.cpu.dcache.total_refs 606786130 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4094.905742 # Cycle average of tags in use
+system.cpu.dcache.total_refs 606786131 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 1372.670230 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 771786000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.905744 # Average occupied blocks per requestor
+system.cpu.dcache.avg_refs 1372.670233 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 771787000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4094.905742 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 187941335 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 606786130 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 606786130 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 606786130 # number of overall hits
-system.cpu.dcache.overall_hits::total 606786130 # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 606786131 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 606786131 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 606786131 # number of overall hits
+system.cpu.dcache.overall_hits::total 606786131 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses
@@ -170,12 +170,12 @@ system.cpu.dcache.overall_miss_latency::cpu.data 6851581000
system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 607228178 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 607228178 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 607228178 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 607228178 # number of overall (read+write) accesses
+system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 607228179 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 607228179 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 607228179 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 607228179 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses
@@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2532 # number of replacements
-system.cpu.l2cache.tagsinuse 22211.029339 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 22211.029327 # Cycle average of tags in use
system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.788687 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21021.301366 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 21021.301355 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 643.199216 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 546.528757 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 546.528756 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.641519 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.019629 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.016679 # Average percentage of cache occupancy