diff options
Diffstat (limited to 'tests/long/se/00.gzip')
9 files changed, 1020 insertions, 1042 deletions
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index 46194a700..358021124 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,7 +522,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/gem5/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 5bcc38f1b..afe1d756a 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 18:59:47 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:34:09 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 8b98b78ac..650fe9ea1 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.164568 # Nu sim_ticks 164568389500 # Number of ticks simulated final_tick 164568389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195675 # Simulator instruction rate (inst/s) -host_op_rate 206765 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56489453 # Simulator tick rate (ticks/s) -host_mem_usage 277972 # Number of bytes of host memory used -host_seconds 2913.26 # Real time elapsed on the host +host_inst_rate 61098 # Simulator instruction rate (inst/s) +host_op_rate 64561 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17638362 # Simulator tick rate (ticks/s) +host_mem_usage 233000 # Number of bytes of host memory used +host_seconds 9330.14 # Real time elapsed on the host sim_insts 570052720 # Number of instructions simulated sim_ops 602360926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 47104 # Number of bytes read from this memory @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 164 # Tr system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 164568371500 # Total gap between requests +system.physmem.totGap 164568372500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 953340995 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1657962995 # Sum of mem lat for all requests +system.physmem.totQLat 953339495 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1657961495 # Sum of mem lat for all requests system.physmem.totBusLat 109328000 # Total cycles spent in databus access system.physmem.totBankLat 595294000 # Total cycles spent in bank access -system.physmem.avgQLat 34880.03 # Average queueing delay per request +system.physmem.avgQLat 34879.98 # Average queueing delay per request system.physmem.avgBankLat 21780.11 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 60660.14 # Average memory access latency +system.physmem.avgMemAccLat 60660.09 # Average memory access latency system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s @@ -191,7 +191,7 @@ system.physmem.readRowHits 17765 # Nu system.physmem.writeRowHits 1091 # Number of row buffer hits during writes system.physmem.readRowHitRate 65.00 # Row buffer hit rate for reads system.physmem.writeRowHitRate 43.00 # Row buffer hit rate for writes -system.physmem.avgGap 5509671.28 # Average gap between requests +system.physmem.avgGap 5509671.31 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -246,23 +246,23 @@ system.cpu.BPredUnit.BTBHits 46871026 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 1427560 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 1061 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68501011 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 68501012 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 666829693 # Number of instructions fetch has processed system.cpu.fetch.Branches 85146783 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 48298586 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 129620938 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 13095502 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119329475 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.BlockedCycles 119329476 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 302 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 67084220 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 755001 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 328178874 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 67084221 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 755002 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 328178875 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.165282 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.193965 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 198558185 60.50% 60.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198558186 60.50% 60.50% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 20911289 6.37% 66.87% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 4967188 1.51% 68.39% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 14345258 4.37% 72.76% # Number of instructions fetched each cycle (Total) @@ -274,11 +274,11 @@ system.cpu.fetch.rateDist::8 60883054 18.55% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 328178874 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 328178875 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.258697 # Number of branch fetches per cycle system.cpu.fetch.rate 2.025996 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 92947684 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96199178 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 96199179 # Number of cycles decode is blocked system.cpu.decode.RunCycles 107899614 # Number of cycles decode is running system.cpu.decode.UnblockCycles 20406722 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 10725676 # Number of cycles decode is squashing @@ -290,19 +290,19 @@ system.cpu.rename.SquashCycles 10725676 # Nu system.cpu.rename.IdleCycles 107135136 # Number of cycles rename is idle system.cpu.rename.BlockCycles 14450172 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 44143 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114043084 # Number of cycles rename is running +system.cpu.rename.RunCycles 114043085 # Number of cycles rename is running system.cpu.rename.UnblockCycles 81780663 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 694816427 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 694816428 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 59310091 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 20339427 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 721301804 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3230529001 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3230528873 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 721301805 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3230529005 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3230528877 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 93882615 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 93882616 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 2064 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 2020 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 170675831 # count of insts added to the skid buffer @@ -317,11 +317,11 @@ system.cpu.iq.iqSquashedInstsIssued 1370428 # Nu system.cpu.iq.iqSquashedInstsExamined 77447824 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 193234107 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 328178874 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 328178875 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.967223 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.725262 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68164683 20.77% 20.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68164684 20.77% 20.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 85309693 25.99% 46.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 75934594 23.14% 69.90% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 40814180 12.44% 82.34% # Number of insts issued each cycle @@ -333,7 +333,7 @@ system.cpu.iq.issued_per_cycle::8 2116297 0.64% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 328178874 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328178875 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 216945 5.75% 5.75% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available @@ -406,7 +406,7 @@ system.cpu.iq.FU_type_0::total 645601186 # Ty system.cpu.iq.rate 1.961498 # Inst issue rate system.cpu.iq.fu_busy_cnt 3772110 # FU busy when requested system.cpu.iq.fu_busy_rate 0.005843 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624523748 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 1624523749 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 757451010 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 637563052 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads @@ -429,7 +429,7 @@ system.cpu.iew.iewSquashCycles 10725676 # Nu system.cpu.iew.iewBlockCycles 798492 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 92069 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 679994152 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 690727 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 690728 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 172202980 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 80458110 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 1965 # Number of dispatched non-speculative instructions @@ -491,7 +491,7 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 977035801 # The number of ROB reads system.cpu.rob.rob_writes 1370761733 # The number of ROB writes system.cpu.timesIdled 41126 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 957906 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 957905 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 570052720 # Number of Instructions Simulated system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated @@ -519,36 +519,36 @@ system.cpu.icache.demand_hits::cpu.inst 67083066 # nu system.cpu.icache.demand_hits::total 67083066 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 67083066 # number of overall hits system.cpu.icache.overall_hits::total 67083066 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses -system.cpu.icache.overall_misses::total 1154 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51351999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51351999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51351999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51351999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51351999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51351999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67084220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67084220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67084220 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67084220 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67084220 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67084220 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 1155 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1155 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1155 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1155 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1155 # number of overall misses +system.cpu.icache.overall_misses::total 1155 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51421999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51421999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51421999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51421999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51421999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51421999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67084221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67084221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67084221 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67084221 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67084221 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67084221 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44499.132582 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44499.132582 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44499.132582 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44499.132582 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44499.132582 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44499.132582 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44521.211255 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44521.211255 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44521.211255 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44521.211255 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44521.211255 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44521.211255 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked @@ -557,171 +557,45 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 38.428571 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 334 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 334 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 334 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 334 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 334 # 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average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47143.901220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47143.901220 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47142.681707 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47142.681707 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47142.681707 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47142.681707 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47142.681707 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47142.681707 # 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number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3714801 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3714801 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3714801 # number of overall misses -system.cpu.dcache.overall_misses::total 3714801 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5159651000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5159651000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 40250551202 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 40250551202 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 339000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 339000 # 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number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201277526 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201277526 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201277526 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201277526 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002594 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002594 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048587 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.048587 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012956 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012956 # 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average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12224.127807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12224.127807 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 131795 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5078 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.954116 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421636 # number of writebacks -system.cpu.dcache.writebacks::total 421636 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144398 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 144398 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3125625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3125625 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3270023 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3270023 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3270023 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3270023 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197619 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197619 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247159 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247159 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444778 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444778 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444778 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444778 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875780500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875780500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4060483756 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4060483756 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6936264256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6936264256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6936264256 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001499 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001499 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.145796 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.145796 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.629975 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.629975 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2559 # number of replacements -system.cpu.l2cache.tagsinuse 22365.188889 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22365.188888 # Cycle average of tags in use system.cpu.l2cache.total_refs 517231 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 24170 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 21.399710 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 20763.498620 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 646.825200 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 646.825199 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 954.865069 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.633652 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.019740 # Average percentage of cache occupancy @@ -751,17 +625,17 @@ system.cpu.l2cache.demand_misses::total 27343 # nu system.cpu.l2cache.overall_misses::cpu.inst 739 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 26604 # number of overall misses system.cpu.l2cache.overall_misses::total 27343 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37001500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 728778000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 765779500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1545376000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1545376000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 37001500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37000500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 728777500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 765778000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1545376500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1545376500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 37000500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 2274154000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2311155500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 37001500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 2311154500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37000500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 2274154000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2311155500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2311154500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 820 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 197619 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 198439 # number of ReadReq accesses(hits+misses) @@ -786,17 +660,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.061362 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.901220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.059814 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.061362 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50069.688769 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 151387.203988 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 137903.745723 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70921.340064 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70921.340064 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50069.688769 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50068.335589 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 151387.100125 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 137903.475599 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70921.363011 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70921.363011 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50068.335589 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85481.656894 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84524.576674 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50069.688769 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84524.540102 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50068.335589 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85481.656894 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84524.576674 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84524.540102 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -827,17 +701,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27332 system.cpu.l2cache.overall_mshr_misses::cpu.inst 736 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26596 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27332 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27342673 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668140562 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695483235 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1273790796 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1273790796 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27342673 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1941931358 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1969274031 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27342673 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1941931358 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1969274031 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27342173 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668139562 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 695481735 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1273791296 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1273791296 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27342173 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1941930858 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1969273031 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27342173 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1941930858 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1969273031 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024320 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027928 # mshr miss rate for ReadReq accesses @@ -849,17 +723,143 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.061338 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.897561 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059796 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.061338 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37150.370924 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139022.172701 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125493.185673 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58457.585865 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.585865 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37150.370924 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73015.918108 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72050.125531 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37150.370924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73015.918108 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72050.125531 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37149.691576 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 139021.964628 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125492.915013 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58457.608811 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58457.608811 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37149.691576 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73015.899308 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72050.088943 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37149.691576 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73015.899308 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72050.088943 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 440681 # number of replacements +system.cpu.dcache.tagsinuse 4091.500678 # Cycle average of tags in use +system.cpu.dcache.total_refs 197565955 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444777 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 444.191033 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 320845000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4091.500678 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998902 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998902 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 131517978 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 131517978 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 66044747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 66044747 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1676 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1676 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1554 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1554 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 197562725 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 197562725 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 197562725 # number of overall hits +system.cpu.dcache.overall_hits::total 197562725 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 342017 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 342017 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3372784 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3372784 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3714801 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3714801 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3714801 # number of overall misses +system.cpu.dcache.overall_misses::total 3714801 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5159649500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5159649500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 40250552202 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 40250552202 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 339000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 339000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45410201702 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45410201702 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45410201702 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45410201702 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131859995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131859995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1698 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1698 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1554 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1554 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201277526 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201277526 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201277526 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201277526 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002594 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002594 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048587 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.048587 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012956 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012956 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018456 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018456 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018456 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018456 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15085.944558 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15085.944558 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11933.925268 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 11933.925268 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15409.090909 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15409.090909 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12224.127673 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12224.127673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12224.127673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12224.127673 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 131795 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5078 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.954116 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 421636 # number of writebacks +system.cpu.dcache.writebacks::total 421636 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144398 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 144398 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3125625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3125625 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3270023 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3270023 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3270023 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3270023 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197619 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197619 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247159 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247159 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444778 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444778 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444778 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444778 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875780000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875780000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4060484256 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4060484256 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6936264256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6936264256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6936264256 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6936264256 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001499 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001499 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14552.143266 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14552.143266 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16428.631998 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16428.631998 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15594.890611 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15594.890611 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index 48dcd7446..a8742bbf7 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -116,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -132,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -426,21 +422,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -463,21 +454,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -504,7 +490,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip +executable=/gem5/dist/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 10b614f5f..4ff3426c2 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:11:57 -gem5 started Oct 30 2012 14:00:44 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:16:54 +gem5 started Jan 4 2013 22:00:02 +gem5 executing on u200540 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 387281648500 because target called exit() +Exiting @ tick 387279743500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index c74d8b444..14b499f19 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387282 # Number of seconds simulated -sim_ticks 387281648500 # Number of ticks simulated -final_tick 387281648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387280 # Number of seconds simulated +sim_ticks 387279743500 # Number of ticks simulated +final_tick 387279743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171377 # Simulator instruction rate (inst/s) -host_op_rate 171918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47367883 # Simulator tick rate (ticks/s) -host_mem_usage 224920 # Number of bytes of host memory used -host_seconds 8176.04 # Real time elapsed on the host +host_inst_rate 70741 # Simulator instruction rate (inst/s) +host_op_rate 70964 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19552386 # Simulator tick rate (ticks/s) +host_mem_usage 225936 # Number of bytes of host memory used +host_seconds 19807.29 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678464 # Number of bytes read from this memory -system.physmem.bytes_read::total 1755072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76608 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 76416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678400 # Number of bytes read from this memory +system.physmem.bytes_read::total 1754816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76416 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1197 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26226 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1194 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26225 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27419 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4333962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4531772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197810 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197810 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 418589 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 418589 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 418589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4333962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4950361 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27424 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 197315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4333818 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4531133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197315 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197315 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418591 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4333818 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4949724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27420 # Total number of read requests seen system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29957 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1755072 # Total number of bytes read from memory +system.physmem.cpureqs 29953 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1754816 # Total number of bytes read from memory system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1755072 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1754816 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1698 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1715 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1714 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1805 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1803 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1697 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1696 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1667 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1745 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1746 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1621 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 158 # Tr system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387281620500 # Total gap between requests +system.physmem.totGap 387279715500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27424 # Categorize read packet sizes +system.physmem.readPktSize::6 27420 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,9 +105,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 8242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 8259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5215 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 916 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 722664308 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1404176308 # Sum of mem lat for all requests -system.physmem.totBusLat 109696000 # Total cycles spent in databus access -system.physmem.totBankLat 571816000 # Total cycles spent in bank access -system.physmem.avgQLat 26351.53 # Average queueing delay per request -system.physmem.avgBankLat 20850.93 # Average bank access latency per request +system.physmem.totQLat 724473296 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1405549296 # Sum of mem lat for all requests +system.physmem.totBusLat 109680000 # Total cycles spent in databus access +system.physmem.totBankLat 571396000 # Total cycles spent in bank access +system.physmem.avgQLat 26421.35 # Average queueing delay per request +system.physmem.avgBankLat 20838.66 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 51202.46 # Average memory access latency +system.physmem.avgMemAccLat 51260.00 # Average memory access latency system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s @@ -186,148 +186,148 @@ system.physmem.avgConsumedWrBW 0.42 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 17.43 # Average write queue length over time -system.physmem.readRowHits 18322 # Number of row buffer hits during reads -system.physmem.writeRowHits 1102 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.51 # Row buffer hit rate for writes -system.physmem.avgGap 12927917.36 # Average gap between requests +system.physmem.avgWrQLen 17.06 # Average write queue length over time +system.physmem.readRowHits 18324 # Number of row buffer hits during reads +system.physmem.writeRowHits 1098 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 43.35 # Row buffer hit rate for writes +system.physmem.avgGap 12929580.19 # Average gap between requests system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774563298 # number of cpu cycles simulated +system.cpu.numCycles 774559488 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 97756783 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 88046378 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3616115 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 65822232 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 65492473 # Number of BTB hits +system.cpu.BPredUnit.lookups 97757265 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 88048400 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3615880 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 65812942 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 65493412 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1334 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 221 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 164852368 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1642212446 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97756783 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65493807 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 329195647 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20823123 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 263322100 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2527 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 1346 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 164857001 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642241879 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97757265 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65494758 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329201347 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20830567 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263300608 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2484 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161933661 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 734964 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774355546 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126740 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146682 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 161939590 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 736919 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774350695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126792 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146705 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 445159899 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74061304 9.56% 67.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37898461 4.89% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9077519 1.17% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28105677 3.63% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18773272 2.42% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11484924 1.48% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3792333 0.49% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146002157 18.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445149348 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74062635 9.56% 67.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37899346 4.89% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9077460 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28106060 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18772938 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11486101 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3791039 0.49% 81.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146005768 18.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774355546 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126209 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.120178 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 215883064 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214466469 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 284208572 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42814616 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16982825 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1636500589 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16982825 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 239715972 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36727743 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52434063 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302057850 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126437093 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1625611071 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30924044 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73480825 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3128707 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1356294088 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2746297990 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2712224165 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34073825 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774350695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126210 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.120227 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 215923264 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214411776 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284212483 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42813992 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16989180 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636523306 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16989180 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239767996 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36725834 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52426044 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302047092 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126394549 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625641256 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 163 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30927570 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73422293 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3124815 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356325471 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746325758 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712253189 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34072569 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 111523649 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2645349 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2664178 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271657434 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 436922066 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 179745095 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 254298230 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83339884 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1512454597 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2610820 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1459325981 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 53748 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 109158045 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 130052751 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 367149 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774355546 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.884568 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.432012 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111555032 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2644888 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2664020 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271706062 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436927389 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179744218 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254493315 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83217297 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512489363 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2610612 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459355655 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53704 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109193723 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130058810 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 366941 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774350695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884619 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.431536 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145671235 18.81% 18.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184692846 23.85% 42.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 209497548 27.05% 69.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131299597 16.96% 86.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70722781 9.13% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20304331 2.62% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8026000 1.04% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3959195 0.51% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 182013 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145647727 18.81% 18.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184570267 23.84% 42.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209695290 27.08% 69.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131219118 16.95% 86.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70710319 9.13% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20417492 2.64% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8005951 1.03% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3903236 0.50% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181295 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774355546 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774350695 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 90752 5.46% 5.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95014 5.72% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1160014 69.81% 80.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 315922 19.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 116724 6.93% 6.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95410 5.66% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1152580 68.43% 81.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 319525 18.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 866438962 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866464141 59.37% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2644873 0.18% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644770 0.18% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued @@ -353,84 +353,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419117163 28.72% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171124983 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419120072 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171126672 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1459325981 # Type of FU issued -system.cpu.iq.rate 1.884063 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1661702 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001139 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3676896998 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1615267495 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1443201042 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17825960 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9193607 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8546616 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1451866721 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9120962 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215450617 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459355655 # Type of FU issued +system.cpu.iq.rate 1.884110 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1684239 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001154 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3676971209 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615339802 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443231270 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17828739 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9193054 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8547507 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451917046 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9122848 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215321036 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34409223 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 57798 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 244556 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12896953 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34414546 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 58846 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 246003 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12896076 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3310 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 91608 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3349 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 91624 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16982825 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3082295 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 247112 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1608751818 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4125389 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 436922066 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 179745095 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2527727 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 148822 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1680 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 244556 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2270064 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1474247 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3744311 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1454009970 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 416570645 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5316011 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16989180 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3081240 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 246114 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608786135 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4123964 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436927389 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179744218 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2527628 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 148187 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1651 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 246003 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2270880 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1473539 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3744419 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454037467 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416573795 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5318188 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 93686401 # number of nop insts executed -system.cpu.iew.exec_refs 587021920 # number of memory reference insts executed -system.cpu.iew.exec_branches 89037548 # Number of branches executed -system.cpu.iew.exec_stores 170451275 # Number of stores executed -system.cpu.iew.exec_rate 1.877200 # Inst execution rate -system.cpu.iew.wb_sent 1452636193 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1451747658 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1153420359 # num instructions producing a value -system.cpu.iew.wb_consumers 1204679279 # num instructions consuming a value +system.cpu.iew.exec_nop 93686160 # number of nop insts executed +system.cpu.iew.exec_refs 587024674 # number of memory reference insts executed +system.cpu.iew.exec_branches 89036390 # Number of branches executed +system.cpu.iew.exec_stores 170450879 # Number of stores executed +system.cpu.iew.exec_rate 1.877244 # Inst execution rate +system.cpu.iew.wb_sent 1452666848 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451778777 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153445523 # num instructions producing a value +system.cpu.iew.wb_consumers 1204705379 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.874279 # insts written-back per cycle +system.cpu.iew.wb_rate 1.874328 # insts written-back per cycle system.cpu.iew.wb_fanout 0.957450 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119133058 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119167265 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3616115 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757373332 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.966696 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509453 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3615880 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757361515 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966727 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509795 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 239955150 31.68% 31.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 275777678 36.41% 68.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42556583 5.62% 73.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54728215 7.23% 80.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19718156 2.60% 83.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13293088 1.76% 85.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30577311 4.04% 89.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10491345 1.39% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70275806 9.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 240009654 31.69% 31.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275743732 36.41% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42570119 5.62% 73.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54687779 7.22% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19671272 2.60% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13286277 1.75% 85.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30573058 4.04% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10535838 1.39% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70283786 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757373332 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757361515 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -441,192 +441,192 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70275806 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70283786 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2295688996 # The number of ROB reads -system.cpu.rob.rob_writes 3234318218 # The number of ROB writes -system.cpu.timesIdled 25993 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 207752 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295703406 # The number of ROB reads +system.cpu.rob.rob_writes 3234392884 # The number of ROB writes +system.cpu.timesIdled 26078 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 208793 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552790 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552790 # CPI: Total CPI of All Threads -system.cpu.ipc 1.809005 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.809005 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1979115545 # number of integer regfile reads -system.cpu.int_regfile_writes 1275157860 # number of integer regfile writes -system.cpu.fp_regfile_reads 16963296 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491838 # number of floating regfile writes -system.cpu.misc_regfile_reads 592677531 # number of misc regfile reads +system.cpu.cpi 0.552787 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552787 # CPI: Total CPI of All Threads +system.cpu.ipc 1.809014 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.809014 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979140277 # number of integer regfile reads +system.cpu.int_regfile_writes 1275189089 # number of integer regfile writes +system.cpu.fp_regfile_reads 16965348 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491584 # number of floating regfile writes +system.cpu.misc_regfile_reads 592679771 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 190 # number of replacements -system.cpu.icache.tagsinuse 1035.892325 # Cycle average of tags in use -system.cpu.icache.total_refs 161931728 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1331 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 121661.703982 # Average number of references to valid blocks. +system.cpu.icache.replacements 200 # number of replacements +system.cpu.icache.tagsinuse 1035.695786 # Cycle average of tags in use +system.cpu.icache.total_refs 161937647 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 121029.631540 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.892325 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505807 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505807 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161931728 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161931728 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161931728 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161931728 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161931728 # number of overall hits -system.cpu.icache.overall_hits::total 161931728 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1933 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1933 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1933 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1933 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1933 # number of overall misses -system.cpu.icache.overall_misses::total 1933 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 80019500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 80019500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 80019500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 80019500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 80019500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 80019500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161933661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161933661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161933661 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161933661 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161933661 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161933661 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1035.695786 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505711 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505711 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161937647 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161937647 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161937647 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161937647 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161937647 # number of overall hits +system.cpu.icache.overall_hits::total 161937647 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1943 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1943 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1943 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1943 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1943 # number of overall misses +system.cpu.icache.overall_misses::total 1943 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 81333500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 81333500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 81333500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 81333500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 81333500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 81333500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161939590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161939590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161939590 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161939590 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161939590 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161939590 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41396.533885 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41396.533885 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41396.533885 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41396.533885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41396.533885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41396.533885 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 129 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41859.752959 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41859.752959 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41859.752959 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41859.752959 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41859.752959 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41859.752959 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 32.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 601 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 601 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 601 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 601 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 601 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 601 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1332 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1332 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1332 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1332 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1332 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1332 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58461000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 58461000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58461000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 58461000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58461000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 58461000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1339 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1339 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1339 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1339 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1339 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1339 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59309500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59309500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59309500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59309500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59309500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59309500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43889.639640 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43889.639640 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43889.639640 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43889.639640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43889.639640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43889.639640 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44293.876027 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44293.876027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44293.876027 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 44293.876027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44293.876027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 44293.876027 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22450.499541 # Cycle average of tags in use -system.cpu.l2cache.total_refs 550174 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24271 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.667958 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22451.919806 # Cycle average of tags in use +system.cpu.l2cache.total_refs 550398 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24266 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.681859 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20742.731551 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1060.708507 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 647.059483 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633018 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.032370 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019747 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.685135 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 134 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 196304 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 196438 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 443776 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 647.177496 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.633057 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.032371 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019750 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.685178 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 144 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 196423 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 196567 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 443928 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 443928 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 240651 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 240651 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 144 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47291.631799 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76986.863680 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75692.706054 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,178 +637,178 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks system.cpu.l2cache.writebacks::total 2533 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1198 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4435 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1195 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022095 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027859 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083018 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083018 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.892457 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056605 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059014 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.892457 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056605 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059014 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34704.553975 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 93077.228031 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80693.889579 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58615.991004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58615.991004 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34704.553975 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64447.791573 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63151.541794 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34704.553975 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64447.791573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63151.541794 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459017 # number of replacements -system.cpu.dcache.tagsinuse 4093.828969 # Cycle average of tags in use -system.cpu.dcache.total_refs 365038721 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463113 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 788.228188 # Average number of references to valid blocks. +system.cpu.dcache.replacements 459203 # number of replacements +system.cpu.dcache.tagsinuse 4093.828957 # Cycle average of tags in use +system.cpu.dcache.total_refs 365170885 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463299 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 788.197007 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 342772000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.828969 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4093.828957 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999470 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999470 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200081459 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200081459 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164955943 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164955943 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 200214093 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200214093 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164955473 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164955473 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365037402 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365037402 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365037402 # number of overall hits -system.cpu.dcache.overall_hits::total 365037402 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 927524 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 927524 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1890873 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1890873 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365169566 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365169566 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365169566 # number of overall hits +system.cpu.dcache.overall_hits::total 365169566 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 927691 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 927691 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1891343 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1891343 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2818397 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2818397 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2818397 # number of overall misses -system.cpu.dcache.overall_misses::total 2818397 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14988914500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14988914500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31918196457 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31918196457 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2819034 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2819034 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2819034 # number of overall misses +system.cpu.dcache.overall_misses::total 2819034 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14988091500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14988091500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31927965942 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31927965942 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 122000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 122000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46907110957 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46907110957 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46907110957 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46907110957 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201008983 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201008983 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 46916057442 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46916057442 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46916057442 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46916057442 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201141784 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201141784 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 367855799 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 367855799 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 367855799 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 367855799 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004614 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004614 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011333 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011333 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 367988600 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 367988600 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 367988600 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 367988600 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004612 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004612 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011336 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011336 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007662 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007662 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007662 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007662 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16160.136557 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16160.136557 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16880.137617 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16880.137617 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.007661 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007661 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007661 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007661 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16156.340312 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16156.340312 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16881.108261 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16881.108261 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 17428.571429 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 17428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16643.187939 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16643.187939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16643.187939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16643.187939 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 574305 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35651 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.109085 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16642.600778 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16642.600778 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16642.600778 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16642.600778 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 573681 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35664 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.085717 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443776 # number of writebacks -system.cpu.dcache.writebacks::total 443776 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 726784 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 726784 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628507 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1628507 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2355291 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2355291 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2355291 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2355291 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200740 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200740 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262366 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262366 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 443928 # number of writebacks +system.cpu.dcache.writebacks::total 443928 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 726830 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 726830 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628912 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628912 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2355742 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2355742 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2355742 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2355742 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200861 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200861 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262431 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262431 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 463106 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 463106 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 463106 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 463106 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2634282500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2634282500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319277500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319277500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 463292 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463292 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463292 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463292 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2635998000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2635998000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319921000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319921000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 108000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 108000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6953560000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6953560000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6953560000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6953560000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6955919000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6955919000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6955919000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6955919000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001572 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001572 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13122.857926 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13122.857926 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16462.794341 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16462.794341 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13123.493361 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13123.493361 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16461.168841 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16461.168841 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 15428.571429 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 15428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15015.050550 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15015.050550 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15015.050550 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15015.050550 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15014.114209 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15014.114209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15014.114209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15014.114209 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini index e5a53f4f2..0e20d1517 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -433,21 +430,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -464,6 +456,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -483,21 +478,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -524,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/gem5/dist/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index 22f96a7fe..c000af4ff 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 30 2012 00:35:18 -gem5 started Dec 30 2012 00:35:30 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jan 4 2013 21:20:54 +gem5 started Jan 4 2013 22:11:32 +gem5 executing on u200540 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 63873cca1..6e46a8347 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.607446 # Nu sim_ticks 607445544000 # Number of ticks simulated final_tick 607445544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57635 # Simulator instruction rate (inst/s) -host_op_rate 106195 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39782943 # Simulator tick rate (ticks/s) -host_mem_usage 279268 # Number of bytes of host memory used -host_seconds 15268.99 # Real time elapsed on the host +host_inst_rate 35384 # Simulator instruction rate (inst/s) +host_op_rate 65197 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24424271 # Simulator tick rate (ticks/s) +host_mem_usage 239876 # Number of bytes of host memory used +host_seconds 24870.57 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 57728 # Number of bytes read from this memory @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 156 # Tr system.physmem.perBankWrReqs::15 156 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 607445529000 # Total gap between requests +system.physmem.totGap 607445530000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 68456169 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 822256169 # Sum of mem lat for all requests +system.physmem.totQLat 68456669 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 822256669 # Sum of mem lat for all requests system.physmem.totBusLat 109436000 # Total cycles spent in databus access system.physmem.totBankLat 644364000 # Total cycles spent in bank access -system.physmem.avgQLat 2502.14 # Average queueing delay per request +system.physmem.avgQLat 2502.16 # Average queueing delay per request system.physmem.avgBankLat 23552.18 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30054.32 # Average memory access latency +system.physmem.avgMemAccLat 30054.34 # Average memory access latency system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s @@ -191,7 +191,7 @@ system.physmem.readRowHits 17697 # Nu system.physmem.writeRowHits 1084 # Number of row buffer hits during writes system.physmem.readRowHitRate 64.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate 42.78 # Row buffer hit rate for writes -system.physmem.avgGap 20320661.33 # Average gap between requests +system.physmem.avgGap 20320661.36 # Average gap between requests system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1214891089 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -204,22 +204,22 @@ system.cpu.BPredUnit.BTBHits 84079165 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 179135724 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 179135725 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 1458430747 # Number of instructions fetch has processed system.cpu.fetch.Branches 158385701 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 84079165 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 399080479 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 88232216 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 574634439 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.BlockedCycles 574634441 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 381 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 187842502 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11743850 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1214538068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 187842503 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11743851 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1214538070 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.059666 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.253312 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 822675210 67.74% 67.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 822675212 67.74% 67.74% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 26883309 2.21% 69.95% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 13192065 1.09% 71.04% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 20566257 1.69% 72.73% # Number of instructions fetched each cycle (Total) @@ -231,18 +231,18 @@ system.cpu.fetch.rateDist::8 215850749 17.77% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1214538068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1214538070 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.130370 # Number of branch fetches per cycle system.cpu.fetch.rate 1.200462 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 288247470 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 497953946 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 497953948 # Number of cycles decode is blocked system.cpu.decode.RunCycles 274080522 # Number of cycles decode is running system.cpu.decode.UnblockCycles 92569137 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 61686993 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 2343830219 # Number of instructions handled by decode system.cpu.rename.SquashCycles 61686993 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 336887109 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124143934 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 124143936 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2487 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 304057721 # Number of cycles rename is running system.cpu.rename.UnblockCycles 387759824 # Number of cycles rename is unblocking @@ -270,11 +270,11 @@ system.cpu.iq.iqSquashedInstsIssued 243450 # Nu system.cpu.iq.iqSquashedInstsExamined 372613756 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 761627172 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 239 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1214538068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1214538070 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.468938 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.421549 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 360345167 29.67% 29.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360345169 29.67% 29.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 364336445 30.00% 59.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 234287346 19.29% 78.96% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 141446603 11.65% 90.60% # Number of insts issued each cycle @@ -286,7 +286,7 @@ system.cpu.iq.issued_per_cycle::8 597279 0.05% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1214538068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1214538070 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 437572 15.09% 15.09% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 15.09% # attempts to use FU when none available @@ -359,7 +359,7 @@ system.cpu.iq.FU_type_0::total 1784080761 # Ty system.cpu.iq.rate 1.468511 # Inst issue rate system.cpu.iq.fu_busy_cnt 2900605 # FU busy when requested system.cpu.iq.fu_busy_rate 0.001626 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4785843295 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 4785843297 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2367295034 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1724820361 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 350 # Number of floating instruction queue reads @@ -379,7 +379,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 2481 # system.cpu.iew.lsq.thread0.cacheBlocked 68 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 61686993 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1142263 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 1142265 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 110648 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 1994506717 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 63004482 # Number of squashed instructions skipped by dispatch @@ -412,11 +412,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 373014217 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 26390469 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1152851075 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 1152851077 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.406508 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.830012 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 418199685 36.28% 36.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 418199687 36.28% 36.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 415017727 36.00% 72.27% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 87014149 7.55% 79.82% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 122172880 10.60% 90.42% # Number of insts commited each cycle @@ -428,7 +428,7 @@ system.cpu.commit.committed_per_cycle::8 32432091 2.81% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1152851075 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1152851077 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493926 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -441,10 +441,10 @@ system.cpu.commit.int_insts 1621354437 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 32432091 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3114927127 # The number of ROB reads +system.cpu.rob.rob_reads 3114927129 # The number of ROB reads system.cpu.rob.rob_writes 4050738571 # The number of ROB writes system.cpu.timesIdled 58873 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 353021 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 353019 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493926 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated @@ -471,36 +471,36 @@ system.cpu.icache.demand_hits::cpu.inst 187841119 # nu system.cpu.icache.demand_hits::total 187841119 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 187841119 # number of overall hits system.cpu.icache.overall_hits::total 187841119 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1383 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1383 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1383 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1383 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1383 # number of overall misses -system.cpu.icache.overall_misses::total 1383 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64282500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64282500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64282500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64282500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64282500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64282500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 187842502 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 187842502 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 187842502 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 187842502 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 187842502 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 187842502 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 1384 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1384 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1384 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1384 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1384 # number of overall misses +system.cpu.icache.overall_misses::total 1384 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 64353500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 64353500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 64353500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 64353500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 64353500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 64353500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 187842503 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 187842503 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 187842503 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 187842503 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 187842503 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 187842503 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46480.477223 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46480.477223 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46480.477223 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46480.477223 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46480.477223 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46480.477223 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46498.193642 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46498.193642 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46498.193642 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46498.193642 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46498.193642 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46498.193642 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 203 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -509,12 +509,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 40.600000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 465 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 465 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 465 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 465 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 465 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 466 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 466 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 466 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 466 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 466 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 466 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 918 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 918 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 918 # number of demand (read+write) MSHR misses @@ -540,114 +540,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50259.259259 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50259.259259 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 50259.259259 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 446019 # number of replacements -system.cpu.dcache.tagsinuse 4092.902027 # Cycle average of tags in use -system.cpu.dcache.total_refs 452395605 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 450115 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1005.066716 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 828955000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4092.902027 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999244 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999244 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 264455973 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 264455973 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 187939624 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 187939624 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 452395597 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 452395597 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 452395597 # 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number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7079925499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7079925499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7079925499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7079925499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264667108 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264667108 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 452853166 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 452853166 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 452853166 # 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average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16490.618174 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15472.913373 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15472.913373 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15472.913373 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15472.913373 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 474 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 48 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.875000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428963 # number of writebacks -system.cpu.dcache.writebacks::total 428963 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7361 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7361 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 84 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 84 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7445 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7445 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7445 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7445 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203774 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203774 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246350 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246350 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 450124 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 450124 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 450124 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 450124 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523541000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523541000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3570237499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3570237499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6093778499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6093778499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6093778499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6093778499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12384.018570 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12384.018570 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14492.541096 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14492.541096 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13537.999527 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13537.999527 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13537.999527 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13537.999527 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2556 # number of replacements system.cpu.l2cache.tagsinuse 22259.528577 # Cycle average of tags in use system.cpu.l2cache.total_refs 531228 # Total number of references to valid blocks. @@ -655,7 +547,7 @@ system.cpu.l2cache.sampled_refs 24191 # Sa system.cpu.l2cache.avg_refs 21.959737 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 20782.488903 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 799.212801 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 799.212802 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 677.826873 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.634231 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.024390 # Average percentage of cache occupancy @@ -688,16 +580,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 902 # system.cpu.l2cache.overall_misses::cpu.data 26457 # number of overall misses system.cpu.l2cache.overall_misses::total 27359 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45120000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 325819500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 370939500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1079318500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1079318500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 325819000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 370939000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1079319500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1079319500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 45120000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1405138000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1450258000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1405138500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1450258500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 45120000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1405138000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1450258000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1405138500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1450258500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 910 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 203769 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 204679 # number of ReadReq accesses(hits+misses) @@ -725,16 +617,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991209 system.cpu.l2cache.overall_miss_rate::cpu.data 0.058778 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.060659 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50022.172949 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71451.644737 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67912.760893 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49290.701923 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49290.701923 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71451.535088 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67912.669352 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49290.747591 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49290.747591 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50022.172949 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53110.254375 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53008.443291 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53110.273274 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53008.461567 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50022.172949 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53110.254375 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53008.443291 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53110.273274 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53008.461567 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -756,16 +648,16 @@ system.cpu.l2cache.demand_mshr_misses::total 27359 system.cpu.l2cache.overall_mshr_misses::cpu.inst 902 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 26457 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 27359 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33761933 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 267685448 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301447381 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1064342050 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 1098103483 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33761933 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1064341550 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33761433 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1064342050 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 1098103483 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991209 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022378 # mshr miss rate for ReadReq accesses @@ -778,17 +670,125 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.060659 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991209 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058778 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.060659 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37430.080931 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58702.949123 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55189.926950 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36381.974791 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36381.974791 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37430.080931 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40229.109498 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37429.526608 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58702.839474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55189.743867 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36382.020459 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36382.020459 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37429.526608 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40229.128397 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40136.828210 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37430.080931 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40229.109498 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37429.526608 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40229.128397 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40136.828210 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 446019 # number of replacements +system.cpu.dcache.tagsinuse 4092.902027 # Cycle average of tags in use +system.cpu.dcache.total_refs 452395605 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 450115 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1005.066716 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 828955000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4092.902027 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999244 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999244 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 264455973 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264455973 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939624 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939624 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452395597 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452395597 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452395597 # number of overall hits +system.cpu.dcache.overall_hits::total 452395597 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 211135 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 211135 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246434 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246434 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 457569 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 457569 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 457569 # number of overall misses +system.cpu.dcache.overall_misses::total 457569 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3016076000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3016076000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4063849999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4063849999 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7079925999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7079925999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7079925999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7079925999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264667108 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264667108 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 452853166 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 452853166 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 452853166 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 452853166 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000798 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000798 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001310 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.001010 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001010 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001010 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001010 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14285.059322 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14285.059322 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16490.622232 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16490.622232 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15472.914465 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15472.914465 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15472.914465 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15472.914465 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 474 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 48 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.875000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 428963 # number of writebacks +system.cpu.dcache.writebacks::total 428963 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7361 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7361 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 84 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 84 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7445 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7445 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7445 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7445 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203774 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203774 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246350 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246350 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 450124 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 450124 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 450124 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 450124 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523540500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523540500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3570238499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3570238499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6093778999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6093778999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6093778999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6093778999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12384.016116 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12384.016116 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14492.545155 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14492.545155 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13538.000638 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13538.000638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13538.000638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13538.000638 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |