diff options
Diffstat (limited to 'tests/long/se/00.gzip')
38 files changed, 831 insertions, 268 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 37ea66e58..c1fb80fc3 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout index 4bff58d47..b4ecd43cf 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:38:38 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:43:43 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 7e649e9a6..e5597cd29 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.274300 # Nu sim_ticks 274300226500 # Number of ticks simulated final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71153 # Simulator instruction rate (inst/s) -host_op_rate 71153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32428333 # Simulator tick rate (ticks/s) -host_mem_usage 214868 # Number of bytes of host memory used -host_seconds 8458.66 # Real time elapsed on the host +host_inst_rate 112537 # Simulator instruction rate (inst/s) +host_op_rate 112537 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51289289 # Simulator tick rate (ticks/s) +host_mem_usage 215256 # Number of bytes of host memory used +host_seconds 5348.10 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5894080 # Number of bytes read from this memory -system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3798144 # Number of bytes written to this memory -system.physmem.num_reads 92095 # Number of read requests responded to by this memory -system.physmem.num_writes 59346 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 21487696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 199489 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13846667 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 35334364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 54720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory +system.physmem.bytes_read::total 5894080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 54720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 54720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3798144 # Number of bytes written to this memory +system.physmem.bytes_written::total 3798144 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 855 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory +system.physmem.num_reads::total 92095 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59346 # Number of write requests responded to by this memory +system.physmem.num_writes::total 59346 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 199489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 21288207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 21487696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 13846667 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13846667 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 13846667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 21288207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35334364 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -156,11 +169,17 @@ system.cpu.icache.demand_accesses::total 25020500 # nu system.cpu.icache.overall_accesses::cpu.inst 25020500 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 25020500 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55543.095005 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55543.095005 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55543.095005 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,11 +207,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 45765000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45765000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 45765000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53526.315789 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.tagsinuse 4094.124914 # Cycle average of tags in use @@ -236,13 +261,21 @@ system.cpu.dcache.demand_accesses::total 153965363 # nu system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029850 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029850 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.010205 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010205 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.010205 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010205 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.000094 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.000094 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21439.553674 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21257.069353 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21257.069353 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 12006000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 3424818500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2777 # number of cycles access was blocked @@ -278,13 +311,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 9028960000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028960000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 9028960000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.436650 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17701.436650 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21509.285380 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21509.285380 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73798 # number of replacements system.cpu.l2cache.tagsinuse 17696.811171 # Cycle average of tags in use @@ -346,18 +387,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 455395 system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.158457 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236350 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.236350 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.200354 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.201852 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.200354 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.201852 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52359.649123 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.042485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52310.393829 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52174.395765 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52174.395765 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52221.678701 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52221.678701 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 1278500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked @@ -392,18 +441,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653566500 system.cpu.l2cache.overall_mshr_miss_latency::total 3687911500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158457 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236350 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236350 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.201852 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.201852 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.914773 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40008.338799 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40063.993941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40063.993941 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40044.644117 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40044.644117 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini index d7f68c19e..01ebbe1c7 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout index 1f4384270..ef914e93c 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:42:45 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 0a8d681a5..aa861e979 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.134621 # Nu sim_ticks 134621123500 # Number of ticks simulated final_tick 134621123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99995 # Simulator instruction rate (inst/s) -host_op_rate 99995 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23802311 # Simulator tick rate (ticks/s) -host_mem_usage 215740 # Number of bytes of host memory used -host_seconds 5655.80 # Real time elapsed on the host +host_inst_rate 192359 # Simulator instruction rate (inst/s) +host_op_rate 192359 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45788058 # Simulator tick rate (ticks/s) +host_mem_usage 216172 # Number of bytes of host memory used +host_seconds 2940.09 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5937600 # Number of bytes read from this memory -system.physmem.bytes_inst_read 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3797952 # Number of bytes written to this memory -system.physmem.num_reads 92775 # Number of read requests responded to by this memory -system.physmem.num_writes 59343 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 44106005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 476359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 28212155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 72318160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 64128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5873472 # Number of bytes read from this memory +system.physmem.bytes_read::total 5937600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3797952 # Number of bytes written to this memory +system.physmem.bytes_written::total 3797952 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1002 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 91773 # Number of read requests responded to by this memory +system.physmem.num_reads::total 92775 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59343 # Number of write requests responded to by this memory +system.physmem.num_writes::total 59343 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 476359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 43629646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 44106005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 476359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 476359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 28212155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 28212155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 28212155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 476359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 43629646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72318160 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -358,11 +371,17 @@ system.cpu.icache.demand_accesses::total 66483943 # nu system.cpu.icache.overall_accesses::cpu.inst 66483943 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 66483943 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34946.440912 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34946.440912 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34946.440912 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34946.440912 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34946.440912 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,11 +409,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 35750000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35750000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 35750000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35678.642715 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35678.642715 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35678.642715 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35678.642715 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 460743 # number of replacements system.cpu.dcache.tagsinuse 4093.783086 # Cycle average of tags in use @@ -446,15 +471,25 @@ system.cpu.dcache.demand_accesses::total 151114481 # nu system.cpu.dcache.overall_accesses::cpu.data 151114481 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 151114481 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006469 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006469 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032971 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032971 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015873 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.015873 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.013388 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013388 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.013388 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.013388 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16273.449094 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16273.449094 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15091.410417 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15091.410417 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 3500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 3500 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15513.457453 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.457453 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15513.457453 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 678496 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 191500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 100 # number of cycles access was blocked @@ -492,13 +527,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4648014495 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4648014495 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 4648014495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001883 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006452 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003076 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003076 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7699.484588 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7699.484588 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11899.490005 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11899.490005 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9999.192183 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 9999.192183 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 74480 # number of replacements system.cpu.l2cache.tagsinuse 17651.004599 # Cycle average of tags in use @@ -560,18 +603,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 464839 system.cpu.l2cache.overall_accesses::total 465841 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.151842 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.155864 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235100 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.235100 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.197430 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.199156 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.197430 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.199156 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34353.792415 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34398.888367 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34397.516471 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34540.434172 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34540.434172 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34353.792415 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34491.179323 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34489.695500 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34353.792415 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34491.179323 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34489.695500 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 339500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 49 # number of cycles access was blocked @@ -606,18 +657,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2868929500 system.cpu.l2cache.overall_mshr_miss_latency::total 2900132500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.151842 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.155864 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.199156 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.197430 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.199156 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31140.718563 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.093158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31018.914898 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31392.467997 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31392.467997 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31259.849097 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31140.718563 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31261.149794 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31259.849097 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 927f52249..352fd32f4 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr index 1b49765a7..1ed796979 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout index db142b8a8..a4781a82f 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:40 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:03:38 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index 068e22070..7df2c8121 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.300931 # Nu sim_ticks 300930958000 # Number of ticks simulated final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2479447 # Simulator instruction rate (inst/s) -host_op_rate 2479447 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1239733454 # Simulator tick rate (ticks/s) -host_mem_usage 205680 # Number of bytes of host memory used -host_seconds 242.74 # Real time elapsed on the host +host_inst_rate 3871430 # Simulator instruction rate (inst/s) +host_op_rate 3871429 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1935730316 # Simulator tick rate (ticks/s) +host_mem_usage 206040 # Number of bytes of host memory used +host_seconds 155.46 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 2782990928 # Number of bytes read from this memory -system.physmem.bytes_inst_read 2407447588 # Number of instructions bytes read from this memory -system.physmem.bytes_written 152669504 # Number of bytes written to this memory -system.physmem.num_reads 716375939 # Number of read requests responded to by this memory -system.physmem.num_writes 39451321 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9247938286 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999999747 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 507324022 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9755262308 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 375543340 # Number of bytes read from this memory +system.physmem.bytes_read::total 2782990928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2407447588 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2407447588 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 152669504 # Number of bytes written to this memory +system.physmem.bytes_written::total 152669504 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 601861897 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 114514042 # Number of read requests responded to by this memory +system.physmem.num_reads::total 716375939 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 39451321 # Number of write requests responded to by this memory +system.physmem.num_writes::total 39451321 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999999747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1247938539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9247938286 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999999747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999999747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 507324022 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 507324022 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999999747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1755262561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9755262308 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 86520ac69..f4efff3d6 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout index 5a809a831..fcee7bced 100755 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:07 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:42:36 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index fb6f85834..4082e04ad 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.765623 # Nu sim_ticks 765623032000 # Number of ticks simulated final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 835603 # Simulator instruction rate (inst/s) -host_op_rate 835603 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1062971026 # Simulator tick rate (ticks/s) -host_mem_usage 214568 # Number of bytes of host memory used -host_seconds 720.27 # Real time elapsed on the host +host_inst_rate 1675799 # Simulator instruction rate (inst/s) +host_op_rate 1675799 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2131786057 # Simulator tick rate (ticks/s) +host_mem_usage 214908 # Number of bytes of host memory used +host_seconds 359.15 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5889984 # Number of bytes read from this memory -system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3797824 # Number of bytes written to this memory -system.physmem.num_reads 92031 # Number of read requests responded to by this memory -system.physmem.num_writes 59341 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7693060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 66456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 4960436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 12653496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 50880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5839104 # Number of bytes read from this memory +system.physmem.bytes_read::total 5889984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3797824 # Number of bytes written to this memory +system.physmem.bytes_written::total 3797824 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 795 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 91236 # Number of read requests responded to by this memory +system.physmem.num_reads::total 92031 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59341 # Number of write requests responded to by this memory +system.physmem.num_writes::total 59341 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 66456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 7626604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7693060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 66456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 66456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4960436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4960436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4960436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 66456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 7626604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12653496 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -110,11 +123,17 @@ system.cpu.icache.demand_accesses::total 601861898 # nu system.cpu.icache.overall_accesses::cpu.inst 601861898 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 601861898 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,11 +155,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 42135000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42135000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use @@ -184,13 +209,21 @@ system.cpu.dcache.demand_accesses::total 153965363 # nu system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006442 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20504.999205 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23926.299265 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22414.479737 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22414.479737 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -218,13 +251,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8841257000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8841257000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.999205 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20926.299265 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73734 # number of replacements system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use @@ -286,18 +327,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 455395 system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.158207 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236340 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.236340 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.200345 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.201738 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.200345 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.201738 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -332,18 +381,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000 system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158207 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236340 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.201738 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.201738 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index d2c692362..c1e9b189c 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 6445e3ddc..1edb7f5fa 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:58 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:27:39 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 54f7feb76..ed106fd55 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.164248 # Nu sim_ticks 164248292500 # Number of ticks simulated final_tick 164248292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95192 # Simulator instruction rate (inst/s) -host_op_rate 100587 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27427613 # Simulator tick rate (ticks/s) -host_mem_usage 231504 # Number of bytes of host memory used -host_seconds 5988.43 # Real time elapsed on the host +host_inst_rate 143439 # Simulator instruction rate (inst/s) +host_op_rate 151568 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41328806 # Simulator tick rate (ticks/s) +host_mem_usage 231960 # Number of bytes of host memory used +host_seconds 3974.18 # Real time elapsed on the host sim_insts 570052728 # Number of instructions simulated sim_ops 602360935 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5850432 # Number of bytes read from this memory -system.physmem.bytes_inst_read 51136 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3722112 # Number of bytes written to this memory -system.physmem.num_reads 91413 # Number of read requests responded to by this memory -system.physmem.num_writes 58158 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 35619439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 311334 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 22661496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 58280935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 51136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5799296 # Number of bytes read from this memory +system.physmem.bytes_read::total 5850432 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 51136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 51136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3722112 # Number of bytes written to this memory +system.physmem.bytes_written::total 3722112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 799 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 90614 # Number of read requests responded to by this memory +system.physmem.num_reads::total 91413 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58158 # Number of write requests responded to by this memory +system.physmem.num_writes::total 58158 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 311334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35308105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 35619439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 311334 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 311334 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 22661496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 22661496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 22661496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 311334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35308105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58280935 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -368,11 +381,17 @@ system.cpu.icache.demand_accesses::total 67495318 # nu system.cpu.icache.overall_accesses::cpu.inst 67495318 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 67495318 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34196.692776 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34196.692776 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34196.692776 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34196.692776 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34196.692776 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,11 +419,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 28616000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28616000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 28616000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34107.270560 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34107.270560 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34107.270560 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34107.270560 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34107.270560 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34107.270560 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 440506 # number of replacements system.cpu.dcache.tagsinuse 4094.673413 # Cycle average of tags in use @@ -460,15 +485,25 @@ system.cpu.dcache.demand_accesses::total 201731606 # nu system.cpu.dcache.overall_accesses::cpu.data 201731606 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 201731606 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001884 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001884 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022587 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022587 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.009379 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.009379 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009008 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009008 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009008 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009008 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13208.806613 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13208.806613 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17259.271740 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17259.271740 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12687.500000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12687.500000 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16703.549355 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 16703.549355 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16703.549355 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 9569014 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2180 # number of cycles access was blocked @@ -506,13 +541,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4172571513 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4172571513 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 4172571513 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001493 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001493 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003560 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002204 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002204 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002204 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8257.093815 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8257.093815 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10286.222787 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10286.222787 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9384.874502 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 9384.874502 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9384.874502 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 9384.874502 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 73212 # number of replacements system.cpu.l2cache.tagsinuse 17814.608666 # Cycle average of tags in use @@ -583,19 +626,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 444603 system.cpu.l2cache.overall_accesses::total 445439 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.956938 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163582 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.166926 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.333333 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235994 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.235994 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.956938 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.203829 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.205242 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.956938 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.203829 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.205242 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.875000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34299.124002 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34299.915423 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34319.932438 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34319.932438 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.875000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34312.514483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34312.683898 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.875000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34312.514483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34312.683898 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2005000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 332 # number of cycles access was blocked @@ -643,20 +695,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2825195000 system.cpu.l2cache.overall_mshr_miss_latency::total 2850070000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163537 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166876 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235994 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235994 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.205220 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.955742 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203809 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.205220 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31132.665832 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31085.271078 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.415277 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31229.898657 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31229.898657 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31177.950620 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31132.665832 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31178.349924 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31177.950620 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini index 98278be8c..c0d4f8993 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout index aa43ef922..3264273f7 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:21:51 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:27:49 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index b23b7f871..ab951a1c0 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.301191 # Nu sim_ticks 301191370000 # Number of ticks simulated final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1201570 # Simulator instruction rate (inst/s) -host_op_rate 1269670 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 634859326 # Simulator tick rate (ticks/s) -host_mem_usage 220780 # Number of bytes of host memory used -host_seconds 474.42 # Real time elapsed on the host +host_inst_rate 2291609 # Simulator instruction rate (inst/s) +host_op_rate 2421488 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1210789798 # Simulator tick rate (ticks/s) +host_mem_usage 221260 # Number of bytes of host memory used +host_seconds 248.76 # Real time elapsed on the host sim_insts 570051644 # Number of instructions simulated sim_ops 602359851 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 2680160157 # Number of bytes read from this memory -system.physmem.bytes_inst_read 2280298136 # Number of instructions bytes read from this memory -system.physmem.bytes_written 236359611 # Number of bytes written to this memory -system.physmem.num_reads 717867713 # Number of read requests responded to by this memory -system.physmem.num_writes 69418858 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 8898529055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7570927866 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 784748949 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9683278004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 2280298136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 399862021 # Number of bytes read from this memory +system.physmem.bytes_read::total 2680160157 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2280298136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2280298136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 236359611 # Number of bytes written to this memory +system.physmem.bytes_written::total 236359611 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 570074534 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147793179 # Number of read requests responded to by this memory +system.physmem.num_reads::total 717867713 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 69418858 # Number of write requests responded to by this memory +system.physmem.num_writes::total 69418858 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7570927866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1327601189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8898529055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7570927866 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7570927866 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 784748949 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 784748949 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7570927866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2112350138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9683278004 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini index 8ba39dd31..81852cb71 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout index ec5b6e605..dd5e622ba 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:22:17 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:27:51 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index dd6b444c4..44a2387d1 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.796763 # Nu sim_ticks 796762926000 # Number of ticks simulated final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 606714 # Simulator instruction rate (inst/s) -host_op_rate 640712 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 850261270 # Simulator tick rate (ticks/s) -host_mem_usage 229976 # Number of bytes of host memory used -host_seconds 937.08 # Real time elapsed on the host +host_inst_rate 1154549 # Simulator instruction rate (inst/s) +host_op_rate 1219245 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1618008338 # Simulator tick rate (ticks/s) +host_mem_usage 230404 # Number of bytes of host memory used +host_seconds 492.43 # Real time elapsed on the host sim_insts 568539343 # Number of instructions simulated sim_ops 600398281 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5759488 # Number of bytes read from this memory -system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3704704 # Number of bytes written to this memory -system.physmem.num_reads 89992 # Number of read requests responded to by this memory -system.physmem.num_writes 57886 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7228609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 49480 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 4649694 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11878304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5720064 # Number of bytes read from this memory +system.physmem.bytes_read::total 5759488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3704704 # Number of bytes written to this memory +system.physmem.bytes_written::total 3704704 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 89376 # Number of read requests responded to by this memory +system.physmem.num_reads::total 89992 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57886 # Number of write requests responded to by this memory +system.physmem.num_writes::total 57886 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 49480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 7179129 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7228609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 49480 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 49480 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4649694 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4649694 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4649694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 49480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 7179129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11878304 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 570074535 # nu system.cpu.icache.overall_accesses::cpu.inst 570074535 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 570074535 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54236.391913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54236.391913 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54236.391913 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54236.391913 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 32945000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32945000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 32945000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51236.391913 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51236.391913 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 433468 # number of replacements system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use @@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 217209383 # nu system.cpu.dcache.overall_accesses::cpu.data 217209383 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 217209383 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20842.679226 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20842.679226 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23909.028529 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23909.028529 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22578.841038 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22578.841038 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8566996000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8566996000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8566996000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17842.679226 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17842.679226 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20909.028529 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20909.028529 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 71804 # number of replacements system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use @@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 437564 system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958009 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.165605 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235929 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.235929 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958009 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.204258 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.205364 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958009 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.204258 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.205364 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3575040000 system.cpu.l2cache.overall_mshr_miss_latency::total 3599680000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165605 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235929 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235929 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.205364 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.205364 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini index 98314f012..6dd839e0e 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout index 3d27114e4..b261460cd 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:43:17 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:35 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 3819069b9..042ffd7cf 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.388554 # Nu sim_ticks 388554296500 # Number of ticks simulated final_tick 388554296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119684 # Simulator instruction rate (inst/s) -host_op_rate 120061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33188741 # Simulator tick rate (ticks/s) -host_mem_usage 223864 # Number of bytes of host memory used -host_seconds 11707.41 # Real time elapsed on the host +host_inst_rate 160259 # Simulator instruction rate (inst/s) +host_op_rate 160764 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44440455 # Simulator tick rate (ticks/s) +host_mem_usage 224388 # Number of bytes of host memory used +host_seconds 8743.26 # Real time elapsed on the host sim_insts 1401188958 # Number of instructions simulated sim_ops 1405604152 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5987456 # Number of bytes read from this memory -system.physmem.bytes_inst_read 85056 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3788160 # Number of bytes written to this memory -system.physmem.num_reads 93554 # Number of read requests responded to by this memory -system.physmem.num_writes 59190 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 15409574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 218904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 9749371 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 25158945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 85056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5902400 # Number of bytes read from this memory +system.physmem.bytes_read::total 5987456 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 85056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 85056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3788160 # Number of bytes written to this memory +system.physmem.bytes_written::total 3788160 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1329 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 92225 # Number of read requests responded to by this memory +system.physmem.num_reads::total 93554 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59190 # Number of write requests responded to by this memory +system.physmem.num_writes::total 59190 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 218904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15190670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15409574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 218904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 218904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9749371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 9749371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9749371 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 218904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15190670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 25158945 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.numCycles 777108594 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -324,11 +337,17 @@ system.cpu.icache.demand_accesses::total 162823525 # nu system.cpu.icache.overall_accesses::cpu.inst 162823525 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 162823525 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.544534 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34024.544534 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34024.544534 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.544534 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34024.544534 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -356,11 +375,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 47023000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47023000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 47023000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34780.325444 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34780.325444 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34780.325444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34780.325444 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 458031 # number of replacements system.cpu.dcache.tagsinuse 4095.115790 # Cycle average of tags in use @@ -412,15 +437,25 @@ system.cpu.dcache.demand_accesses::total 368453310 # nu system.cpu.dcache.overall_accesses::cpu.data 368453310 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 368453310 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003985 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003985 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011224 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011224 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.007263 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007263 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.007263 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007263 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14794.703875 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14794.703875 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15844.705290 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15844.705290 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38142.857143 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 38142.857143 # average SwapReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15529.487014 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 15529.487014 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15529.487014 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked @@ -460,15 +495,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 5156941222 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5156941222 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 5156941222 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001571 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001571 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001254 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7769.265376 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7769.265376 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13747.043644 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13747.043644 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35142.857143 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 35142.857143 # average SwapReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11159.311915 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11159.311915 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11159.311915 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 75325 # number of replacements system.cpu.l2cache.tagsinuse 17833.274372 # Cycle average of tags in use @@ -533,18 +578,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 462127 system.cpu.l2cache.overall_accesses::total 463479 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982988 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.160796 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.166316 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.229160 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.229160 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982988 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.199566 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.201852 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982988 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.199566 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.201852 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34238.148984 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34029.222495 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34037.511942 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34411.294082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34411.294082 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34277.465421 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34238.148984 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34278.031987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34277.465421 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -579,18 +632,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2878289500 system.cpu.l2cache.overall_mshr_miss_latency::total 2919493000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.160796 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166316 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.229160 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.229160 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.201852 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982988 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.199566 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.201852 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31003.386005 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.486990 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.403630 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31318.658630 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31318.658630 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31206.501058 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31003.386005 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31209.428029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31206.501058 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 5860d36d4..47913c070 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout index 86dd2db54..bf7412ed2 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:43:18 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:41 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index a7bbf2f2d..ed36e3ce0 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -4,23 +4,37 @@ sim_seconds 0.744764 # Nu sim_ticks 744764119000 # Number of ticks simulated final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1723625 # Simulator instruction rate (inst/s) -host_op_rate 1728749 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 864377228 # Simulator tick rate (ticks/s) -host_mem_usage 213676 # Number of bytes of host memory used -host_seconds 861.62 # Real time elapsed on the host +host_inst_rate 3186892 # Simulator instruction rate (inst/s) +host_op_rate 3196366 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1598188492 # Simulator tick rate (ticks/s) +host_mem_usage 214172 # Number of bytes of host memory used +host_seconds 466.01 # Real time elapsed on the host sim_insts 1485108101 # Number of instructions simulated sim_ops 1489523295 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 7326269637 # Number of bytes read from this memory -system.physmem.bytes_inst_read 5940452044 # Number of instructions bytes read from this memory -system.physmem.bytes_written 614672063 # Number of bytes written to this memory -system.physmem.num_reads 1887625855 # Number of read requests responded to by this memory -system.physmem.num_writes 166846816 # Number of write requests responded to by this memory -system.physmem.num_other 1326 # Number of other requests responded to by this memory -system.physmem.bw_read 9837033566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7976286575 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 825324485 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 10662358051 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 5940452044 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1385817593 # Number of bytes read from this memory +system.physmem.bytes_read::total 7326269637 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5940452044 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5940452044 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 614672063 # Number of bytes written to this memory +system.physmem.bytes_written::total 614672063 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1485113011 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 402512844 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1887625855 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 166846816 # Number of write requests responded to by this memory +system.physmem.num_writes::total 166846816 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 1326 # Number of other requests responded to by this memory +system.physmem.num_other::total 1326 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7976286575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1860746990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9837033566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7976286575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7976286575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 825324485 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 825324485 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7976286575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2686071475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10662358051 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.numCycles 1489528239 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini index 8e4dd6b01..577b4c1d7 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout index 0309c0267..4517a277e 100755 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:43:22 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:45 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 327f1f99e..0ce23ef70 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 2.064259 # Nu sim_ticks 2064258667000 # Number of ticks simulated final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 667477 # Simulator instruction rate (inst/s) -host_op_rate 669461 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 927773801 # Simulator tick rate (ticks/s) -host_mem_usage 222564 # Number of bytes of host memory used -host_seconds 2224.96 # Real time elapsed on the host +host_inst_rate 1371910 # Simulator instruction rate (inst/s) +host_op_rate 1375988 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1906915769 # Simulator tick rate (ticks/s) +host_mem_usage 223048 # Number of bytes of host memory used +host_seconds 1082.51 # Real time elapsed on the host sim_insts 1485108101 # Number of instructions simulated sim_ops 1489523295 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5909952 # Number of bytes read from this memory -system.physmem.bytes_inst_read 70592 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3778240 # Number of bytes written to this memory -system.physmem.num_reads 92343 # Number of read requests responded to by this memory -system.physmem.num_writes 59035 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2862990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 34197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1830313 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 4693303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 70592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory +system.physmem.bytes_read::total 5909952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 70592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 70592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3778240 # Number of bytes written to this memory +system.physmem.bytes_written::total 3778240 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1103 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory +system.physmem.num_reads::total 92343 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59035 # Number of write requests responded to by this memory +system.physmem.num_writes::total 59035 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 34197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2828793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2862990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 34197 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 34197 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1830313 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1830313 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1830313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 34197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2828793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4693303 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.numCycles 4128517334 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 1485113012 # nu system.cpu.icache.overall_accesses::cpu.inst 1485113012 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1485113012 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55848.238482 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55848.238482 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55848.238482 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55848.238482 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 58503000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58503000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 58503000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52848.238482 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52848.238482 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 449125 # number of replacements system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use @@ -160,15 +185,25 @@ system.cpu.dcache.demand_accesses::total 569359660 # nu system.cpu.dcache.overall_accesses::cpu.data 569359660 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 569359660 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001557 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000796 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20775.839079 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20775.839079 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23705.368693 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23705.368693 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22454.694692 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22454.694692 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,15 +235,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8817140000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8817140000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8817140000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001557 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17775.839079 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20705.368693 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20705.368693 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 74112 # number of replacements system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use @@ -273,18 +318,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 453221 system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996387 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.161330 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.166080 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231101 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.231101 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996387 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.201315 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.203252 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996387 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.201315 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.203252 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,18 +372,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649600000 system.cpu.l2cache.overall_mshr_miss_latency::total 3693720000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.161330 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166080 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231101 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.231101 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.203252 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.203252 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout index 7b2a9ad59..5eab9f73c 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:07:25 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 639bcc189..26e1be238 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.636988 # Nu sim_ticks 636988382500 # Number of ticks simulated final_tick 636988382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71818 # Simulator instruction rate (inst/s) -host_op_rate 132329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51984066 # Simulator tick rate (ticks/s) -host_mem_usage 250428 # Number of bytes of host memory used -host_seconds 12253.53 # Real time elapsed on the host +host_inst_rate 63436 # Simulator instruction rate (inst/s) +host_op_rate 116883 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45916521 # Simulator tick rate (ticks/s) +host_mem_usage 227532 # Number of bytes of host memory used +host_seconds 13872.75 # Real time elapsed on the host sim_insts 880025312 # Number of instructions simulated sim_ops 1621493982 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5834048 # Number of bytes read from this memory -system.physmem.bytes_inst_read 59200 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3731712 # Number of bytes written to this memory -system.physmem.num_reads 91157 # Number of read requests responded to by this memory -system.physmem.num_writes 58308 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9158798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 92937 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5858367 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 15017166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 59200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5774848 # Number of bytes read from this memory +system.physmem.bytes_read::total 5834048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 59200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 59200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3731712 # Number of bytes written to this memory +system.physmem.bytes_written::total 3731712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 925 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 90232 # Number of read requests responded to by this memory +system.physmem.num_reads::total 91157 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58308 # Number of write requests responded to by this memory +system.physmem.num_writes::total 58308 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 9065861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9158798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92937 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92937 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5858367 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5858367 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5858367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 9065861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15017166 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1273976766 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -322,11 +335,17 @@ system.cpu.icache.demand_accesses::total 186830267 # nu system.cpu.icache.overall_accesses::cpu.inst 186830267 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 186830267 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33672.202166 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 33672.202166 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 33672.202166 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 33672.202166 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 33672.202166 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,11 +373,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 32805000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32805000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 32805000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35085.561497 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35085.561497 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35085.561497 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35085.561497 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35085.561497 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35085.561497 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 445407 # number of replacements system.cpu.dcache.tagsinuse 4093.514636 # Cycle average of tags in use @@ -402,13 +427,21 @@ system.cpu.dcache.demand_accesses::total 453124365 # nu system.cpu.dcache.overall_accesses::cpu.data 453124365 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 453124365 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000780 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000780 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001308 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001308 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.001000 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001000 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001000 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001000 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10393.162559 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 10393.162559 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13094.918510 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13094.918510 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11861.789165 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 11861.789165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11861.789165 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -444,13 +477,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 3996172000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3996172000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 3996172000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000767 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000767 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001308 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001308 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000992 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000992 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7432.029905 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7432.029905 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10094.012234 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10094.012234 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8890.022958 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8890.022958 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8890.022958 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8890.022958 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 72883 # number of replacements system.cpu.l2cache.tagsinuse 17779.692577 # Cycle average of tags in use @@ -519,18 +560,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 449505 system.cpu.l2cache.overall_accesses::total 450433 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996767 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.156964 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.160780 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236882 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.236882 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996767 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.200736 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.202376 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996767 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.200736 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.202376 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34278.378378 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34292.077967 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34291.692045 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34267.939507 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34267.939507 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34278.378378 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34276.476195 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34276.495497 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34278.378378 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34276.476195 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34276.495497 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -565,18 +614,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2797343000 system.cpu.l2cache.overall_mshr_miss_latency::total 2826078500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.156964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.160780 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236882 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.202376 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996767 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200736 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202376 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.405405 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.525430 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.268608 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.660140 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.660140 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.405405 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.673464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31002.320173 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout index 87bcc8171..db4607fa4 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:08:17 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 14740711a..0e02ab2e6 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.963993 # Nu sim_ticks 963992704000 # Number of ticks simulated final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 688761 # Simulator instruction rate (inst/s) -host_op_rate 1269079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 754478822 # Simulator tick rate (ticks/s) -host_mem_usage 239576 # Number of bytes of host memory used -host_seconds 1277.69 # Real time elapsed on the host +host_inst_rate 1254577 # Simulator instruction rate (inst/s) +host_op_rate 2311626 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1374282564 # Simulator tick rate (ticks/s) +host_mem_usage 216676 # Number of bytes of host memory used +host_seconds 701.45 # Real time elapsed on the host sim_insts 880025313 # Number of instructions simulated sim_ops 1621493983 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 11334586825 # Number of bytes read from this memory -system.physmem.bytes_inst_read 9492133912 # Number of instructions bytes read from this memory -system.physmem.bytes_written 864451000 # Number of bytes written to this memory -system.physmem.num_reads 1605558864 # Number of read requests responded to by this memory -system.physmem.num_writes 188186057 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11757959140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 9846686466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 896740189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 12654699330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 9492133912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1842452913 # Number of bytes read from this memory +system.physmem.bytes_read::total 11334586825 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 9492133912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 9492133912 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 864451000 # Number of bytes written to this memory +system.physmem.bytes_written::total 864451000 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1186516739 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 419042125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1605558864 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 188186057 # Number of write requests responded to by this memory +system.physmem.num_writes::total 188186057 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 9846686466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1911272674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11757959140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9846686466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9846686466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 896740189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 896740189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9846686466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2808012863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12654699330 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1927985409 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout index 9ebad8844..7f0dbded6 100755 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:13:02 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 4294088ef..00ab9a331 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 1.803259 # Nu sim_ticks 1803258587000 # Number of ticks simulated final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 617600 # Simulator instruction rate (inst/s) -host_op_rate 1137962 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1265523884 # Simulator tick rate (ticks/s) -host_mem_usage 248496 # Number of bytes of host memory used -host_seconds 1424.91 # Real time elapsed on the host +host_inst_rate 587265 # Simulator instruction rate (inst/s) +host_op_rate 1082068 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1203364849 # Simulator tick rate (ticks/s) +host_mem_usage 225604 # Number of bytes of host memory used +host_seconds 1498.51 # Real time elapsed on the host sim_insts 880025313 # Number of instructions simulated sim_ops 1621493983 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 5725952 # Number of bytes read from this memory -system.physmem.bytes_inst_read 46208 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3712448 # Number of bytes written to this memory -system.physmem.num_reads 89468 # Number of read requests responded to by this memory -system.physmem.num_writes 58007 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3175336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 25625 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2058744 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 5234080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5679744 # Number of bytes read from this memory +system.physmem.bytes_read::total 5725952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3712448 # Number of bytes written to this memory +system.physmem.bytes_written::total 3712448 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 88746 # Number of read requests responded to by this memory +system.physmem.num_reads::total 89468 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58007 # Number of write requests responded to by this memory +system.physmem.num_writes::total 58007 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3149711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3175336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 25625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 25625 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2058744 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2058744 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2058744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3149711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5234080 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 3606517174 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 1186516740 # nu system.cpu.icache.overall_accesses::cpu.inst 1186516740 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1186516740 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 38266000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 437952 # number of replacements system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use @@ -152,13 +177,21 @@ system.cpu.dcache.demand_accesses::total 607228182 # nu system.cpu.dcache.overall_accesses::cpu.data 607228182 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 607228182 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001300 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20490.305383 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20490.305383 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23997.572756 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23997.572756 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22431.962140 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22431.962140 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,13 +219,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8589860000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8589860000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8589860000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17490.305383 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17490.305383 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20997.572756 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20997.572756 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 71208 # number of replacements system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use @@ -254,18 +295,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 442048 system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154531 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.157613 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238037 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.238037 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.200761 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.202064 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.200761 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.202064 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -300,18 +349,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3549840000 system.cpu.l2cache.overall_mshr_miss_latency::total 3578720000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.157613 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238037 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238037 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.202064 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202064 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |