diff options
Diffstat (limited to 'tests/long/se/00.gzip')
13 files changed, 3437 insertions, 2691 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 0e822db77..f322f4941 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.269669 # Number of seconds simulated -sim_ticks 269668883500 # Number of ticks simulated -final_tick 269668883500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.269772 # Number of seconds simulated +sim_ticks 269771922500 # Number of ticks simulated +final_tick 269771922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49435 # Simulator instruction rate (inst/s) -host_op_rate 49435 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22150100 # Simulator tick rate (ticks/s) -host_mem_usage 271532 # Number of bytes of host memory used -host_seconds 12174.61 # Real time elapsed on the host +host_inst_rate 152624 # Simulator instruction rate (inst/s) +host_op_rate 152624 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68411173 # Simulator tick rate (ticks/s) +host_mem_usage 225196 # Number of bytes of host memory used +host_seconds 3943.39 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6040712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6240305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 240651 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 240651 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 240651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6040712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6480955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6038405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6237921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 240559 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 240559 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 240559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6038405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6478480 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 26294 # Total number of read requests seen system.physmem.writeReqs 1014 # Total number of write requests seen system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady @@ -43,41 +43,41 @@ system.physmem.bytesConsumedRd 1682816 # by system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1624 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1676 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1558 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1549 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1582 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1650 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1710 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1672 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 59 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 49 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 58 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 74 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 59 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 70 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 78 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1672 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1579 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1680 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1732 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1812 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1867 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1778 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1658 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1444 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1493 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1505 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 70 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 71 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 70 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 82 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 95 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 79 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 54 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 64 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 89 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 35 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 33 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 38 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 48 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 269668831500 # Total gap between requests +system.physmem.totGap 269771850500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -92,11 +92,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 1014 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 16677 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1891 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 17534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1475 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,8 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see @@ -147,8 +147,8 @@ system.physmem.wrQLenPdf::19 44 # Wh system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -156,14 +156,96 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 383236250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1095312500 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 8692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 200.548550 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.216882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 827.235747 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 7745 89.10% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 118 1.36% 90.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 74 0.85% 91.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 56 0.64% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 40 0.46% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 23 0.26% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 20 0.23% 92.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 390 4.49% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 4 0.05% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 9 0.10% 97.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 7 0.08% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 0.07% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 2 0.02% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 4 0.05% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 7 0.08% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 4 0.05% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 3 0.03% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 2 0.02% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 1 0.01% 97.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 9 0.10% 98.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.01% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2 0.02% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.05% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.02% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.01% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 2 0.02% 98.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 3 0.03% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 4 0.05% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 3 0.03% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 4 0.05% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 3 0.03% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.01% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 3 0.03% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.01% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 2 0.02% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 2 0.02% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 2 0.02% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 2 0.02% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 4 0.05% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 2 0.02% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 2 0.02% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.02% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.01% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 2 0.02% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 3 0.03% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.01% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 3 0.03% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 1 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 2 0.02% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 1 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 2 0.02% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 1 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.02% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 4 0.05% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.02% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 44 0.51% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 9 0.10% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 5 0.06% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.02% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 11 0.13% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8577 2 0.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 8692 # Bytes accessed per row activation +system.physmem.totQLat 332225750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 999160750 # Sum of mem lat for all requests system.physmem.totBusLat 131400000 # Total cycles spent in databus access -system.physmem.totBankLat 580676250 # Total cycles spent in bank access -system.physmem.avgQLat 14582.81 # Average queueing delay per request -system.physmem.avgBankLat 22095.75 # Average bank access latency per request +system.physmem.totBankLat 535535000 # Total cycles spent in bank access +system.physmem.avgQLat 12641.77 # Average queueing delay per request +system.physmem.avgBankLat 20378.04 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41678.56 # Average memory access latency +system.physmem.avgMemAccLat 38019.82 # Average memory access latency system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s @@ -172,36 +254,52 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 12.19 # Average write queue length over time -system.physmem.readRowHits 16315 # Number of row buffer hits during reads -system.physmem.writeRowHits 296 # Number of row buffer hits during writes -system.physmem.readRowHitRate 62.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.19 # Row buffer hit rate for writes -system.physmem.avgGap 9875085.38 # Average gap between requests -system.cpu.branchPred.lookups 86401588 # Number of BP lookups -system.cpu.branchPred.condPredicted 81471319 # Number of conditional branches predicted +system.physmem.readRowHits 18015 # Number of row buffer hits during reads +system.physmem.writeRowHits 585 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.69 # Row buffer hit rate for writes +system.physmem.avgGap 9878857.86 # Average gap between requests +system.membus.throughput 6478480 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4966 # Transaction distribution +system.membus.trans_dist::ReadResp 4966 # Transaction distribution +system.membus.trans_dist::Writeback 1014 # Transaction distribution +system.membus.trans_dist::ReadExReq 21328 # Transaction distribution +system.membus.trans_dist::ReadExResp 21328 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 53602 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 53602 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1747712 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1747712 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1747712 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 40219500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 248608250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.branchPred.lookups 86401392 # Number of BP lookups +system.cpu.branchPred.condPredicted 81471121 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 36340860 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 45048223 # Number of BTB lookups -system.cpu.branchPred.BTBHits 34648139 # Number of BTB hits +system.cpu.branchPred.BTBLookups 45048026 # Number of BTB lookups +system.cpu.branchPred.BTBHits 34648141 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 76.913442 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 76.913783 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517866 # DTB read hits +system.cpu.dtb.read_hits 114525360 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520497 # DTB read accesses -system.cpu.dtb.write_hits 39453488 # DTB write hits +system.cpu.dtb.read_accesses 114527991 # DTB read accesses +system.cpu.dtb.write_hits 39455215 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39455790 # DTB write accesses -system.cpu.dtb.data_hits 153971354 # DTB hits +system.cpu.dtb.write_accesses 39457517 # DTB write accesses +system.cpu.dtb.data_hits 153980575 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153976287 # DTB accesses +system.cpu.dtb.data_accesses 153985508 # DTB accesses system.cpu.itb.fetch_hits 24966979 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -219,34 +317,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 539337768 # number of cpu cycles simulated +system.cpu.numCycles 539543846 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 37213741 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49187847 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541069811 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 37213743 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49187649 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541069671 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1004924657 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1004924517 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255160339 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 255160482 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 154930401 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 34118747 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 2217126 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 36335873 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 26212045 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 58.092858 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412134920 # Number of Instructions Executed. +system.cpu.execution_unit.executions 412134922 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 535759851 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 535782792 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 296128 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50805895 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 488531873 # Number of cycles cpu stages are processed. -system.cpu.activity 90.579949 # Percentage of cycles cpu is active +system.cpu.timesIdled 294264 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 51002909 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 488540937 # Number of cycles cpu stages are processed. +system.cpu.activity 90.547032 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -258,124 +356,144 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.896123 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.896465 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.896123 # CPI: Total CPI of All Threads -system.cpu.ipc 1.115918 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.896465 # CPI: Total CPI of All Threads +system.cpu.ipc 1.115492 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.115918 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 200608412 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338729356 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.804679 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 228909431 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310428337 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.557315 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 197773731 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341564037 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.330265 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 427958956 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111378812 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.651031 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 192540057 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 346797711 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.300654 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.115492 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 200810173 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338733673 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.781491 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 229113520 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310430326 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.535700 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 197979216 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341564630 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.306186 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 428164340 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111379506 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.643272 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 192742225 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346801621 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.276819 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 729.833568 # Cycle average of tags in use -system.cpu.icache.total_refs 24965946 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.672642 # Cycle average of tags in use +system.cpu.icache.total_refs 24965940 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29199.936842 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29199.929825 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 729.833568 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.356364 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.356364 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 24965946 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24965946 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24965946 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24965946 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24965946 # number of overall hits -system.cpu.icache.overall_hits::total 24965946 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1033 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1033 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1033 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1033 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1033 # number of overall misses -system.cpu.icache.overall_misses::total 1033 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 55677000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 55677000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 55677000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 55677000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 55677000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 55677000 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 729.672642 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.356285 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.356285 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24965940 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24965940 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24965940 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24965940 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24965940 # number of overall hits +system.cpu.icache.overall_hits::total 24965940 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1039 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1039 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1039 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1039 # number of overall misses +system.cpu.icache.overall_misses::total 1039 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 73110500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 73110500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 73110500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 73110500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 73110500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 73110500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 24966979 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 24966979 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 24966979 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 24966979 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 24966979 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 24966979 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53898.354308 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53898.354308 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53898.354308 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53898.354308 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53898.354308 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53898.354308 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70366.217517 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70366.217517 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70366.217517 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70366.217517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70366.217517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70366.217517 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 267 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 66.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 133.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 178 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 178 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 178 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 178 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 178 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 178 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 184 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 184 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 184 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 184 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45946500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45946500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45946500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45946500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45946500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45946500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60213000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 60213000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60213000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 60213000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60213000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 60213000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53738.596491 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53738.596491 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53738.596491 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53738.596491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53738.596491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53738.596491 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70424.561404 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70424.561404 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70424.561404 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70424.561404 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70424.561404 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70424.561404 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 211885535 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 202062 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 202062 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 436887 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 254188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 254188 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1710 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1347677 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1349387 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 57106048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 57160768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 57160768 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 883455500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1282500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 683092999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22879.137372 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22873.227488 # Cycle average of tags in use system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21684.500481 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 718.953671 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 475.683220 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21678.205650 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 718.794355 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 476.227482 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.661566 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021936 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014533 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.698036 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits @@ -400,17 +518,17 @@ system.cpu.l2cache.demand_misses::total 26294 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses system.cpu.l2cache.overall_misses::total 26294 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44941500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470659500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 515601000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1197956000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1197956000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 44941500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1668615500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1713557000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 44941500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1668615500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1713557000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 59208000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 554748000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 613956000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1528945500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1528945500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 59208000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2083693500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2142901500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 59208000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2083693500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2142901500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -435,17 +553,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.057631 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53438.168847 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.272727 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 103826.218284 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56168.229557 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56168.229557 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53438.168847 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65556.732016 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65169.126036 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53438.168847 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65556.732016 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65169.126036 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70401.902497 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 134484.363636 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 123631.896899 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71687.242123 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71687.242123 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70401.902497 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81864.357836 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81497.737126 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70401.902497 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81864.357836 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81497.737126 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -467,17 +585,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34505688 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418277231 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452782919 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 932478797 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 932478797 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34505688 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1350756028 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1385261716 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34505688 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1350756028 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1385261716 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48784500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 502370250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 551154750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1264256500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1264256500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48784500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1766626750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1815411250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48784500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1766626750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1815411250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses @@ -489,51 +607,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41029.355529 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101400.540848 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91176.584575 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43720.873828 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43720.873828 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41029.355529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53068.637410 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52683.567202 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41029.355529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53068.637410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52683.567202 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58007.728894 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 121786.727273 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 110985.652437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59276.842648 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59276.842648 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58007.728894 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69407.407771 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69042.794934 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58007.728894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69407.407771 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69042.794934 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.423663 # Cycle average of tags in use -system.cpu.dcache.total_refs 151786149 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4093.048176 # Cycle average of tags in use +system.cpu.dcache.total_refs 151792699 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 333.306578 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 332192000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.423663 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37665349 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37665349 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 151786149 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 151786149 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 151786149 # number of overall hits -system.cpu.dcache.overall_hits::total 151786149 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393242 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393242 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1785972 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1785972 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2179214 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2179214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2179214 # number of overall misses -system.cpu.dcache.overall_misses::total 2179214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984700000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5984700000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23169621500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23169621500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29154321500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29154321500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29154321500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29154321500 # number of overall miss cycles +system.cpu.dcache.avg_refs 333.320961 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 382930000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.048176 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999279 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999279 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114127941 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114127941 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37664758 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37664758 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 151792699 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 151792699 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 151792699 # number of overall hits +system.cpu.dcache.overall_hits::total 151792699 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 386101 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 386101 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1786563 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1786563 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2172664 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2172664 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2172664 # number of overall misses +system.cpu.dcache.overall_misses::total 2172664 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6056986500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6056986500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25183645000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25183645000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31240631500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31240631500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31240631500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31240631500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -542,40 +660,40 @@ system.cpu.dcache.demand_accesses::cpu.data 153965363 # system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003434 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003434 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045270 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045270 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014154 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014154 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15218.872857 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15218.872857 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.115760 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.115760 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.365548 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13378.365548 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.365548 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13378.365548 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 191067 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6052 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.570886 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 62.222222 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003372 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003372 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045285 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045285 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014111 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014111 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014111 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014111 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15687.570092 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15687.570092 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14096.141586 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14096.141586 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14378.952061 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14378.952061 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14378.952061 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14378.952061 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 376840 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 954 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17814 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.154148 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 95.400000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks system.cpu.dcache.writebacks::total 436887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192010 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192010 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531809 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1531809 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1723819 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1723819 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1723819 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1723819 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 184869 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 184869 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1532400 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1532400 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1717269 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1717269 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1717269 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1717269 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -584,14 +702,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643678500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643678500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782203500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782203500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6425882000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6425882000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6425882000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6425882000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2727636001 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2727636001 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4113048000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4113048000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6840684001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6840684001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6840684001 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6840684001 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -600,14 +718,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.465711 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.465711 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.015333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.015333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.567749 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.567749 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.567749 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.567749 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13554.683157 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13554.683157 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16182.717390 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16182.717390 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15021.429750 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15021.429750 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15021.429750 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15021.429750 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 1f1ca601b..8b45989c8 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133697 # Number of seconds simulated -sim_ticks 133696809500 # Number of ticks simulated -final_tick 133696809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133885 # Number of seconds simulated +sim_ticks 133884967500 # Number of ticks simulated +final_tick 133884967500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77616 # Simulator instruction rate (inst/s) -host_op_rate 77616 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18348551 # Simulator tick rate (ticks/s) -host_mem_usage 272684 # Number of bytes of host memory used -host_seconds 7286.51 # Real time elapsed on the host +host_inst_rate 162173 # Simulator instruction rate (inst/s) +host_op_rate 162173 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38391719 # Simulator tick rate (ticks/s) +host_mem_usage 228276 # Number of bytes of host memory used +host_seconds 3487.34 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1636544 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory -system.physmem.bytes_written::total 67072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 955 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25571 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26526 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 457154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12240711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12697865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 457154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 457154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 501672 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 501672 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 501672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 457154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12240711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13199537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26526 # Total number of read requests seen -system.physmem.writeReqs 1048 # Total number of write requests seen -system.physmem.cpureqs 27574 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697664 # Total number of bytes read from memory -system.physmem.bytesWritten 67072 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697664 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 61056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636160 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66944 # Number of bytes written to this memory +system.physmem.bytes_written::total 66944 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25565 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26519 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 456033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12220640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12676673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 456033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 456033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 500011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 500011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 500011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 456033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12220640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13176685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26519 # Total number of read requests seen +system.physmem.writeReqs 1046 # Total number of write requests seen +system.physmem.cpureqs 27565 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697216 # Total number of bytes read from memory +system.physmem.bytesWritten 66944 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 66944 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1631 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1680 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1627 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1648 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1676 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1684 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 58 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 53 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 64 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 75 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 73 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1678 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1699 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1739 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1730 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1813 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1787 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1459 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1505 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1515 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 64 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 61 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 71 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 72 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 73 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 82 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 95 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 80 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 54 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 65 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 90 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 35 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 34 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 44 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 52 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 133696776000 # Total gap between requests +system.physmem.totGap 133884902000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26526 # Categorize read packet sizes +system.physmem.readPktSize::6 26519 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1048 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 9044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5069 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1070 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 11989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 566 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,7 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see @@ -135,8 +135,8 @@ system.physmem.wrQLenPdf::7 46 # Wh system.physmem.wrQLenPdf::8 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see @@ -147,7 +147,7 @@ system.physmem.wrQLenPdf::19 45 # Wh system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -156,56 +156,157 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 652146750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1350583000 # Sum of mem lat for all requests -system.physmem.totBusLat 132555000 # Total cycles spent in databus access -system.physmem.totBankLat 565881250 # Total cycles spent in bank access -system.physmem.avgQLat 24599.10 # Average queueing delay per request -system.physmem.avgBankLat 21345.15 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 8244 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 213.286754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 86.643190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 848.319386 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 6744 81.80% 81.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 612 7.42% 89.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 105 1.27% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 71 0.86% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 43 0.52% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 25 0.30% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 16 0.19% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 389 4.72% 97.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 10 0.12% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 9 0.11% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 3 0.04% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 3 0.04% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.06% 97.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 0.10% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 9 0.11% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 7 0.08% 97.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 5 0.06% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.04% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 7 0.08% 97.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 6 0.07% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.05% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2 0.02% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 2 0.02% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.02% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 1 0.01% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 3 0.04% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 4 0.05% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 4 0.05% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.01% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 2 0.02% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.02% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 3 0.04% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.01% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.02% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 2 0.02% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.01% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.02% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.01% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.01% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 2 0.02% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 2 0.02% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 1 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 1 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.01% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 2 0.02% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 2 0.02% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 1 0.01% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.01% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 3 0.04% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.01% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 1 0.01% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.01% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 1 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.01% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.02% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.01% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 6 0.07% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.01% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 2 0.02% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 43 0.52% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 11 0.13% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 4 0.05% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 3 0.04% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 13 0.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 8244 # Bytes accessed per row activation +system.physmem.totQLat 457304500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1107883250 # Sum of mem lat for all requests +system.physmem.totBusLat 132520000 # Total cycles spent in databus access +system.physmem.totBankLat 518058750 # Total cycles spent in bank access +system.physmem.avgQLat 17254.17 # Average queueing delay per request +system.physmem.avgBankLat 19546.44 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 50944.25 # Average memory access latency -system.physmem.avgRdBW 12.70 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 41800.61 # Average memory access latency +system.physmem.avgRdBW 12.68 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 12.70 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 12.68 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.10 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 9.33 # Average write queue length over time -system.physmem.readRowHits 16975 # Number of row buffer hits during reads -system.physmem.writeRowHits 275 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 26.24 # Row buffer hit rate for writes -system.physmem.avgGap 4848653.66 # Average gap between requests -system.cpu.branchPred.lookups 76441752 # Number of BP lookups -system.cpu.branchPred.condPredicted 70864410 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2706781 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 43062122 # Number of BTB lookups -system.cpu.branchPred.BTBHits 41938047 # Number of BTB hits +system.physmem.avgWrQLen 7.87 # Average write queue length over time +system.physmem.readRowHits 18718 # Number of row buffer hits during reads +system.physmem.writeRowHits 577 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 55.16 # Row buffer hit rate for writes +system.physmem.avgGap 4857061.56 # Average gap between requests +system.membus.throughput 13176685 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 5255 # Transaction distribution +system.membus.trans_dist::ReadResp 5255 # Transaction distribution +system.membus.trans_dist::Writeback 1046 # Transaction distribution +system.membus.trans_dist::ReadExReq 21264 # Transaction distribution +system.membus.trans_dist::ReadExResp 21264 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 54084 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 54084 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1764160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1764160 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1764160 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 40437500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 246430250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu.branchPred.lookups 76481142 # Number of BP lookups +system.cpu.branchPred.condPredicted 70905485 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2712830 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 43152568 # Number of BTB lookups +system.cpu.branchPred.BTBHits 41951176 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.389643 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1605813 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 97.215943 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1604071 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 122608255 # DTB read hits -system.cpu.dtb.read_misses 28801 # DTB read misses +system.cpu.dtb.read_hits 122621956 # DTB read hits +system.cpu.dtb.read_misses 28776 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 122637056 # DTB read accesses -system.cpu.dtb.write_hits 40754827 # DTB write hits -system.cpu.dtb.write_misses 25617 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 40780444 # DTB write accesses -system.cpu.dtb.data_hits 163363082 # DTB hits -system.cpu.dtb.data_misses 54418 # DTB misses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 163417500 # DTB accesses -system.cpu.itb.fetch_hits 65484737 # ITB hits +system.cpu.dtb.read_accesses 122650732 # DTB read accesses +system.cpu.dtb.write_hits 40755113 # DTB write hits +system.cpu.dtb.write_misses 25625 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 40780738 # DTB write accesses +system.cpu.dtb.data_hits 163377069 # DTB hits +system.cpu.dtb.data_misses 54401 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 163431470 # DTB accesses +system.cpu.itb.fetch_hits 65530786 # ITB hits system.cpu.itb.fetch_misses 41 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 65484778 # ITB accesses +system.cpu.itb.fetch_accesses 65530827 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,133 +320,133 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267393620 # number of cpu cycles simulated +system.cpu.numCycles 267769936 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 67132788 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 699091920 # Number of instructions fetch has processed -system.cpu.fetch.Branches 76441752 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43543860 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 117791826 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11623941 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73287443 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65484737 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 927172 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 267096777 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.617373 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.445045 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 67189108 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 699431830 # Number of instructions fetch has processed +system.cpu.fetch.Branches 76481142 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43555247 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 117843991 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11666830 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73504935 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 68 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1313 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 19 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65530786 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 931341 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267451900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.615169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.444449 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 149304951 55.90% 55.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10344865 3.87% 59.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11847519 4.44% 64.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10566772 3.96% 68.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7010837 2.62% 70.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2867971 1.07% 71.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3579531 1.34% 73.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3103336 1.16% 74.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68470995 25.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149607909 55.94% 55.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10348918 3.87% 59.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11847203 4.43% 64.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10573344 3.95% 68.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7008253 2.62% 70.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2869794 1.07% 71.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3587132 1.34% 73.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3111076 1.16% 74.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68498271 25.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 267096777 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285877 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.614467 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 84255179 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57589844 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102698571 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13670600 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8882583 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3874487 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 931 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 691126555 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3231 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8882583 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 92229912 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12770086 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1212 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 103061748 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50151236 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 680987279 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 426 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38480754 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5456693 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 520711815 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 896998441 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 896995902 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2539 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267451900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285623 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.612063 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 84322843 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57802490 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102700565 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13714405 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8911597 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3873381 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 948 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 691440481 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3137 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8911597 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 92312573 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12823003 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1534 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 103090752 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50312441 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 681258889 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 435 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38630282 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5470230 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 520856634 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 897283230 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 897280730 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2500 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 56856926 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 56 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 61 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112143528 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 126973457 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42377854 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14839100 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10235293 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 621082747 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 48 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 604577802 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 299631 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 54891737 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29918454 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 31 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 267096777 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.263516 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.822324 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 57001745 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 66 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 72 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112491401 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 126996487 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42388542 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14811954 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10030949 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 621209385 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 604684391 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 299599 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 55017699 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29989465 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267451900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.260909 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.823825 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52289348 19.58% 19.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55783537 20.89% 40.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53427937 20.00% 60.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36631888 13.71% 74.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31292246 11.72% 85.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23678415 8.87% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10025583 3.75% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3414414 1.28% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 553409 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52525807 19.64% 19.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 56031435 20.95% 40.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53465406 19.99% 60.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36379699 13.60% 74.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31195818 11.66% 85.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23840953 8.91% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10047725 3.76% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3411796 1.28% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 553261 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 267096777 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267451900 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2692091 70.58% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 42 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 729838 19.13% 89.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 392410 10.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2753778 71.24% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 45 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 726781 18.80% 90.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 385136 9.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 439064264 72.62% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7069 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439140797 72.62% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7079 0.00% 72.62% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued @@ -373,84 +474,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 124327148 20.56% 93.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41179273 6.81% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124346650 20.56% 93.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41189817 6.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 604577802 # Type of FU issued -system.cpu.iq.rate 2.261003 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3814381 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006309 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1480362706 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 675977802 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 596495784 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3687 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2189 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1715 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 608390320 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1863 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12281051 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 604684391 # Type of FU issued +system.cpu.iq.rate 2.258224 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3865740 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006393 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1480982314 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 676230303 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 596557394 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3707 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2213 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1724 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 608548258 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1873 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12279987 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12459415 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 35750 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5512 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2926533 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12482445 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36037 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5437 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2937221 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6468 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 56300 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6392 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 65545 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8882583 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1439479 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 190555 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 663921502 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1696631 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 126973457 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42377854 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 142659 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7414 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5512 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1334753 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1804223 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3138976 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599473269 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 122637223 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5104533 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8911597 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1457895 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 191973 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 664097895 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1705444 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 126996487 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42388542 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 56 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 144321 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7199 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5437 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1338458 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1807769 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3146227 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599553495 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 122650887 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5130896 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 42838707 # number of nop insts executed -system.cpu.iew.exec_refs 163435917 # number of memory reference insts executed -system.cpu.iew.exec_branches 66623579 # Number of branches executed -system.cpu.iew.exec_stores 40798694 # Number of stores executed -system.cpu.iew.exec_rate 2.241913 # Inst execution rate -system.cpu.iew.wb_sent 597432372 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 596497499 # cumulative count of insts written-back -system.cpu.iew.wb_producers 415924305 # num instructions producing a value -system.cpu.iew.wb_consumers 530247239 # num instructions consuming a value +system.cpu.iew.exec_nop 42888454 # number of nop insts executed +system.cpu.iew.exec_refs 163450221 # number of memory reference insts executed +system.cpu.iew.exec_branches 66634078 # Number of branches executed +system.cpu.iew.exec_stores 40799334 # Number of stores executed +system.cpu.iew.exec_rate 2.239062 # Inst execution rate +system.cpu.iew.wb_sent 597495724 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 596559118 # cumulative count of insts written-back +system.cpu.iew.wb_producers 415919830 # num instructions producing a value +system.cpu.iew.wb_consumers 530239470 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.230784 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.784397 # average fanout of values written-back +system.cpu.iew.wb_rate 2.227879 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.784400 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 61940872 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 62116663 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2705903 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258214194 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.330844 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.692748 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2711961 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258540303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.327904 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.691623 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 79436879 30.76% 30.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72473576 28.07% 58.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25624236 9.92% 68.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9154468 3.55% 72.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10267531 3.98% 76.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 21039855 8.15% 84.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6818360 2.64% 87.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3702360 1.43% 88.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29696929 11.50% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79687582 30.82% 30.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72573675 28.07% 58.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25533783 9.88% 68.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9229698 3.57% 72.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10307338 3.99% 76.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20995746 8.12% 84.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6840090 2.65% 87.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3701122 1.43% 88.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29671269 11.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258214194 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 258540303 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,192 +562,212 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29696929 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29671269 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 892250711 # The number of ROB reads -system.cpu.rob.rob_writes 1336492363 # The number of ROB writes -system.cpu.timesIdled 34289 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 296843 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 892778271 # The number of ROB reads +system.cpu.rob.rob_writes 1336872912 # The number of ROB writes +system.cpu.timesIdled 34547 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 318036 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.472801 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.472801 # CPI: Total CPI of All Threads -system.cpu.ipc 2.115056 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.115056 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 844981893 # number of integer regfile reads -system.cpu.int_regfile_writes 490535855 # number of integer regfile writes -system.cpu.fp_regfile_reads 379 # number of floating regfile reads +system.cpu.cpi 0.473466 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.473466 # CPI: Total CPI of All Threads +system.cpu.ipc 2.112083 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.112083 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 845093769 # number of integer regfile reads +system.cpu.int_regfile_writes 490581182 # number of integer regfile writes +system.cpu.fp_regfile_reads 382 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 39 # number of replacements -system.cpu.icache.tagsinuse 825.626517 # Cycle average of tags in use -system.cpu.icache.total_refs 65483355 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 973 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67300.467626 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 435443419 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 211400 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 211400 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 444967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 254560 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 254560 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1944 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1374943 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1376887 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 58237120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 58299328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 58299328 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 900430500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1458499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 697482499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.cpu.icache.replacements 40 # number of replacements +system.cpu.icache.tagsinuse 824.576664 # Cycle average of tags in use +system.cpu.icache.total_refs 65529394 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 972 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67417.072016 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 825.626517 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.403138 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.403138 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 65483355 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 65483355 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 65483355 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 65483355 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 65483355 # number of overall hits -system.cpu.icache.overall_hits::total 65483355 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1381 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1381 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1381 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1381 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1381 # number of overall misses -system.cpu.icache.overall_misses::total 1381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 73729000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 73729000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 73729000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 73729000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 73729000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 73729000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65484736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65484736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65484736 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65484736 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65484736 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65484736 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 824.576664 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.402625 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.402625 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 65529394 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 65529394 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 65529394 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 65529394 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 65529394 # number of overall hits +system.cpu.icache.overall_hits::total 65529394 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1391 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1391 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1391 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1391 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1391 # number of overall misses +system.cpu.icache.overall_misses::total 1391 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 90149500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 90149500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 90149500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 90149500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 90149500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 90149500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 65530785 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 65530785 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 65530785 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 65530785 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 65530785 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 65530785 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53388.124547 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53388.124547 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53388.124547 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53388.124547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53388.124547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53388.124547 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64809.130122 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64809.130122 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64809.130122 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64809.130122 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64809.130122 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64809.130122 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 33.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 58.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 408 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 408 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 408 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 408 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 408 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 408 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 973 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 973 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 973 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 973 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 973 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 973 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54179000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54179000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54179000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54179000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54179000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54179000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 419 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 419 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 419 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 419 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 419 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 419 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 972 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 972 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 972 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 972 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 972 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 972 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 66407501 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 66407501 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 66407501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 66407501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 66407501 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 66407501 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55682.425488 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55682.425488 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55682.425488 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55682.425488 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55682.425488 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55682.425488 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68320.474280 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68320.474280 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68320.474280 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68320.474280 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68320.474280 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68320.474280 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1081 # number of replacements -system.cpu.l2cache.tagsinuse 22922.098360 # Cycle average of tags in use -system.cpu.l2cache.total_refs 547070 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23518 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.261757 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1077 # number of replacements +system.cpu.l2cache.tagsinuse 22914.008377 # Cycle average of tags in use +system.cpu.l2cache.total_refs 547130 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23515 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.267276 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21473.132839 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 816.078621 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 632.886901 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.655308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.024905 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019314 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.699527 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21467.928297 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 816.924139 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 629.155942 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.655149 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.024931 # 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average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460841 # number of replacements -system.cpu.dcache.tagsinuse 4090.895658 # Cycle average of tags in use -system.cpu.dcache.total_refs 146899681 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 464937 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 315.956099 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 301835000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4090.895658 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998754 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998754 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 109250298 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 109250298 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37649372 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37649372 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 146899670 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 146899670 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 146899670 # number of overall hits -system.cpu.dcache.overall_hits::total 146899670 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1022486 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1022486 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1801949 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1801949 # number of WriteReq misses +system.cpu.dcache.replacements 460892 # number of replacements +system.cpu.dcache.tagsinuse 4090.586607 # Cycle average of tags in use +system.cpu.dcache.total_refs 146918843 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 464988 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 315.962655 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 315391000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4090.586607 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998678 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998678 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 109270363 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 109270363 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37648463 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37648463 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 17 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 17 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 146918826 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 146918826 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 146918826 # number of overall hits +system.cpu.dcache.overall_hits::total 146918826 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1007750 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1007750 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1802858 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1802858 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2824435 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2824435 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2824435 # number of overall misses -system.cpu.dcache.overall_misses::total 2824435 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15308231000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15308231000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26204381408 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26204381408 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2810608 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2810608 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2810608 # number of overall misses +system.cpu.dcache.overall_misses::total 2810608 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15255049500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15255049500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27585273680 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27585273680 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 48500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 48500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41512612408 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41512612408 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41512612408 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41512612408 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 110272784 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 110272784 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 42840323180 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42840323180 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42840323180 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42840323180 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 110278113 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 110278113 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 149724105 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 149724105 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 149724105 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 149724105 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009272 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009272 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045675 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045675 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.312500 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.312500 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018864 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018864 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018864 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018864 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14971.580051 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14971.580051 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14542.243653 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14542.243653 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 149729434 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 149729434 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 149729434 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 149729434 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009138 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009138 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045698 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045698 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.227273 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.227273 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018771 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018771 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018771 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018771 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15137.732076 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15137.732076 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15300.857683 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15300.857683 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9700 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9700 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14697.669590 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14697.669590 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14697.669590 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14697.669590 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 306629 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2099 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 18462 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.608656 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 190.818182 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15242.368619 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15242.368619 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15242.368619 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15242.368619 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 382457 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1107 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 20340 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.803196 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 92.250000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 444926 # number of writebacks -system.cpu.dcache.writebacks::total 444926 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 812044 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 812044 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1547454 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1547454 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 444967 # number of writebacks +system.cpu.dcache.writebacks::total 444967 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 797322 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 797322 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548298 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1548298 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2359498 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2359498 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2359498 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2359498 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210442 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210442 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254495 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254495 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 464937 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 464937 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 464937 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 464937 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2697776000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2697776000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4104342498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4104342498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6802118498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6802118498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6802118498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6802118498 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 2345620 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2345620 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2345620 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2345620 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210428 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210428 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254560 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254560 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464988 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464988 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464988 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464988 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2709117501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2709117501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357981491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357981491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7067098992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7067098992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7067098992 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7067098992 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001908 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001908 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003105 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003105 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12819.570238 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12819.570238 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16127.399352 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16127.399352 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14630.193979 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14630.193979 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14630.193979 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14630.193979 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003106 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003106 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.320437 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.320437 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17119.663305 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17119.663305 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15198.454567 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15198.454567 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15198.454567 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15198.454567 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index 0780eabd0..fbf28575b 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.300931 # Nu sim_ticks 300930958000 # Number of ticks simulated final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2641824 # Simulator instruction rate (inst/s) -host_op_rate 2641824 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1320922836 # Simulator tick rate (ticks/s) -host_mem_usage 264040 # Number of bytes of host memory used -host_seconds 227.82 # Real time elapsed on the host +host_inst_rate 3984763 # Simulator instruction rate (inst/s) +host_op_rate 3984763 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1992397518 # Simulator tick rate (ticks/s) +host_mem_usage 217612 # Number of bytes of host memory used +host_seconds 151.04 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 507324022 # Wr system.physmem.bw_total::cpu.inst 7999999747 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1755262561 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9755262308 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9755262308 # Throughput (bytes/s) +system.membus.data_through_bus 2935660432 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 19cf772df..52085a7cc 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.762403 # Nu sim_ticks 762403375000 # Number of ticks simulated final_tick 762403375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1151537 # Simulator instruction rate (inst/s) -host_op_rate 1151537 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1458711281 # Simulator tick rate (ticks/s) -host_mem_usage 272496 # Number of bytes of host memory used -host_seconds 522.66 # Real time elapsed on the host +host_inst_rate 1417339 # Simulator instruction rate (inst/s) +host_op_rate 1417339 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1795416637 # Simulator tick rate (ticks/s) +host_mem_usage 225056 # Number of bytes of host memory used +host_seconds 424.64 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 84449 # To system.physmem.bw_total::cpu.inst 65729 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2136486 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2286664 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 2286664 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4910 # Transaction distribution +system.membus.trans_dist::ReadResp 4910 # Transaction distribution +system.membus.trans_dist::Writeback 1006 # Transaction distribution +system.membus.trans_dist::ReadExReq 21324 # Transaction distribution +system.membus.trans_dist::ReadExResp 21324 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 53474 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 53474 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1743360 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1743360 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1743360 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 35288000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 236106000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -405,5 +421,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.298499 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 74969406 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 202027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 202027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 436887 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 254163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 254163 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1590 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1347677 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1349267 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 57106048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 57156928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 57156928 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 883425500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1192500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 683092500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 595117ec0..01544a32c 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164563 # Number of seconds simulated -sim_ticks 164562530500 # Number of ticks simulated -final_tick 164562530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164717 # Number of seconds simulated +sim_ticks 164716794500 # Number of ticks simulated +final_tick 164716794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62422 # Simulator instruction rate (inst/s) -host_op_rate 65960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18020016 # Simulator tick rate (ticks/s) -host_mem_usage 288128 # Number of bytes of host memory used -host_seconds 9132.21 # Real time elapsed on the host +host_inst_rate 131424 # Simulator instruction rate (inst/s) +host_op_rate 138873 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37975042 # Simulator tick rate (ticks/s) +host_mem_usage 246336 # Number of bytes of host memory used +host_seconds 4337.50 # Real time elapsed on the host sim_insts 570051585 # Number of instructions simulated sim_ops 602359791 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 46976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1701120 # Number of bytes read from this memory -system.physmem.bytes_read::total 1748096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 46976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 46976 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 47232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1701568 # Number of bytes read from this memory +system.physmem.bytes_read::total 1748800 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47232 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory system.physmem.bytes_written::total 162368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26580 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27314 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 738 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26587 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27325 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 285460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10337226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10622685 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 285460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 285460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 986664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 986664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 986664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 285460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10337226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11609350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27315 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 286747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10330264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10617011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 286747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 286747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 985740 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 985740 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 985740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 286747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10330264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11602751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27326 # Total number of read requests seen system.physmem.writeReqs 2537 # Total number of write requests seen -system.physmem.cpureqs 29852 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1748096 # Total number of bytes read from memory +system.physmem.cpureqs 29863 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1748800 # Total number of bytes read from memory system.physmem.bytesWritten 162368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1748096 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1748800 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1691 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1726 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1687 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1696 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1735 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1759 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1740 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1680 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 163 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1621 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1738 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1816 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1755 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1757 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1715 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1788 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1779 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1795 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1647 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 166 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 158 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 164562514500 # Total gap between requests +system.physmem.totGap 164716777500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27315 # Categorize read packet sizes +system.physmem.readPktSize::6 27326 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,12 +92,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 2537 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 14709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,8 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see @@ -147,8 +147,8 @@ system.physmem.wrQLenPdf::19 110 # Wh system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -156,14 +156,87 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 922192000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1672085750 # Sum of mem lat for all requests -system.physmem.totBusLat 136575000 # Total cycles spent in databus access -system.physmem.totBankLat 613318750 # Total cycles spent in bank access -system.physmem.avgQLat 33761.38 # Average queueing delay per request -system.physmem.avgBankLat 22453.55 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 9336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 204.188518 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 86.332799 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 802.540236 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 7834 83.91% 83.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 317 3.40% 87.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 190 2.04% 89.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 83 0.89% 90.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 60 0.64% 90.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 70 0.75% 91.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 60 0.64% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 493 5.28% 97.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 6 0.06% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 7 0.07% 97.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 3 0.03% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 4 0.04% 97.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 3 0.03% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 4 0.04% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.05% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 7 0.07% 97.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 5 0.05% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 5 0.05% 98.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.04% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 6 0.06% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.01% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2 0.02% 98.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.01% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 4 0.04% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.03% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.02% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.02% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 7 0.07% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 2 0.02% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.02% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 4 0.04% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.01% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.01% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.01% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.01% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.01% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 5 0.05% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 1 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 3 0.03% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.01% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 4 0.04% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.02% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 6 0.06% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 7 0.07% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 2 0.02% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 4 0.04% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 2 0.02% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.04% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.02% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.03% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.02% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 1 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 6 0.06% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 4 0.04% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 3 0.03% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 60 0.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 9336 # Bytes accessed per row activation +system.physmem.totQLat 724618250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1428985750 # Sum of mem lat for all requests +system.physmem.totBusLat 136630000 # Total cycles spent in databus access +system.physmem.totBankLat 567737500 # Total cycles spent in bank access +system.physmem.avgQLat 26517.54 # Average queueing delay per request +system.physmem.avgBankLat 20776.46 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 61214.93 # Average memory access latency +system.physmem.avgMemAccLat 52294.00 # Average memory access latency system.physmem.avgRdBW 10.62 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 10.62 # Average consumed read bandwidth in MB/s @@ -171,21 +244,37 @@ system.physmem.avgConsumedWrBW 0.99 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 5.61 # Average write queue length over time -system.physmem.readRowHits 16878 # Number of row buffer hits during reads -system.physmem.writeRowHits 1046 # Number of row buffer hits during writes -system.physmem.readRowHitRate 61.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.23 # Row buffer hit rate for writes -system.physmem.avgGap 5512612.71 # Average gap between requests -system.cpu.branchPred.lookups 85150983 # Number of BP lookups -system.cpu.branchPred.condPredicted 79934550 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2340692 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 47125153 # Number of BTB lookups -system.cpu.branchPred.BTBHits 46874770 # Number of BTB hits +system.physmem.avgWrQLen 5.04 # Average write queue length over time +system.physmem.readRowHits 18612 # Number of row buffer hits during reads +system.physmem.writeRowHits 1908 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.21 # Row buffer hit rate for writes +system.physmem.avgGap 5515747.83 # Average gap between requests +system.membus.throughput 11602751 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 5535 # Transaction distribution +system.membus.trans_dist::ReadResp 5534 # Transaction distribution +system.membus.trans_dist::Writeback 2537 # Transaction distribution +system.membus.trans_dist::ReadExReq 21791 # Transaction distribution +system.membus.trans_dist::ReadExResp 21791 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 57188 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 57188 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1911168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1911168 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1911168 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 59882500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 257832500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu.branchPred.lookups 85149850 # Number of BP lookups +system.cpu.branchPred.condPredicted 79935034 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2341119 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 47171100 # Number of BTB lookups +system.cpu.branchPred.BTBHits 46877755 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.468685 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1426734 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1006 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.378126 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1426315 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1039 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,134 +318,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329125062 # number of cpu cycles simulated +system.cpu.numCycles 329433590 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 68488081 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 666859732 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85150983 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48301504 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 129623989 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13095310 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119330996 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 68491080 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 666869934 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85149850 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48304070 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 129626718 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13098656 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119406737 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 265 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 67073182 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 755353 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 328169942 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.165410 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.193997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 278 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 67075214 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 755042 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 328254094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.164915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.193789 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 198546194 60.50% 60.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20910126 6.37% 66.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4967453 1.51% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14343462 4.37% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8888191 2.71% 75.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9444820 2.88% 78.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4399595 1.34% 79.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5788141 1.76% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 60881960 18.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198627609 60.51% 60.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20909439 6.37% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4965485 1.51% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14345312 4.37% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8888539 2.71% 75.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9448384 2.88% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4398392 1.34% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5788124 1.76% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 60882810 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 328169942 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258719 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.026159 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 92898933 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96237751 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 107895398 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20412735 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10725125 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4735181 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1555 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703255584 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5767 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10725125 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107098247 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14386106 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 39798 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114033717 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81886949 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 694825042 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59412332 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20333868 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 677 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 721309974 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3230585653 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3230585525 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 328254094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258473 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.024292 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92927462 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96288420 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 107921370 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20389102 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10727740 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4734116 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1608 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703272688 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6032 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10727740 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107129786 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14463787 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40672 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114031737 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81860372 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 694842750 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 61 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59365311 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20352093 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 658 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 721318867 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3230668466 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3230668338 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 93892601 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1652 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1598 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 170754110 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172203089 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80461729 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21612175 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28771400 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 679988719 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2878 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 645594653 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1373062 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 77449325 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 193321568 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 174 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 328169942 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.967257 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.725062 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 93901494 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1663 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1606 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 170675033 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172203367 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80466872 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21668199 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28984539 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 680005400 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2870 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 645602000 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1370838 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 77464153 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 193377702 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 328254094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.966775 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.724168 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68186439 20.78% 20.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85247300 25.98% 46.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75946350 23.14% 69.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40813735 12.44% 82.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28838397 8.79% 91.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14924394 4.55% 95.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5564389 1.70% 97.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6539948 1.99% 99.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2108990 0.64% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68222380 20.78% 20.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85248644 25.97% 46.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76005248 23.15% 69.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40782290 12.42% 82.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28865696 8.79% 91.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14929305 4.55% 95.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5554109 1.69% 97.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6609349 2.01% 99.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2037073 0.62% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 328169942 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328254094 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 216923 5.73% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2702396 71.39% 77.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 865914 22.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 217031 5.77% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2685741 71.41% 77.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 858362 22.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403371824 62.48% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6559 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403375767 62.48% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6562 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued @@ -384,84 +473,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 165561293 25.64% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76654974 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 165561645 25.64% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76658023 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 645594653 # Type of FU issued -system.cpu.iq.rate 1.961548 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3785233 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005863 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624517507 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 757453052 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 637549292 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 645602000 # Type of FU issued +system.cpu.iq.rate 1.959733 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3761134 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005826 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624590030 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 757484567 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 637551440 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 649379866 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 649363114 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30368159 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30365020 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23250496 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 123413 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12359 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10240716 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23250774 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 122077 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12388 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10245859 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12899 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 36224 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12881 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 36063 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10725125 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 795867 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 92517 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 679994676 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 687635 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172203089 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80461729 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1550 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 32824 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16429 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12359 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1356301 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1461196 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2817497 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 641509024 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163485499 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4085629 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10727740 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 829837 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 90327 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 680011324 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 689748 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172203367 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80466872 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1542 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 33020 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14329 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12388 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1357418 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1460538 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2817956 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 641515531 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163488286 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4086469 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3079 # number of nop insts executed -system.cpu.iew.exec_refs 239366742 # number of memory reference insts executed -system.cpu.iew.exec_branches 74672084 # Number of branches executed -system.cpu.iew.exec_stores 75881243 # Number of stores executed -system.cpu.iew.exec_rate 1.949135 # Inst execution rate -system.cpu.iew.wb_sent 638953926 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 637549308 # cumulative count of insts written-back -system.cpu.iew.wb_producers 418527294 # num instructions producing a value -system.cpu.iew.wb_consumers 649860425 # num instructions consuming a value +system.cpu.iew.exec_nop 3054 # number of nop insts executed +system.cpu.iew.exec_refs 239371647 # number of memory reference insts executed +system.cpu.iew.exec_branches 74671273 # Number of branches executed +system.cpu.iew.exec_stores 75883361 # Number of stores executed +system.cpu.iew.exec_rate 1.947329 # Inst execution rate +system.cpu.iew.wb_sent 638961836 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 637551456 # cumulative count of insts written-back +system.cpu.iew.wb_producers 418605320 # num instructions producing a value +system.cpu.iew.wb_consumers 649951687 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937103 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644026 # average fanout of values written-back +system.cpu.iew.wb_rate 1.935296 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644056 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 77643008 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 77660016 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2339215 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 317444817 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.897526 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.237559 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2339596 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 317526354 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.897039 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.237311 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93252713 29.38% 29.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104341557 32.87% 62.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42984071 13.54% 75.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8786627 2.77% 78.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25947006 8.17% 86.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12913913 4.07% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7624115 2.40% 93.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1170537 0.37% 93.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20424278 6.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93315961 29.39% 29.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104358414 32.87% 62.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42989043 13.54% 75.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8780083 2.77% 78.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25952112 8.17% 86.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12911096 4.07% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7631938 2.40% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1174119 0.37% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20413588 6.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 317444817 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 317526354 # Number of insts commited each cycle system.cpu.commit.committedInsts 570051636 # Number of instructions committed system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,191 +561,217 @@ system.cpu.commit.branches 70892524 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 533522631 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20424278 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20413588 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 977022777 # The number of ROB reads -system.cpu.rob.rob_writes 1370762747 # The number of ROB writes -system.cpu.timesIdled 43954 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 955120 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 977132012 # The number of ROB reads +system.cpu.rob.rob_writes 1370799549 # The number of ROB writes +system.cpu.timesIdled 46711 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1179496 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 570051585 # Number of Instructions Simulated system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated -system.cpu.cpi 0.577360 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.577360 # CPI: Total CPI of All Threads -system.cpu.ipc 1.732021 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.732021 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3204272502 # number of integer regfile reads -system.cpu.int_regfile_writes 663034338 # number of integer regfile writes +system.cpu.cpi 0.577901 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.577901 # CPI: Total CPI of All Threads +system.cpu.ipc 1.730399 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.730399 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3204308856 # number of integer regfile reads +system.cpu.int_regfile_writes 663036750 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 234758554 # number of misc regfile reads +system.cpu.misc_regfile_reads 234764578 # number of misc regfile reads system.cpu.misc_regfile_writes 2656 # number of misc regfile writes -system.cpu.icache.replacements 49 # number of replacements -system.cpu.icache.tagsinuse 688.587828 # Cycle average of tags in use -system.cpu.icache.total_refs 67072069 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 83009.986386 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 336903691 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 198317 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 198316 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 421602 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247171 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1633 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1310945 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1312578 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 52224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 55441408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 55493632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 55493632 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 855147500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1225999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 667010989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.cpu.icache.replacements 51 # number of replacements +system.cpu.icache.tagsinuse 691.196113 # Cycle average of tags in use +system.cpu.icache.total_refs 67074062 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 816 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 82198.605392 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 688.587828 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.336225 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.336225 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67072069 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67072069 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67072069 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67072069 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67072069 # number of overall hits -system.cpu.icache.overall_hits::total 67072069 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1113 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1113 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1113 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1113 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1113 # number of overall misses -system.cpu.icache.overall_misses::total 1113 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 54408499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 54408499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 54408499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 54408499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 54408499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 54408499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67073182 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67073182 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67073182 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67073182 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67073182 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67073182 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 691.196113 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.337498 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.337498 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67074062 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67074062 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67074062 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67074062 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67074062 # number of overall hits +system.cpu.icache.overall_hits::total 67074062 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1152 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1152 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1152 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1152 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1152 # number of overall misses +system.cpu.icache.overall_misses::total 1152 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 71751999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 71751999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 71751999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 71751999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 71751999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 71751999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67075214 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67075214 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67075214 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67075214 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67075214 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67075214 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48884.545373 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48884.545373 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48884.545373 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48884.545373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48884.545373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48884.545373 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 288 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62284.721354 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62284.721354 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62284.721354 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62284.721354 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62284.721354 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62284.721354 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.142857 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 61.857143 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 304 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 304 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 304 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 304 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 304 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 304 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 809 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 809 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 809 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 809 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 809 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 809 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42322999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42322999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42322999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42322999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42322999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42322999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 335 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 335 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 335 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 335 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 335 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 817 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 817 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 817 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 817 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 817 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 817 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53391000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 53391000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53391000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 53391000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53391000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 53391000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52315.202719 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52315.202719 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52315.202719 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52315.202719 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52315.202719 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52315.202719 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65350.061200 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65350.061200 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65350.061200 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 65350.061200 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65350.061200 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 65350.061200 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2559 # number of replacements -system.cpu.l2cache.tagsinuse 22357.775190 # Cycle average of tags in use -system.cpu.l2cache.total_refs 517077 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24151 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.410169 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22356.312317 # Cycle average of tags in use +system.cpu.l2cache.total_refs 517275 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24166 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.405073 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20763.745562 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 648.701789 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 945.327839 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633659 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.019797 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.028849 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.682305 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 74 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 192736 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 192810 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 421641 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 421641 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 225382 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 225382 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 74 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 418118 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 418192 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 74 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 418118 # number of overall hits -system.cpu.l2cache.overall_hits::total 418192 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 735 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088162 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.088162 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.905637 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.059815 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.061364 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.905637 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.059815 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.061364 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70077.131258 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 148662.991471 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 138191.489362 # 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number of cycles access was blocked @@ -668,168 +783,168 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 2537 # number of writebacks system.cpu.l2cache.writebacks::total 2537 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 11 # 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number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1326 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1326 # number of LoadLockedReq hits +system.cpu.dcache.replacements 440574 # number of replacements +system.cpu.dcache.tagsinuse 4091.363669 # Cycle average of tags in use +system.cpu.dcache.total_refs 197559820 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444670 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 444.284121 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 321256000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4091.363669 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998868 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998868 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 131518279 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 131518279 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 66038889 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 66038889 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1323 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1323 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 197559804 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 197559804 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 197559804 # number of overall hits -system.cpu.dcache.overall_hits::total 197559804 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 341685 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 341685 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3370037 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3370037 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3711722 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3711722 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3711722 # number of overall misses -system.cpu.dcache.overall_misses::total 3711722 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5064964500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5064964500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 40707637762 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 40707637762 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 338000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 338000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45772602262 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45772602262 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45772602262 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45772602262 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 131853995 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 131853995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 197557168 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 197557168 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 197557168 # number of overall hits +system.cpu.dcache.overall_hits::total 197557168 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 341807 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 341807 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3378642 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3378642 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3720449 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3720449 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3720449 # number of overall misses +system.cpu.dcache.overall_misses::total 3720449 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5118261000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5118261000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 44228568380 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 44228568380 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 392500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 392500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 49346829380 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 49346829380 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 49346829380 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 49346829380 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131860086 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131860086 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1348 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1348 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1346 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1346 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201271526 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201271526 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201271526 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201271526 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002591 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002591 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048547 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.048547 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016320 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016320 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018441 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018441 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018441 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018441 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14823.490935 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14823.490935 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12079.285112 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12079.285112 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15363.636364 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15363.636364 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12331.904777 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12331.904777 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12331.904777 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12331.904777 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 146535 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 32 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5250 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 201277617 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201277617 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201277617 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201277617 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002592 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002592 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048671 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.048671 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017088 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017088 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018484 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018484 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018484 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018484 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14974.125749 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14974.125749 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13090.634752 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13090.634752 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17065.217391 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17065.217391 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13263.675804 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13263.675804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13263.675804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13263.675804 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 148047 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 158 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5424 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.911429 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.294801 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421641 # number of writebacks -system.cpu.dcache.writebacks::total 421641 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144151 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 144151 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3122863 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3122863 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3267014 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3267014 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3267014 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3267014 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197534 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197534 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247174 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247174 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444708 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444708 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444708 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444708 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2832398000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2832398000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4097760821 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4097760821 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6930158821 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6930158821 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6930158821 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6930158821 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 421602 # number of writebacks +system.cpu.dcache.writebacks::total 421602 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144306 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 144306 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3131471 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3131471 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 23 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 23 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3275777 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3275777 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3275777 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3275777 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197501 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197501 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247171 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247171 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444672 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444672 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444672 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444672 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2858072011 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2858072011 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4363789439 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4363789439 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7221861450 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7221861450 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7221861450 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7221861450 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses @@ -838,14 +953,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002209 system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14338.787247 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14338.787247 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16578.446038 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16578.446038 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15583.616263 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15583.616263 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15583.616263 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15583.616263 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14471.177417 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14471.177417 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17654.941069 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17654.941069 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16240.872936 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16240.872936 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16240.872936 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16240.872936 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index 0212f6dff..e6e533fb5 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.301191 # Nu sim_ticks 301191365000 # Number of ticks simulated final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1714897 # Simulator instruction rate (inst/s) -host_op_rate 1812090 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 906079333 # Simulator tick rate (ticks/s) -host_mem_usage 278712 # Number of bytes of host memory used -host_seconds 332.41 # Real time elapsed on the host +host_inst_rate 1664644 # Simulator instruction rate (inst/s) +host_op_rate 1758990 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 879528148 # Simulator tick rate (ticks/s) +host_mem_usage 233480 # Number of bytes of host memory used +host_seconds 342.45 # Real time elapsed on the host sim_insts 570051636 # Number of instructions simulated sim_ops 602359842 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 784748962 # Wr system.physmem.bw_total::cpu.inst 7570927872 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2112350170 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9683278042 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9683278042 # Throughput (bytes/s) +system.membus.data_through_bus 2916519731 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 42a2fd6fd..f13bbbf22 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.793670 # Nu sim_ticks 793670137000 # Number of ticks simulated final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 904187 # Simulator instruction rate (inst/s) -host_op_rate 954854 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1262227313 # Simulator tick rate (ticks/s) -host_mem_usage 287296 # Number of bytes of host memory used -host_seconds 628.79 # Real time elapsed on the host +host_inst_rate 583678 # Simulator instruction rate (inst/s) +host_op_rate 616385 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 814802699 # Simulator tick rate (ticks/s) +host_mem_usage 241980 # Number of bytes of host memory used +host_seconds 974.06 # Real time elapsed on the host sim_insts 568539335 # Number of instructions simulated sim_ops 600398272 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 201031 # To system.physmem.bw_total::cpu.inst 48625 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2110539 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2360195 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 2360195 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4941 # Transaction distribution +system.membus.trans_dist::ReadResp 4941 # Transaction distribution +system.membus.trans_dist::Writeback 2493 # Transaction distribution +system.membus.trans_dist::ReadExReq 21835 # Transaction distribution +system.membus.trans_dist::ReadExResp 21835 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 56045 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 56045 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1873216 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1873216 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1873216 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 49213000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 240984000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 69093329 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 190459 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 190459 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 418626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247748 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247748 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1286 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1293754 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1295040 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 41152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 54796160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 54837312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 54837312 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 847042500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 964500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 656346000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index fc36793dc..812998109 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387291 # Number of seconds simulated -sim_ticks 387290918500 # Number of ticks simulated -final_tick 387290918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387399 # Number of seconds simulated +sim_ticks 387398892000 # Number of ticks simulated +final_tick 387398892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75176 # Simulator instruction rate (inst/s) -host_op_rate 75413 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20778674 # Simulator tick rate (ticks/s) -host_mem_usage 280588 # Number of bytes of host memory used -host_seconds 18638.87 # Real time elapsed on the host +host_inst_rate 157866 # Simulator instruction rate (inst/s) +host_op_rate 158364 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43646663 # Simulator tick rate (ticks/s) +host_mem_usage 236680 # Number of bytes of host memory used +host_seconds 8875.80 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678656 # Number of bytes read from this memory -system.physmem.bytes_read::total 1755328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory -system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1198 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26229 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27427 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4334354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4532324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197970 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197970 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 418579 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 418579 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 418579 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4334354 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4950904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27428 # Total number of read requests seen -system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29961 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1755328 # Total number of bytes read from memory -system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1755328 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 76288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678592 # Number of bytes read from this memory +system.physmem.bytes_read::total 1754880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76288 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162048 # Number of bytes written to this memory +system.physmem.bytes_written::total 162048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1192 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26228 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27420 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2532 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2532 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 196924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4332981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4529905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 196924 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 196924 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418298 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418298 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 196924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4332981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4948202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27421 # Total number of read requests seen +system.physmem.writeReqs 2532 # Total number of write requests seen +system.physmem.cpureqs 29953 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1754880 # Total number of bytes read from memory +system.physmem.bytesWritten 162048 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1754880 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162048 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1660 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1696 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1770 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1770 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1628 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1884 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1775 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1646 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1602 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1531 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1534 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1777 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1778 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1801 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 148 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 162 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387290890500 # Total gap between requests +system.physmem.totGap 387398864000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27428 # Categorize read packet sizes +system.physmem.readPktSize::6 27421 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 2533 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 8079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 974 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2532 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 9983 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11822 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5095 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 520 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -124,9 +124,9 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see @@ -147,8 +147,8 @@ system.physmem.wrQLenPdf::19 110 # Wh system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -156,14 +156,99 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 716281750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1441798000 # Sum of mem lat for all requests -system.physmem.totBusLat 137140000 # Total cycles spent in databus access -system.physmem.totBankLat 588376250 # Total cycles spent in bank access -system.physmem.avgQLat 26114.98 # Average queueing delay per request -system.physmem.avgBankLat 21451.66 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 9394 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 203.806685 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 84.980950 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 820.153394 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 8091 86.13% 86.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 139 1.48% 87.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 97 1.03% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 115 1.22% 89.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 131 1.39% 91.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 46 0.49% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 57 0.61% 92.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 495 5.27% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 0.05% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 8 0.09% 97.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 8 0.09% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 0.06% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 6 0.06% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 3 0.03% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.03% 98.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.05% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1 0.01% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1 0.01% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.03% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 7 0.07% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.03% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.03% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 2 0.02% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 2 0.02% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.01% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.02% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.03% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.01% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.03% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 3 0.03% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.01% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 3 0.03% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.02% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 3 0.03% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 2 0.02% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.02% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 3 0.03% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.02% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.01% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.02% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.01% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.01% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 1 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.01% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 2 0.02% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.01% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 2 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.02% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 2 0.02% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.01% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 1 0.01% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.03% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 1 0.01% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 2 0.02% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 1 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 2 0.02% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.02% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 2 0.02% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 3 0.03% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 4 0.04% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 2 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 3 0.03% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 3 0.03% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 63 0.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 9394 # Bytes accessed per row activation +system.physmem.totQLat 539470500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1246251750 # Sum of mem lat for all requests +system.physmem.totBusLat 137105000 # Total cycles spent in databus access +system.physmem.totBankLat 569676250 # Total cycles spent in bank access +system.physmem.avgQLat 19673.63 # Average queueing delay per request +system.physmem.avgBankLat 20775.18 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52566.65 # Average memory access latency +system.physmem.avgMemAccLat 45448.81 # Average memory access latency system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s @@ -171,252 +256,268 @@ system.physmem.avgConsumedWrBW 0.42 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 17.33 # Average write queue length over time -system.physmem.readRowHits 17584 # Number of row buffer hits during reads -system.physmem.writeRowHits 1051 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.49 # Row buffer hit rate for writes -system.physmem.avgGap 12926500.80 # Average gap between requests -system.cpu.branchPred.lookups 97760274 # Number of BP lookups -system.cpu.branchPred.condPredicted 88050389 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 3615826 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 65794197 # Number of BTB lookups -system.cpu.branchPred.BTBHits 65495164 # Number of BTB hits +system.physmem.avgWrQLen 16.43 # Average write queue length over time +system.physmem.readRowHits 18651 # Number of row buffer hits during reads +system.physmem.writeRowHits 1906 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.28 # Row buffer hit rate for writes +system.physmem.avgGap 12933558.04 # Average gap between requests +system.membus.throughput 4948202 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 5633 # Transaction distribution +system.membus.trans_dist::ReadResp 5632 # Transaction distribution +system.membus.trans_dist::Writeback 2532 # Transaction distribution +system.membus.trans_dist::ReadExReq 21788 # Transaction distribution +system.membus.trans_dist::ReadExResp 21788 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 57373 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 57373 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1916928 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1916928 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1916928 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 57596000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 256936750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.branchPred.lookups 97761890 # Number of BP lookups +system.cpu.branchPred.condPredicted 88051950 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 3615398 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 65795011 # Number of BTB lookups +system.cpu.branchPred.BTBHits 65493795 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.545502 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1327 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.542190 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1333 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 221 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774581838 # number of cpu cycles simulated +system.cpu.numCycles 774797785 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 164861421 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1642294018 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97760274 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65496491 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 329212106 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20844019 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 263270886 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2530 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161941896 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 736850 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774347981 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146753 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 164870049 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642248421 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97761890 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65495128 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329214190 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20840770 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263425370 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2796 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 161945451 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 735894 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774503521 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126508 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146615 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 445135875 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74066133 9.56% 67.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37898132 4.89% 71.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9078559 1.17% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28105360 3.63% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18771878 2.42% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11487710 1.48% 80.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3792341 0.49% 81.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146011993 18.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445289331 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74062894 9.56% 67.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37897346 4.89% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9078563 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28105911 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18772818 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11485706 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3794812 0.49% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146016140 18.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774347981 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126210 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.120233 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 216009984 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214299096 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 284224623 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42813319 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17000959 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1636588191 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17000959 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 239857670 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36775472 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52409372 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302053149 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126251359 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1625741176 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 144 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30927043 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73283464 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3120923 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1356412040 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2746512805 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2712406209 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34106596 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774503521 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126177 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.119583 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 216045393 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214430589 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284206110 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42830421 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16991008 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636611354 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16991008 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239885098 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36871695 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52473274 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302059993 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126222453 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625714374 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30924746 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73227733 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3172404 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356421780 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746534895 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712238159 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34296736 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 111641601 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2643056 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2663342 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271532800 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 436949673 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 179753673 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 254530912 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83488154 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1512578374 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2608372 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1459383903 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 52245 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 109279211 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 130205744 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 364701 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774347981 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.884662 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.431358 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111651341 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2642938 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2663443 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271529341 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436963345 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179743092 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254343956 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83161988 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512506564 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2608276 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459339733 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53312 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109205745 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130222811 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 364605 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774503521 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884226 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.431683 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145644273 18.81% 18.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184515384 23.83% 42.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 209689604 27.08% 69.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131356597 16.96% 86.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70636694 9.12% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20383529 2.63% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8079794 1.04% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3860513 0.50% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181593 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145873373 18.83% 18.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184398139 23.81% 42.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209824996 27.09% 69.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131195131 16.94% 86.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70728709 9.13% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20383962 2.63% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8004266 1.03% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3913593 0.51% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181352 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774347981 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774503521 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 108798 6.48% 6.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95504 5.69% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1157743 69.01% 81.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 315646 18.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 114122 6.75% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 97466 5.77% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1164668 68.90% 81.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 314034 18.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 866498027 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866437474 59.37% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2644895 0.18% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419117526 28.72% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171123455 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644764 0.18% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419138356 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171119139 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1459383903 # Type of FU issued -system.cpu.iq.rate 1.884093 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1677691 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001150 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3677006053 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1615499463 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1443256661 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17839670 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9205608 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8545927 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1451932919 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9128675 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215271062 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459339733 # Type of FU issued +system.cpu.iq.rate 1.883510 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1690290 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001158 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3677004243 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615280670 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443165364 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17922346 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9279147 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8546420 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451856157 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9173866 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215403822 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34436830 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 58273 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 245758 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12905531 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34450502 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 58568 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 246048 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12894950 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3343 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 99974 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3290 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 138899 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17000959 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3021185 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 246438 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1608872021 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4125769 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 436949673 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 179753673 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2525299 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 148197 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1793 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 245758 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2269874 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1473729 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3743603 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1454064480 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 416571691 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5319423 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16991008 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3096733 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 244441 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608794631 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4137633 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436963345 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179743092 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2525201 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 147095 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1875 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 246048 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2270642 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1473051 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3743693 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454012420 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416588335 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5327313 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 93685275 # number of nop insts executed -system.cpu.iew.exec_refs 587019661 # number of memory reference insts executed -system.cpu.iew.exec_branches 89035299 # Number of branches executed -system.cpu.iew.exec_stores 170447970 # Number of stores executed -system.cpu.iew.exec_rate 1.877225 # Inst execution rate -system.cpu.iew.wb_sent 1452686018 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1451802588 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1153472607 # num instructions producing a value -system.cpu.iew.wb_consumers 1204727325 # num instructions consuming a value +system.cpu.iew.exec_nop 93679791 # number of nop insts executed +system.cpu.iew.exec_refs 587032224 # number of memory reference insts executed +system.cpu.iew.exec_branches 89032109 # Number of branches executed +system.cpu.iew.exec_stores 170443889 # Number of stores executed +system.cpu.iew.exec_rate 1.876635 # Inst execution rate +system.cpu.iew.wb_sent 1452595352 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451711784 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153369073 # num instructions producing a value +system.cpu.iew.wb_consumers 1204594740 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.874305 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957455 # average fanout of values written-back +system.cpu.iew.wb_rate 1.873665 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957475 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119253312 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119176384 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3615826 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757347022 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.966765 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509958 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3615398 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757512513 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509470 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 240030131 31.69% 31.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 275730182 36.41% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42558160 5.62% 73.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54684817 7.22% 80.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19637761 2.59% 83.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13291596 1.76% 85.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30564343 4.04% 89.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10573009 1.40% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70277023 9.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 240122511 31.70% 31.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275742858 36.40% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42578645 5.62% 73.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54721179 7.22% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19701382 2.60% 83.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13286584 1.75% 85.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30581396 4.04% 89.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10490891 1.38% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70287067 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757347022 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757512513 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -427,192 +528,212 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70277023 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70287067 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2295781723 # The number of ROB reads -system.cpu.rob.rob_writes 3234577019 # The number of ROB writes -system.cpu.timesIdled 25986 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 233857 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295860242 # The number of ROB reads +system.cpu.rob.rob_writes 3234413109 # The number of ROB writes +system.cpu.timesIdled 27770 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 294264 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552803 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552803 # CPI: Total CPI of All Threads -system.cpu.ipc 1.808962 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.808962 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1979163604 # number of integer regfile reads -system.cpu.int_regfile_writes 1275210426 # number of integer regfile writes -system.cpu.fp_regfile_reads 16962684 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491940 # number of floating regfile writes -system.cpu.misc_regfile_reads 592672173 # number of misc regfile reads +system.cpu.cpi 0.552957 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552957 # CPI: Total CPI of All Threads +system.cpu.ipc 1.808458 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.808458 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979095871 # number of integer regfile reads +system.cpu.int_regfile_writes 1275125772 # number of integer regfile writes +system.cpu.fp_regfile_reads 16962854 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491602 # number of floating regfile writes +system.cpu.misc_regfile_reads 592684666 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 197 # number of replacements -system.cpu.icache.tagsinuse 1035.819290 # Cycle average of tags in use -system.cpu.icache.total_refs 161939953 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 121031.355007 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 150116939 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 202209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 202208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 444002 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 262464 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 262464 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1370676 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1373347 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 85440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 58069696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 58155136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 58155136 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 898339500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 2002500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 695005500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu.icache.replacements 199 # number of replacements +system.cpu.icache.tagsinuse 1032.766528 # Cycle average of tags in use +system.cpu.icache.total_refs 161943463 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1335 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 121305.964794 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.819290 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505771 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505771 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161939953 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161939953 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161939953 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161939953 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161939953 # number of overall hits -system.cpu.icache.overall_hits::total 161939953 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1943 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1943 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1943 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1943 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1943 # number of overall misses -system.cpu.icache.overall_misses::total 1943 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 84888000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 84888000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 84888000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 84888000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 84888000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 84888000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161941896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161941896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161941896 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161941896 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161941896 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161941896 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1032.766528 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.504281 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.504281 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161943463 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161943463 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161943463 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161943463 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161943463 # number of overall hits +system.cpu.icache.overall_hits::total 161943463 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1988 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1988 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1988 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1988 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1988 # number of overall misses +system.cpu.icache.overall_misses::total 1988 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 115233000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 115233000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 115233000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 115233000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 115233000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 115233000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161945451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161945451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161945451 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161945451 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161945451 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161945451 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43689.140504 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43689.140504 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43689.140504 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43689.140504 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43689.140504 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43689.140504 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57964.285714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 57964.285714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 57964.285714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 57964.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 57964.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 57964.285714 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1339 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1339 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1339 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1339 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1339 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1339 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62446000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 62446000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62446000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 62446000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62446000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 62446000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 652 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 652 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 652 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 652 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 652 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 652 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1336 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1336 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1336 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1336 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1336 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1336 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 82779000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 82779000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 82779000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 82779000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 82779000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 82779000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46636.295743 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46636.295743 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46636.295743 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 46636.295743 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46636.295743 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 46636.295743 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61960.329341 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61960.329341 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61960.329341 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61960.329341 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61960.329341 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61960.329341 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22452.577609 # Cycle average of tags in use -system.cpu.l2cache.total_refs 550279 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24276 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.667614 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2555 # number of replacements +system.cpu.l2cache.tagsinuse 22446.824248 # Cycle average of tags in use +system.cpu.l2cache.total_refs 550534 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24268 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.685594 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20742.053836 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1060.970953 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 649.552820 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 107120.495495 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 98636.605716 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86369.217000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86369.217000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67062.028500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89882.091658 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 88889.263703 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67062.028500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89882.091658 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 88889.263703 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # 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mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54653.185247 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 94808.783784 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 86304.322741 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73989.512576 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73989.512576 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54653.185247 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77513.897362 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76519.300901 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54653.185247 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77513.897362 # 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number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200258461 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164955659 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164955659 # number of WriteReq hits +system.cpu.dcache.replacements 459241 # number of replacements +system.cpu.dcache.tagsinuse 4093.680719 # Cycle average of tags in use +system.cpu.dcache.total_refs 365075170 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463337 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 787.925786 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 357850000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.680719 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999434 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999434 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 200118468 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200118468 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164955383 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164955383 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365214120 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365214120 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365214120 # number of overall hits -system.cpu.dcache.overall_hits::total 365214120 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 922594 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 922594 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1891157 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1891157 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365073851 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365073851 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365073851 # number of overall hits +system.cpu.dcache.overall_hits::total 365073851 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 907674 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 907674 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1891433 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1891433 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2813751 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2813751 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2813751 # number of overall misses -system.cpu.dcache.overall_misses::total 2813751 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14741568500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14741568500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31920810636 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31920810636 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 150000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 150000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46662379136 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46662379136 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46662379136 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46662379136 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201181055 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201181055 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2799107 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2799107 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2799107 # number of overall misses +system.cpu.dcache.overall_misses::total 2799107 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14763566000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14763566000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33756143071 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33756143071 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 142000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 142000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48519709071 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48519709071 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48519709071 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48519709071 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201026142 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201026142 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 368027871 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 368027871 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 368027871 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 368027871 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004586 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004586 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011335 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011335 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 367872958 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 367872958 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 367872958 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 367872958 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004515 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004515 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011336 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011336 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007645 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007645 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007645 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007645 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15978.391904 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15978.391904 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16878.985000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16878.985000 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 21428.571429 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 21428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16583.691711 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16583.691711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16583.691711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16583.691711 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 590874 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35646 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.576166 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.007609 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007609 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007609 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007609 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16265.273656 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16265.273656 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17846.861650 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17846.861650 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 20285.714286 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 20285.714286 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17333.995832 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17333.995832 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17333.995832 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17333.995832 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 694627 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 46 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 38063 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.249402 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 46 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443878 # number of writebacks -system.cpu.dcache.writebacks::total 443878 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721765 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 721765 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628742 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1628742 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2350507 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2350507 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2350507 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2350507 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200829 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200829 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262415 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262415 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 444002 # number of writebacks +system.cpu.dcache.writebacks::total 444002 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 706801 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 706801 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628976 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628976 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2335777 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2335777 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2335777 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2335777 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200873 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200873 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262457 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262457 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 463244 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 463244 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 463244 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 463244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2611858000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2611858000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4360853500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4360853500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 136000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 136000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6972711500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6972711500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6972711500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6972711500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000998 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 463330 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463330 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463330 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463330 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643681500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643681500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4650895000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4650895000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 128000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 128000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7294576500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7294576500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7294576500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7294576500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses @@ -785,16 +906,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.382689 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.382689 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16618.156355 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16618.156355 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 19428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 19428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15051.919723 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15051.919723 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15051.919723 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15051.919723 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13160.959910 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13160.959910 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17720.598041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17720.598041 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 18285.714286 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 18285.714286 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15743.803553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15743.803553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15743.803553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15743.803553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index 9073b6f33..b5f7d83aa 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.744764 # Nu sim_ticks 744764112500 # Number of ticks simulated final_tick 744764112500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2243211 # Simulator instruction rate (inst/s) -host_op_rate 2249879 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1124943447 # Simulator tick rate (ticks/s) -host_mem_usage 273192 # Number of bytes of host memory used -host_seconds 662.05 # Real time elapsed on the host +host_inst_rate 3917871 # Simulator instruction rate (inst/s) +host_op_rate 3929519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1964765726 # Simulator tick rate (ticks/s) +host_mem_usage 224984 # Number of bytes of host memory used +host_seconds 379.06 # Real time elapsed on the host sim_insts 1485108088 # Number of instructions simulated sim_ops 1489523282 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 5940451992 # Number of bytes read from this memory @@ -35,6 +35,9 @@ system.physmem.bw_write::total 825324492 # Wr system.physmem.bw_total::cpu.inst 7976286575 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2686071498 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10662358072 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10662372316 # Throughput (bytes/s) +system.membus.data_through_bus 7940952255 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.numCycles 1489528226 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 226830c92..860c680b8 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.061066 # Nu sim_ticks 2061066313000 # Number of ticks simulated final_tick 2061066313000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1083437 # Simulator instruction rate (inst/s) -host_op_rate 1086658 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1503618533 # Simulator tick rate (ticks/s) -host_mem_usage 281644 # Number of bytes of host memory used -host_seconds 1370.74 # Real time elapsed on the host +host_inst_rate 684045 # Simulator instruction rate (inst/s) +host_op_rate 686079 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 949333559 # Simulator tick rate (ticks/s) +host_mem_usage 233488 # Number of bytes of host memory used +host_seconds 2171.07 # Real time elapsed on the host sim_insts 1485108088 # Number of instructions simulated sim_ops 1489523282 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 78189 # To system.physmem.bw_total::cpu.inst 31642 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 811479 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 921310 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 921310 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 5293 # Transaction distribution +system.membus.trans_dist::ReadResp 5293 # Transaction distribution +system.membus.trans_dist::Writeback 2518 # Transaction distribution +system.membus.trans_dist::ReadExReq 21859 # Transaction distribution +system.membus.trans_dist::ReadExResp 21859 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 56822 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 56822 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1898880 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1898880 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1898880 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 49814000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 244368000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.numCycles 4122132626 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -393,5 +409,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.690416 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 27625902 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 194593 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 194593 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 435341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 259735 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 259735 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2214 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1341783 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1343997 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 70848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 56867968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 56938816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56938816 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 880175500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1660500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 679831500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index b2e32248a..29e9634dd 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,83 +1,83 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.602332 # Number of seconds simulated -sim_ticks 602332345500 # Number of ticks simulated -final_tick 602332345500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.602519 # Number of seconds simulated +sim_ticks 602519213000 # Number of ticks simulated +final_tick 602519213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59375 # Simulator instruction rate (inst/s) -host_op_rate 109402 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40639301 # Simulator tick rate (ticks/s) -host_mem_usage 298404 # Number of bytes of host memory used -host_seconds 14821.42 # Real time elapsed on the host +host_inst_rate 94132 # Simulator instruction rate (inst/s) +host_op_rate 173444 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64448799 # Simulator tick rate (ticks/s) +host_mem_usage 251596 # Number of bytes of host memory used +host_seconds 9348.80 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493927 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 57280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1693184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 57152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1693312 # Number of bytes read from this memory system.physmem.bytes_read::total 1750464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 57280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 57280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162240 # Number of bytes written to this memory -system.physmem.bytes_written::total 162240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 895 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26456 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 57152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 57152 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory +system.physmem.bytes_written::total 162112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 893 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26458 # Number of read requests responded to by this memory system.physmem.num_reads::total 27351 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2535 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2535 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2811046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2906143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 269353 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 269353 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 269353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2811046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3175496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 94855 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2810387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2905242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94855 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94855 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 269057 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 269057 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 269057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2810387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3174299 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 27351 # Total number of read requests seen -system.physmem.writeReqs 2535 # Total number of write requests seen -system.physmem.cpureqs 29886 # Reqs generatd by CPU via cache - shady +system.physmem.writeReqs 2533 # Total number of write requests seen +system.physmem.cpureqs 29884 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 1750464 # Total number of bytes read from memory -system.physmem.bytesWritten 162240 # Total number of bytes written to memory +system.physmem.bytesWritten 162112 # Total number of bytes written to memory system.physmem.bytesConsumedRd 1750464 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162240 # bytesWritten derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1741 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1707 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1659 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1711 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1725 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1725 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1752 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1742 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 155 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1729 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1834 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1565 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1603 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1731 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1748 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1766 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1802 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1763 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1630 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 168 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 164 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 147 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 602332206500 # Total gap between requests +system.physmem.totGap 602519006000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -91,13 +91,13 @@ system.physmem.writePktSize::2 0 # Ca system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 2535 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 26932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2533 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 26975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -127,8 +127,8 @@ system.physmem.rdQLenPdf::31 0 # Wh system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see @@ -156,14 +156,82 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 88037750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 893262750 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 9709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 196.647235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 83.287733 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 790.384353 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 8486 87.40% 87.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 125 1.29% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 100 1.03% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 90 0.93% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 83 0.85% 91.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 70 0.72% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 47 0.48% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 479 4.93% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 8 0.08% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3 0.03% 97.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 0.04% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2 0.02% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.05% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 2 0.02% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 8 0.08% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 3 0.03% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 9 0.09% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 5 0.05% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.03% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.02% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.04% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.04% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 3 0.03% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 4 0.04% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.03% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 2 0.02% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.01% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 1 0.01% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 5 0.05% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 7 0.07% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 2 0.02% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 2 0.02% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.01% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 4 0.04% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 4 0.04% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.01% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 9 0.09% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 13 0.13% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.01% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.03% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 1 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 5 0.05% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.02% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 4 0.04% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 5 0.05% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 2 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 4 0.04% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.02% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 60 0.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 9709 # Bytes accessed per row activation +system.physmem.totQLat 62966000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 815954750 # Sum of mem lat for all requests system.physmem.totBusLat 136755000 # Total cycles spent in databus access -system.physmem.totBankLat 668470000 # Total cycles spent in bank access -system.physmem.avgQLat 3218.81 # Average queueing delay per request -system.physmem.avgBankLat 24440.42 # Average bank access latency per request +system.physmem.totBankLat 616233750 # Total cycles spent in bank access +system.physmem.avgQLat 2302.15 # Average queueing delay per request +system.physmem.avgBankLat 22530.57 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32659.24 # Average memory access latency +system.physmem.avgMemAccLat 29832.72 # Average memory access latency system.physmem.avgRdBW 2.91 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.91 # Average consumed read bandwidth in MB/s @@ -171,146 +239,167 @@ system.physmem.avgConsumedWrBW 0.27 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 8.01 # Average write queue length over time -system.physmem.readRowHits 16404 # Number of row buffer hits during reads -system.physmem.writeRowHits 1020 # Number of row buffer hits during writes -system.physmem.readRowHitRate 59.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.24 # Row buffer hit rate for writes -system.physmem.avgGap 20154326.66 # Average gap between requests -system.cpu.branchPred.lookups 155894666 # Number of BP lookups -system.cpu.branchPred.condPredicted 155894666 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25699129 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80742532 # Number of BTB lookups -system.cpu.branchPred.BTBHits 80542859 # Number of BTB hits +system.physmem.avgWrQLen 7.81 # Average write queue length over time +system.physmem.readRowHits 18284 # Number of row buffer hits during reads +system.physmem.writeRowHits 1888 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.54 # Row buffer hit rate for writes +system.physmem.avgGap 20161926.32 # Average gap between requests +system.membus.throughput 3174299 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 5448 # Transaction distribution +system.membus.trans_dist::ReadResp 5448 # Transaction distribution +system.membus.trans_dist::Writeback 2533 # Transaction distribution +system.membus.trans_dist::ReadExReq 21903 # Transaction distribution +system.membus.trans_dist::ReadExResp 21903 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 57235 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 57235 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 57235 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 57235 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1912576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1912576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 1912576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1912576 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1912576 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 54010000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 256633000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.branchPred.lookups 156229699 # Number of BP lookups +system.cpu.branchPred.condPredicted 156229699 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25700090 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80130735 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79954590 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.752704 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 2586842 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5513 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.780178 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 2760708 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5575 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1204664695 # number of cpu cycles simulated +system.cpu.numCycles 1205038430 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 175314236 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1434822441 # Number of instructions fetch has processed -system.cpu.fetch.Branches 155894666 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83129701 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 393116244 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83893731 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 577823849 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 123 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 791 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 184597714 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11658023 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1204295068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.043367 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.243240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 175276442 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1436709759 # Number of instructions fetch has processed +system.cpu.fetch.Branches 156229699 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 82715298 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 393071073 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83888584 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 578277772 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 906 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 2 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 184712777 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11835246 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1204659879 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.045547 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.246119 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 818096949 67.93% 67.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26918487 2.24% 70.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 12895052 1.07% 71.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20223867 1.68% 72.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26382325 2.19% 75.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18061341 1.50% 76.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31920988 2.65% 79.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 38294164 3.18% 82.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 211501895 17.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 818506882 67.95% 67.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26870857 2.23% 70.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 12535228 1.04% 71.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20195142 1.68% 72.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26380482 2.19% 75.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18063889 1.50% 76.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31357703 2.60% 79.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 38322925 3.18% 82.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212426771 17.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1204295068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.129409 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.191055 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 284492311 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 500325603 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 268669661 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92767668 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 58039825 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2310318754 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 58039825 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 333414311 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124348906 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3625 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 298566996 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 389921405 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2218156227 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 521 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 243059098 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 121762189 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2583430749 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5648758417 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5648752173 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6244 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1204659879 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.129647 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.192252 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 284492310 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 500755512 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 268717714 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92660799 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 58033544 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2310812595 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 58033544 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 333444734 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124733131 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3847 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 298470128 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 389974495 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2217748571 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12521 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 243097280 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 121807098 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2582807342 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5647663149 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5647656949 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6200 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895260 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 696535489 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 103 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 103 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 737453259 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 525280959 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 216617119 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 339037703 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144743699 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1968663502 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 332 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1774132594 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 144752 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 346851970 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 707722705 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1204295068 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.473171 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.418728 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 695912082 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 105 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 105 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 737293343 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 525275195 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 216586351 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 339249104 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144696192 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1968455796 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 343 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1773948225 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 152074 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 346640912 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 707550278 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 294 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1204659879 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.472572 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.418644 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 354010440 29.40% 29.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 362491598 30.10% 59.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234089313 19.44% 78.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 140647652 11.68% 90.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60236623 5.00% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39446291 3.28% 98.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10873538 0.90% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1896665 0.16% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 602948 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 354366536 29.42% 29.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 362605011 30.10% 59.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234071294 19.43% 78.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 140518579 11.66% 90.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60300441 5.01% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39440661 3.27% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10869049 0.90% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1880938 0.16% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 607370 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1204295068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1204659879 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 400252 14.21% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2198563 78.06% 92.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 217598 7.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 405736 14.35% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2202072 77.90% 92.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 219007 7.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812295 2.64% 2.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1058825283 59.68% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 18980 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 398 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812378 2.64% 2.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1058677272 59.68% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 18975 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 392 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.32% # Type of FU issued @@ -337,84 +426,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.32% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 476287231 26.85% 89.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192188407 10.83% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 476256932 26.85% 89.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192182276 10.83% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1774132594 # Type of FU issued -system.cpu.iq.rate 1.472719 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2816413 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001587 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4755521042 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2315690389 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1716753140 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 379 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1840 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1730136533 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 179 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210301951 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1773948225 # Type of FU issued +system.cpu.iq.rate 1.472109 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2826815 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001594 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4755534756 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2315271702 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1716628380 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 462 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1804 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1729962441 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 210357388 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 106238837 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 40588 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 180694 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 28431061 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 106233073 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 38741 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 180751 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 28400293 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2329 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 64 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2345 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 48 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 58039825 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1222123 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 102210 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1968663834 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63066910 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 525280959 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 216617119 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49147 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2813 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 180694 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1387767 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24439207 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25826974 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1757694663 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 472697091 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 16437931 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 58033544 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1572366 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 106573 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1968456139 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63007739 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 525275195 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 216586351 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 94 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49655 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2783 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 180751 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1386811 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24440636 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25827447 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1757502391 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 472605363 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 16445834 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 664152329 # number of memory reference insts executed -system.cpu.iew.exec_branches 110147604 # Number of branches executed -system.cpu.iew.exec_stores 191455238 # Number of stores executed -system.cpu.iew.exec_rate 1.459074 # Inst execution rate -system.cpu.iew.wb_sent 1717478326 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1716753232 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1259860051 # num instructions producing a value -system.cpu.iew.wb_consumers 1819503625 # num instructions consuming a value +system.cpu.iew.exec_refs 664057082 # number of memory reference insts executed +system.cpu.iew.exec_branches 110136743 # Number of branches executed +system.cpu.iew.exec_stores 191451719 # Number of stores executed +system.cpu.iew.exec_rate 1.458462 # Inst execution rate +system.cpu.iew.wb_sent 1717351615 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1716628496 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1259714523 # num instructions producing a value +system.cpu.iew.wb_consumers 1819339484 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.425088 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692420 # average fanout of values written-back +system.cpu.iew.wb_rate 1.424543 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692402 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 347171319 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 346963425 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25699242 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1146255243 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.414601 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.834752 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25700222 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1146626335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.414143 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.834829 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 413178457 36.05% 36.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 412793718 36.01% 72.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87651437 7.65% 79.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122127525 10.65% 90.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23936453 2.09% 92.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25493357 2.22% 94.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16343741 1.43% 96.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12104723 1.06% 97.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32625832 2.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 413585484 36.07% 36.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 412792006 36.00% 72.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 87637452 7.64% 79.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122098814 10.65% 90.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 23946599 2.09% 92.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25447448 2.22% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16362955 1.43% 96.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12115407 1.06% 97.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32640170 2.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1146255243 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1146626335 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493927 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -425,195 +514,217 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354439 # Number of committed integer instructions. system.cpu.commit.function_calls 1061692 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32625832 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32640170 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3082294657 # The number of ROB reads -system.cpu.rob.rob_writes 3995391584 # The number of ROB writes -system.cpu.timesIdled 60284 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 369627 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3082443517 # The number of ROB reads +system.cpu.rob.rob_writes 3994969913 # The number of ROB writes +system.cpu.timesIdled 60378 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 378551 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493927 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.368898 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.368898 # CPI: Total CPI of All Threads -system.cpu.ipc 0.730515 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.730515 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3534938952 # number of integer regfile reads -system.cpu.int_regfile_writes 1966276795 # number of integer regfile writes -system.cpu.fp_regfile_reads 92 # number of floating regfile reads -system.cpu.misc_regfile_reads 906122047 # number of misc regfile reads +system.cpu.cpi 1.369323 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.369323 # CPI: Total CPI of All Threads +system.cpu.ipc 0.730288 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.730288 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3534639638 # number of integer regfile reads +system.cpu.int_regfile_writes 1966129317 # number of integer regfile writes +system.cpu.fp_regfile_reads 116 # number of floating regfile reads +system.cpu.misc_regfile_reads 905981948 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 34 # number of replacements -system.cpu.icache.tagsinuse 799.517991 # Cycle average of tags in use -system.cpu.icache.total_refs 184596362 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 200866.552775 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 93457946 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 204658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 204658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 428893 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246296 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1854 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1328951 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1330805 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 56250752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 56309952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56309952 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 868818500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1393500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 675040498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.icache.replacements 41 # number of replacements +system.cpu.icache.tagsinuse 797.090296 # Cycle average of tags in use +system.cpu.icache.total_refs 184711350 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 199687.945946 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 799.517991 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.390390 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.390390 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 184596362 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 184596362 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 184596362 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 184596362 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 184596362 # number of overall hits -system.cpu.icache.overall_hits::total 184596362 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1352 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1352 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1352 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1352 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1352 # number of overall misses -system.cpu.icache.overall_misses::total 1352 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 65001000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 65001000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 65001000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 65001000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 65001000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 65001000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 184597714 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 184597714 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 184597714 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 184597714 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 184597714 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 184597714 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48077.662722 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48077.662722 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48077.662722 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48077.662722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48077.662722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48077.662722 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 237 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 797.090296 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.389204 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.389204 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 184711350 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 184711350 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 184711350 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 184711350 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 184711350 # number of overall hits +system.cpu.icache.overall_hits::total 184711350 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1427 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1427 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1427 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1427 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1427 # number of overall misses +system.cpu.icache.overall_misses::total 1427 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 89875000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 89875000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 89875000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 89875000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 89875000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 89875000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 184712777 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 184712777 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 184712777 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 184712777 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 184712777 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 184712777 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000008 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000008 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000008 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000008 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000008 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000008 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62981.779958 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62981.779958 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62981.779958 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62981.779958 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62981.779958 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62981.779958 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 295 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 21 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.250000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 73.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 21 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47826000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47826000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47826000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47826000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47826000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47826000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 498 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 498 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 498 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 498 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 498 # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 999.884735 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 960887000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4092.296880 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999096 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999096 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 262033427 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 262033427 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939697 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939697 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 449973124 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 449973124 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 449973124 # number of overall hits +system.cpu.dcache.overall_hits::total 449973124 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 211198 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 211198 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246361 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246361 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 457559 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 457559 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 457559 # number of overall misses +system.cpu.dcache.overall_misses::total 457559 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3104170500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3104170500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4487459000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4487459000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7591629500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7591629500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7591629500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7591629500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 262244625 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 262244625 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 450577836 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 450577836 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 450577836 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 450577836 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000806 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000806 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 450430683 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 450430683 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 450430683 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 450430683 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000805 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000805 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001309 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.001016 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.001016 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001016 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14304.482843 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14304.482843 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16702.214741 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16702.214741 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15594.973785 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15594.973785 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15594.973785 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15594.973785 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 342 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14697.916173 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14697.916173 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18214.973149 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 18214.973149 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16591.586003 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16591.586003 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16591.586003 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16591.586003 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 322 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.953488 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.702703 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 429005 # number of writebacks -system.cpu.dcache.writebacks::total 429005 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7496 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7496 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 71 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 71 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7567 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7567 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7567 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7567 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203910 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203910 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246323 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 450233 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 450233 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 450233 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 450233 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2529393000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2529393000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3622096999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3622096999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6151489999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6151489999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6151489999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6151489999 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 428893 # number of writebacks +system.cpu.dcache.writebacks::total 428893 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7460 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7460 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 70 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 70 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7530 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7530 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7530 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7530 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203738 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203738 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246291 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246291 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 450029 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 450029 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 450029 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 450029 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2608561002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2608561002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3994205500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3994205500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6602766502 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6602766502 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6602766502 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6602766502 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000777 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000777 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses @@ -768,14 +879,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000999 system.cpu.dcache.demand_mshr_miss_rate::total 0.000999 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000999 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12404.457849 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12404.457849 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14704.664197 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14704.664197 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13662.903428 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13662.903428 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13662.903428 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13662.903428 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12803.507456 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12803.507456 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16217.423698 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16217.423698 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14671.868928 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14671.868928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14671.868928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14671.868928 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 8d09ee016..1af1a34f9 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -33,6 +33,9 @@ system.physmem.bw_write::total 896740221 # Wr system.physmem.bw_total::cpu.inst 9846686428 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2808012957 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12654699384 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 12654699384 # Throughput (bytes/s) +system.membus.data_through_bus 12199037473 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1927985345 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 441f669b6..f21ff386d 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -34,6 +34,26 @@ system.physmem.bw_total::writebacks 89270 # To system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 1049487 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 5039 # Transaction distribution +system.membus.trans_dist::ReadResp 5039 # Transaction distribution +system.membus.trans_dist::Writeback 2511 # Transaction distribution +system.membus.trans_dist::ReadExReq 21970 # Transaction distribution +system.membus.trans_dist::ReadExResp 21970 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 56529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 56529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 56529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 56529 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1889280 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1889280 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1889280 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 49608000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 243081000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 3600386796 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -370,5 +390,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 30778915 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 198048 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 198048 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 422980 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 244722 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 244722 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1444 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1307076 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1308520 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 55361792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 55408000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 55408000 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 855855000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1083000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 663072000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |