diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt | 203 |
1 files changed, 105 insertions, 98 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 2f7887688..508ed63ed 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061241 # Nu sim_ticks 61241011500 # Number of ticks simulated final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 252391 # Simulator instruction rate (inst/s) -host_op_rate 253648 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 170598134 # Simulator tick rate (ticks/s) -host_mem_usage 450980 # Number of bytes of host memory used -host_seconds 358.98 # Real time elapsed on the host +host_inst_rate 266495 # Simulator instruction rate (inst/s) +host_op_rate 267822 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 180131185 # Simulator tick rate (ticks/s) +host_mem_usage 451088 # Number of bytes of host memory used +host_seconds 339.98 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 40 2.59% 51.26% # By system.physmem.bytesPerActivate::896-1023 47 3.05% 54.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 705 45.69% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1543 # Bytes accessed per row activation -system.physmem.totQLat 73241750 # Total ticks spent queuing -system.physmem.totMemAccLat 365254250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 73240250 # Total ticks spent queuing +system.physmem.totMemAccLat 365252750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4702.82 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4702.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23452.82 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23452.73 # Average memory access latency per DRAM burst system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s @@ -227,28 +227,28 @@ system.physmem_0.preEnergy 3440250 # En system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2491477695 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34557963000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41122783185 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.511702 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57480391250 # Time in different power states +system.physmem_0.actBackEnergy 2491483680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34557957750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41122783920 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.511714 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57480384250 # Time in different power states system.physmem_0.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1713925750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1713932750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 5360040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2924625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2555146980 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34502112750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41122878195 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.513254 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57387655250 # Time in different power states +system.physmem_1.actBackEnergy 2555148690 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34502111250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41122878405 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.513257 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57387653250 # Time in different power states system.physmem_1.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1806574750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1806576750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 20752188 # Number of BP lookups system.cpu.branchPred.condPredicted 17062075 # Number of conditional branches predicted @@ -386,8 +386,8 @@ system.cpu.discardedOps 2176623 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.351856 # CPI: cycles per instruction system.cpu.ipc 0.739724 # IPC: instructions per cycle -system.cpu.tickCycles 109255164 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13226859 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 109255161 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13226862 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 946097 # number of replacements system.cpu.dcache.tags.tagsinuse 3616.872758 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26263183 # Total number of references to valid blocks. @@ -428,14 +428,14 @@ system.cpu.dcache.demand_misses::cpu.data 989217 # n system.cpu.dcache.demand_misses::total 989217 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 989221 # number of overall misses system.cpu.dcache.overall_misses::total 989221 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919048000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11919048000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542627500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2542627500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14461675500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14461675500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14461675500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14461675500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919046000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11919046000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542633500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2542633500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14461679500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14461679500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14461679500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14461679500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22509137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22509137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -460,14 +460,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.036309 system.cpu.dcache.demand_miss_rate::total 0.036309 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.335544 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.335544 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.242627 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.242627 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.315580 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14619.315580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.256465 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14619.256465 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.333358 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.333358 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.323390 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.323390 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.319624 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14619.319624 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.260509 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14619.260509 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -496,16 +496,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950190 system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865351000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865351000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481616500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481616500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865349000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865349000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481625500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481625500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346967500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12346967500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347124000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12347124000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346974500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12346974500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347131000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12347131000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040136 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040136 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -516,16 +516,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034877 system.cpu.dcache.demand_mshr_miss_rate::total 0.034877 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034876 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.843401 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.843401 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.166150 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.166150 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.841188 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.841188 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.358602 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.358602 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.209053 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.209053 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.332730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.332730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.216420 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.216420 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.340097 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.340097 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements system.cpu.icache.tags.tagsinuse 689.439811 # Cycle average of tags in use @@ -587,6 +587,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 5 # number of writebacks +system.cpu.icache.writebacks::total 5 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses @@ -613,12 +615,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536 system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10245.556298 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 10245.556296 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1833992 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 117.888539 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655412 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655409 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444539 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456347 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.285512 # Average percentage of cache occupancy @@ -634,8 +636,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15237898 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15237898 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 943278 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 943278 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32221 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32221 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits @@ -660,20 +664,22 @@ system.cpu.l2cache.demand_misses::total 15582 # nu system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses system.cpu.l2cache.overall_misses::total 15582 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067673500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1067673500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067670500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1067670500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57597000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 57597000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21897000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 21897000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 57597000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1089570500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1147167500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1089567500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1147164500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 57597000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1089570500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1147167500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 943278 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 943278 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::cpu.data 1089567500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1147164500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 943278 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 943278 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46765 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46765 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) @@ -698,18 +704,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016385 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.894114 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.894114 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.687844 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.687844 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73621.325889 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.592057 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73621.133359 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73621.325889 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.592057 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73621.133359 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,18 +746,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922233500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922230500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922230500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49710000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49710000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18946000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18946000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49710000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941179500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 990889500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941176500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 990886500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49710000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941179500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 990889500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941176500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 990886500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311002 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311002 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses @@ -764,18 +770,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.894114 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.894114 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.687844 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.687844 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.006757 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.406061 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.006757 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.406061 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 1897097 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -784,8 +790,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 943278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2674 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2670 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46765 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46765 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution @@ -793,22 +800,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 903428 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1608 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846334 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2847942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121233472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1897097 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012905 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 950995 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1896781 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 316 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 950829 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1897097 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1891826500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 950995 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1891831500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1203998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -833,9 +840,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21741000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21739000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82130750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82131250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |