diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1480 |
1 files changed, 744 insertions, 736 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index a9bdce95d..3b8f7cb56 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058328 # Number of seconds simulated -sim_ticks 58328364500 # Number of ticks simulated -final_tick 58328364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058675 # Number of seconds simulated +sim_ticks 58675371500 # Number of ticks simulated +final_tick 58675371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135523 # Simulator instruction rate (inst/s) -host_op_rate 136198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87259482 # Simulator tick rate (ticks/s) -host_mem_usage 492508 # Number of bytes of host memory used -host_seconds 668.45 # Real time elapsed on the host +host_inst_rate 111966 # Simulator instruction rate (inst/s) +host_op_rate 112523 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72520515 # Simulator tick rate (ticks/s) +host_mem_usage 490592 # Number of bytes of host memory used +host_seconds 809.09 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 218752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 921408 # Number of bytes read from this memory -system.physmem.bytes_read::total 1184896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 218240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 923072 # Number of bytes read from this memory +system.physmem.bytes_read::total 1186048 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5696 # Number of bytes written to this memory -system.physmem.bytes_written::total 5696 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory +system.physmem.bytes_written::total 6656 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3418 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14397 # Number of read requests responded to by this memory -system.physmem.num_reads::total 18514 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 89 # Number of write requests responded to by this memory -system.physmem.num_writes::total 89 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 766968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3750354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15796911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 20314233 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 766968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 766968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 97654 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 97654 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 97654 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 766968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3750354 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15796911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20411887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 18515 # Number of read requests accepted -system.physmem.writeReqs 89 # Number of write requests accepted -system.physmem.readBursts 18515 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 89 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1179904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5056 # Total number of bytes read from write queue -system.physmem.bytesWritten 4480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1184960 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5696 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 79 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one +system.physmem.num_reads::cpu.data 3410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14423 # Number of read requests responded to by this memory +system.physmem.num_reads::total 18532 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory +system.physmem.num_writes::total 104 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 762432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3719448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15731848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 20213728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 762432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 762432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 113438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 113438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 113438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 762432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3719448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15731848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20327166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 18533 # Number of read requests accepted +system.physmem.writeReqs 104 # Number of write requests accepted +system.physmem.readBursts 18533 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 104 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1180480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue +system.physmem.bytesWritten 4608 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1186112 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6656 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 3247 # Per bank write bursts +system.physmem.perBankRdBursts::0 3245 # Per bank write bursts system.physmem.perBankRdBursts::1 921 # Per bank write bursts -system.physmem.perBankRdBursts::2 949 # Per bank write bursts +system.physmem.perBankRdBursts::2 952 # Per bank write bursts system.physmem.perBankRdBursts::3 1031 # Per bank write bursts -system.physmem.perBankRdBursts::4 1061 # Per bank write bursts -system.physmem.perBankRdBursts::5 1117 # Per bank write bursts -system.physmem.perBankRdBursts::6 1095 # Per bank write bursts -system.physmem.perBankRdBursts::7 1097 # Per bank write bursts +system.physmem.perBankRdBursts::4 1065 # Per bank write bursts +system.physmem.perBankRdBursts::5 1118 # Per bank write bursts +system.physmem.perBankRdBursts::6 1097 # Per bank write bursts +system.physmem.perBankRdBursts::7 1096 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts system.physmem.perBankRdBursts::10 932 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 902 # Per bank write bursts -system.physmem.perBankRdBursts::13 896 # Per bank write bursts -system.physmem.perBankRdBursts::14 1399 # Per bank write bursts -system.physmem.perBankRdBursts::15 904 # Per bank write bursts +system.physmem.perBankRdBursts::12 904 # Per bank write bursts +system.physmem.perBankRdBursts::13 895 # Per bank write bursts +system.physmem.perBankRdBursts::14 1401 # Per bank write bursts +system.physmem.perBankRdBursts::15 903 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 2 # Per bank write bursts -system.physmem.perBankWrBursts::3 1 # Per bank write bursts -system.physmem.perBankWrBursts::4 2 # Per bank write bursts -system.physmem.perBankWrBursts::5 9 # Per bank write bursts -system.physmem.perBankWrBursts::6 10 # Per bank write bursts -system.physmem.perBankWrBursts::7 8 # Per bank write bursts -system.physmem.perBankWrBursts::8 2 # Per bank write bursts +system.physmem.perBankWrBursts::2 3 # Per bank write bursts +system.physmem.perBankWrBursts::3 3 # Per bank write bursts +system.physmem.perBankWrBursts::4 12 # Per bank write bursts +system.physmem.perBankWrBursts::5 10 # Per bank write bursts +system.physmem.perBankWrBursts::6 15 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 1 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 3 # Per bank write bursts +system.physmem.perBankWrBursts::10 1 # Per bank write bursts system.physmem.perBankWrBursts::11 3 # Per bank write bursts -system.physmem.perBankWrBursts::12 2 # Per bank write bursts -system.physmem.perBankWrBursts::13 9 # Per bank write bursts -system.physmem.perBankWrBursts::14 13 # Per bank write bursts -system.physmem.perBankWrBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::12 5 # Per bank write bursts +system.physmem.perBankWrBursts::13 12 # Per bank write bursts +system.physmem.perBankWrBursts::14 7 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58328356000 # Total gap between requests +system.physmem.totGap 58675363000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 18515 # Read request sizes (log2) +system.physmem.readPktSize::6 18533 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 89 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 13470 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 477 # What read queue length does an incoming req see +system.physmem.writePktSize::6 104 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 12556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 99 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -149,20 +149,20 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see @@ -198,102 +198,109 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 3107 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 380.704216 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.847183 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 402.867268 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1088 35.02% 35.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 865 27.84% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94 3.03% 65.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 72 2.32% 68.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 65 2.09% 70.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 68 2.19% 72.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 56 1.80% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 51 1.64% 75.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 748 24.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 3107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 397.815736 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 217.392167 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.651837 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 841 28.28% 28.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 992 33.36% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 92 3.09% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 59 1.98% 66.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 59 1.98% 68.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 62 2.08% 70.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 53 1.78% 72.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 59 1.98% 74.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 757 25.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2974 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 4608 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 1496.681558 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7484.705695 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 1 25.00% 25.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 1 25.00% 50.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 4542 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 1434.998534 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7438.956513 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 2 50.00% 50.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.500000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.477704 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1 25.00% 25.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3 75.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 4 100.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.physmem.totQLat 204802662 # Total ticks spent queuing -system.physmem.totMemAccLat 550477662 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 92180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11108.84 # Average queueing delay per DRAM burst +system.physmem.totQLat 819558662 # Total ticks spent queuing +system.physmem.totMemAccLat 1165402412 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 92225000 # Total ticks spent in databus transfers +system.physmem.avgQLat 44432.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29858.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 20.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 63182.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 20.12 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 20.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.10 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 20.21 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.16 # Data bus utilization in percentage system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.38 # Average write queue length when enqueuing -system.physmem.readRowHits 15382 # Number of row buffer hits during reads -system.physmem.writeRowHits 10 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.49 # Row buffer hit rate for writes -system.physmem.avgGap 3135258.87 # Average gap between requests -system.physmem.pageHitRate 83.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 17803800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 9714375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 81876600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 162000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3809622960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6575109030 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29228595750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39722884515 # Total energy per rank (pJ) -system.physmem_0.averagePower 681.036990 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48583441495 # Time in different power states -system.physmem_0.memoryStateTime::REF 1947660000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7795971005 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5609520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3060750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 61760400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 187920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3809622960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2425538385 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32868570000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39174349935 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.632528 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54671634140 # Time in different power states -system.physmem_1.memoryStateTime::REF 1947660000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1708703360 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 28233990 # Number of BP lookups -system.cpu.branchPred.condPredicted 23266525 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 835401 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11829630 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11747896 # Number of BTB hits +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 17.01 # Average write queue length when enqueuing +system.physmem.readRowHits 15523 # Number of row buffer hits during reads +system.physmem.writeRowHits 12 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 11.88 # Row buffer hit rate for writes +system.physmem.avgGap 3148326.61 # Average gap between requests +system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15986460 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8481825 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 75141360 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 224460 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1848222480.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 457291620 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 99494880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 3995273070 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3179264640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 10079734425 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 19762775190 # Total energy per rank (pJ) +system.physmem_0.averagePower 336.815504 # Core power per rank (mW) +system.physmem_0.totalIdleTime 57405272063 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 196297250 # Time in different power states +system.physmem_0.memoryStateTime::REF 786242000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 40364411250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 8279321820 # Time in different power states +system.physmem_0.memoryStateTime::ACT 287560187 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 8761538993 # Time in different power states +system.physmem_1.actEnergy 5305020 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2804505 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 56548800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 151380 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250773120.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 129702360 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 13640160 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 769421340 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 250623360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 13483521390 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 14962606875 # Total energy per rank (pJ) +system.physmem_1.averagePower 255.006594 # Core power per rank (mW) +system.physmem_1.totalIdleTime 58353889098 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 22210250 # Time in different power states +system.physmem_1.memoryStateTime::REF 106530000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 56015166500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 652672389 # Time in different power states +system.physmem_1.memoryStateTime::ACT 191421152 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1687371209 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 28234010 # Number of BP lookups +system.cpu.branchPred.condPredicted 23266490 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 835433 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11829728 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11748003 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.309074 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 74550 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.309156 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 74546 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 27225 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25478 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1747 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 27219 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25475 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1744 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -323,7 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -353,7 +360,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,7 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -414,84 +421,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58328364500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 116656730 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 117350744 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 746133 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134907690 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28233990 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11847924 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115018036 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1674227 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 853 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 829 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32275439 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 555 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116602964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.162155 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.318550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 746331 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134908246 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28234010 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11848024 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115699810 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1674291 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 849 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 926 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32275670 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 568 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 117285061 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.155401 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.317679 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 59067374 50.66% 50.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13933709 11.95% 62.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9228635 7.91% 70.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34373246 29.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 59749210 50.94% 50.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13933958 11.88% 62.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9228354 7.87% 70.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34373539 29.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116602964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.242026 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.156450 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8835100 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64368120 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33012562 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9561783 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825399 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4097891 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11814 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114395515 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1985251 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825399 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15271601 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50089085 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 110009 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35409630 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14897240 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110872720 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1412183 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11133547 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1231881 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1645196 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 486344 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129945840 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483153679 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119447461 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 433 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 117285061 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.240595 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.149616 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8835265 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 65049836 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33012809 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9561722 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 825429 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4097911 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114395758 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1985288 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 825429 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15272092 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50298480 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 112986 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35409562 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15366512 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110872789 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1412207 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11133815 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1555614 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2094363 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 506230 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129945991 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483154289 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119447702 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22632921 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22633072 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21513680 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26805319 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5347286 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 522469 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 256366 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109667529 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21514760 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26805262 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5347320 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 521988 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 256188 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109667585 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101366370 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074686 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18634782 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41671490 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101366888 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074694 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18634838 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41670017 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116602964 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.869329 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.988911 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 117285061 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.864278 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.988233 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54969091 47.14% 47.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31363076 26.90% 74.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22007447 18.87% 92.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7065313 6.06% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197724 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55650042 47.45% 47.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31364266 26.74% 74.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22008003 18.76% 92.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7064697 6.02% 98.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197740 1.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -499,9 +506,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116602964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 117285061 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9783594 48.67% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9783493 48.67% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available @@ -530,12 +537,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9615674 47.83% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 702930 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9615894 47.83% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 702925 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71970691 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71970995 71.00% 71.00% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued @@ -560,86 +567,86 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24337594 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5047205 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24337772 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5047242 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101366370 # Type of FU issued -system.cpu.iq.rate 0.868929 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20102261 # FU busy when requested +system.cpu.iq.FU_type_0::total 101366888 # Type of FU issued +system.cpu.iq.rate 0.863794 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20102375 # FU busy when requested system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340512191 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128311283 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99607990 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 628 # Number of floating instruction queue writes +system.cpu.iq.int_inst_queue_reads 341195448 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128311397 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99608403 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 458 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121468392 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 288047 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 121469025 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 238 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 288057 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4329408 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 4329351 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602442 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 602476 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130712 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 130798 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825399 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8206553 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 706266 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109688634 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 825429 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8290686 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 768265 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109688691 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26805319 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5347286 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26805262 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5347320 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 180569 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 362078 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 180386 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 424316 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 435086 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412401 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 847487 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100109489 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23802993 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1256881 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 435090 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412415 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 847505 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100109953 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23803133 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1256935 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12822 # number of nop insts executed -system.cpu.iew.exec_refs 28718621 # number of memory reference insts executed -system.cpu.iew.exec_branches 20621294 # Number of branches executed -system.cpu.iew.exec_stores 4915628 # Number of stores executed -system.cpu.iew.exec_rate 0.858154 # Inst execution rate -system.cpu.iew.wb_sent 99693258 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99608103 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59691284 # num instructions producing a value -system.cpu.iew.wb_consumers 95529167 # num instructions consuming a value -system.cpu.iew.wb_rate 0.853856 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624849 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17363279 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 12823 # number of nop insts executed +system.cpu.iew.exec_refs 28718801 # number of memory reference insts executed +system.cpu.iew.exec_branches 20621332 # Number of branches executed +system.cpu.iew.exec_stores 4915668 # Number of stores executed +system.cpu.iew.exec_rate 0.853083 # Inst execution rate +system.cpu.iew.wb_sent 99693665 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99608516 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59691499 # num instructions producing a value +system.cpu.iew.wb_consumers 95528314 # num instructions consuming a value +system.cpu.iew.wb_rate 0.848810 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624857 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17363350 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 823687 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113915056 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.799312 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.736114 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 823717 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 114597116 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.794554 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.732042 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77490817 68.03% 68.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18611366 16.34% 84.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7154135 6.28% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3469454 3.05% 93.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1644903 1.44% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 541342 0.48% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 703110 0.62% 96.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 178773 0.16% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4121156 3.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 78173194 68.22% 68.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18611100 16.24% 84.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7154015 6.24% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3469592 3.03% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644807 1.44% 95.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541237 0.47% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 703127 0.61% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178794 0.16% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4121250 3.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113915056 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 114597116 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -685,80 +692,80 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4121156 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 218205084 # The number of ROB reads -system.cpu.rob.rob_writes 219522331 # The number of ROB writes -system.cpu.timesIdled 576 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 53766 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4121250 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 218887121 # The number of ROB reads +system.cpu.rob.rob_writes 219522508 # The number of ROB writes +system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 65683 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.287747 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.287747 # CPI: Total CPI of All Threads -system.cpu.ipc 0.776550 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.776550 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108097252 # number of integer regfile reads -system.cpu.int_regfile_writes 58691902 # number of integer regfile writes +system.cpu.cpi 1.295408 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.295408 # CPI: Total CPI of All Threads +system.cpu.ipc 0.771958 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.771958 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108097860 # number of integer regfile reads +system.cpu.int_regfile_writes 58692141 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads system.cpu.fp_regfile_writes 93 # number of floating regfile writes -system.cpu.cc_regfile_reads 369002875 # number of cc regfile reads -system.cpu.cc_regfile_writes 58686679 # number of cc regfile writes -system.cpu.misc_regfile_reads 28409649 # number of misc regfile reads +system.cpu.cc_regfile_reads 369004584 # number of cc regfile reads +system.cpu.cc_regfile_writes 58686965 # number of cc regfile writes +system.cpu.misc_regfile_reads 28409767 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 5470636 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.779483 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18249262 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5471148 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.335545 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 36545500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.779483 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999569 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999569 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 5470621 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.769293 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18249382 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5471133 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.335576 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 38111500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.769293 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999549 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999549 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61906894 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61906894 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 13887138 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13887138 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353836 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353836 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61907171 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61907171 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 13887260 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13887260 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353834 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353834 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18240974 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18240974 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18241496 # number of overall hits -system.cpu.dcache.overall_hits::total 18241496 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9587451 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9587451 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381145 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381145 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18241094 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18241094 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18241616 # number of overall hits +system.cpu.dcache.overall_hits::total 18241616 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9587475 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9587475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381147 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381147 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9968596 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9968596 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9968603 # number of overall misses -system.cpu.dcache.overall_misses::total 9968603 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88929958000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88929958000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000514273 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4000514273 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 284000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 284000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92930472273 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92930472273 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92930472273 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92930472273 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23474589 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23474589 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9968622 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9968622 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9968629 # number of overall misses +system.cpu.dcache.overall_misses::total 9968629 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89371349000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89371349000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4092576700 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4092576700 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 93463925700 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 93463925700 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 93463925700 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 93463925700 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23474735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23474735 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -767,474 +774,475 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28209570 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28209570 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28210099 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28210099 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408418 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408418 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28209716 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28209716 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28210245 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28210245 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408417 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408417 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353376 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353376 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353370 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353370 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9275.662322 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9275.662322 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10496.042905 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10496.042905 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20285.714286 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20285.714286 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9322.323051 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9322.323051 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9322.316504 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9322.316504 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 330469 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 108734 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121517 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.719529 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.469699 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 5470636 # number of writebacks -system.cpu.dcache.writebacks::total 5470636 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338792 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4338792 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158657 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158657 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.353375 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353375 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353369 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353369 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9321.677397 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9321.677397 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10737.528303 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10737.528303 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9375.811993 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9375.811993 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9375.805409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9375.805409 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 331977 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 129797 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121610 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12840 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.729850 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.108801 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 5470621 # number of writebacks +system.cpu.dcache.writebacks::total 5470621 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338830 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4338830 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158660 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158660 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4497449 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4497449 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4497449 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4497449 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248659 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248659 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222488 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222488 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4497490 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4497490 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4497490 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4497490 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248645 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248645 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5471147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5471147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5471151 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5471151 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43429617000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43429617000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285050165 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285050165 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 217500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 217500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45714667165 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45714667165 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45714884665 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45714884665 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223589 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 5471132 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5471132 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5471136 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5471136 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817219500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817219500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2296823105 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2296823105 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46114042605 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46114042605 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46114278105 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46114278105 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223587 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223587 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8274.421524 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8274.421524 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.442294 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.442294 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54375 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54375 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8355.591097 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8355.591097 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8355.624742 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8355.624742 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 447 # number of replacements -system.cpu.icache.tags.tagsinuse 427.481000 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32274286 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35701.643805 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193945 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193945 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193941 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.193941 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.291702 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.291702 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10323.403637 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10323.403637 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8428.610862 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8428.610862 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8428.647744 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8428.647744 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 448 # number of replacements +system.cpu.icache.tags.tagsinuse 427.600534 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32274508 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35623.077263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 427.481000 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.834924 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.834924 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 457 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 427.600534 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835157 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835157 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64551760 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64551760 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 32274286 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32274286 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32274286 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32274286 # 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mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000587 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000625 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000753 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000625 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.771775 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000585 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000585 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000751 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058605 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2737.542327 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2737.542327 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95681.818182 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95681.818182 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63298.571429 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63298.571429 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67882.553606 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67882.553606 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63298.571429 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70655.162328 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69404.952658 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63298.571429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70655.162328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2737.542327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3593.825187 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10943139 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 302176 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302175 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058654 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3406.123577 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 133078.717201 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 133078.717201 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76926.428571 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76926.428571 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192051.010430 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192051.010430 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167527.852104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5508.275023 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 10943112 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471085 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 302425 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302424 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5457869 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13303 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 318447 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5245519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5457385 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 36 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318720 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226521 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226521 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 905 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244627 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2256 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16415198 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700360896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318574 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5952 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5790626 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.052683 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.223400 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 226520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244613 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412897 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16415158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700272512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700359168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318864 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6912 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5790903 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052723 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.223481 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485560 94.73% 94.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305065 5.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485590 94.73% 94.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305312 5.27% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5790626 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10942652515 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 5790903 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10942625015 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.6 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1357497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1360996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206727492 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 18642 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 3008 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.respLayer1.occupancy 8206704493 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 18677 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 3023 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 18174 # Transaction distribution -system.membus.trans_dist::WritebackDirty 89 # Transaction distribution -system.membus.trans_dist::CleanEvict 34 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 18190 # Transaction distribution +system.membus.trans_dist::WritebackDirty 104 # Transaction distribution +system.membus.trans_dist::CleanEvict 36 # Transaction distribution system.membus.trans_dist::UpgradeReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 340 # Transaction distribution -system.membus.trans_dist::ReadExResp 340 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 18175 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 37156 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1190592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1190592 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 342 # Transaction distribution +system.membus.trans_dist::ReadExResp 342 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 18191 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 37209 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1192704 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 18519 # Request fanout histogram +system.membus.snoop_fanout::samples 18537 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18519 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 18537 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18519 # Request fanout histogram -system.membus.reqLayer0.occupancy 29524488 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 18537 # Request fanout histogram +system.membus.reqLayer0.occupancy 29625930 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 97237655 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 97326818 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |