diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt | 315 |
1 files changed, 153 insertions, 162 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index dd28872f6..63806d746 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.148086 # Number of seconds simulated -sim_ticks 148086239000 # Number of ticks simulated -final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.148083 # Number of seconds simulated +sim_ticks 148083373000 # Number of ticks simulated +final_tick 148083373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1056603 # Simulator instruction rate (inst/s) -host_op_rate 1064179 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1727464138 # Simulator tick rate (ticks/s) -host_mem_usage 363220 # Number of bytes of host memory used -host_seconds 85.72 # Real time elapsed on the host -sim_insts 90576869 # Number of instructions simulated -sim_ops 91226321 # Number of ops (including micro ops) simulated +host_inst_rate 1433979 # Simulator instruction rate (inst/s) +host_op_rate 1444261 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2344399916 # Simulator tick rate (ticks/s) +host_mem_usage 365828 # Number of bytes of host memory used +host_seconds 63.16 # Real time elapsed on the host +sim_insts 90576861 # Number of instructions simulated +sim_ops 91226312 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 949120 # Number of bytes read from this memory -system.physmem.bytes_read::total 986112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 944768 # Number of bytes read from this memory +system.physmem.bytes_read::total 981760 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 36992 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 36992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory -system.physmem.bytes_written::total 2048 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14830 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15408 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory -system.physmem.num_writes::total 32 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 249800 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6409238 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6659039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 249800 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 249800 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 13830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 13830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 249800 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6409238 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6672869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 249805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6379974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6629779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 249805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 249805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 249805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6379974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6629779 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,43 +70,43 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 296172478 # number of cpu cycles simulated +system.cpu.numCycles 296166746 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90576869 # Number of instructions committed -system.cpu.committedOps 91226321 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses +system.cpu.committedInsts 90576861 # Number of instructions committed +system.cpu.committedOps 91226312 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 96832 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls -system.cpu.num_int_insts 72525682 # number of integer instructions +system.cpu.num_func_calls 112245 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15548925 # number of instructions that are conditional controls +system.cpu.num_int_insts 72525674 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read -system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written +system.cpu.num_int_register_reads 464563355 # number of times the integer registers were read +system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_mem_refs 27318811 # number of memory refs -system.cpu.num_load_insts 22573967 # Number of load instructions +system.cpu.num_mem_refs 27318810 # number of memory refs +system.cpu.num_load_insts 22573966 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 296172478 # Number of busy cycles +system.cpu.num_busy_cycles 296166746 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 510.335448 # Cycle average of tags in use -system.cpu.icache.total_refs 107830181 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 510.334547 # Cycle average of tags in use +system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.335448 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 510.334547 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.249187 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.249187 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 107830181 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 107830181 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 107830181 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 107830181 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 107830181 # number of overall hits -system.cpu.icache.overall_hits::total 107830181 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 107830172 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 107830172 # number of overall hits +system.cpu.icache.overall_hits::total 107830172 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses @@ -126,12 +119,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 32662000 system.cpu.icache.demand_miss_latency::total 32662000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 32662000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 32662000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 107830780 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 107830780 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 107830780 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 107830780 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 107830780 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 107830780 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 107830771 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 107830771 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 107830771 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses @@ -178,26 +171,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 942702 # number of replacements -system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use -system.cpu.dcache.total_refs 26345365 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3568.539568 # Cycle average of tags in use +system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3568.549501 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.871228 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.871228 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21649219 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21649219 # number of ReadReq hits +system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 54479146000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3568.539568 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.871225 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.871225 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26337591 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26337591 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26337591 # number of overall hits -system.cpu.dcache.overall_hits::total 26337591 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 26337590 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26337590 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26337590 # number of overall hits +system.cpu.dcache.overall_hits::total 26337590 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses @@ -206,26 +199,26 @@ system.cpu.dcache.demand_misses::cpu.data 946798 # n system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses system.cpu.dcache.overall_misses::total 946798 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12614490000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12614490000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12611634000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12611634000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1263542000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1263542000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13878032000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13878032000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13878032000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13878032000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22549408 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22549408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 13875176000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13875176000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13875176000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13875176000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27284389 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27284389 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27284389 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27284389 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27284388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27284388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27284388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27284388 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses @@ -234,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14013.157237 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14013.157237 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.984570 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.984570 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 27109.399472 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14657.859438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14657.859438 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.842955 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14654.842955 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.842955 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14654.842955 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +243,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942309 # number of writebacks -system.cpu.dcache.writebacks::total 942309 # number of writebacks +system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks +system.cpu.dcache.writebacks::total 942334 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses @@ -260,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946798 system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9913923000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9913923000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11037638000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11037638000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11037638000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11037638000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -276,68 +269,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11013.157237 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11013.157237 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11657.859438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11657.859438 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 634 # number of replacements -system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1594542 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 103.595504 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 9598.880462 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1827210 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 119.246231 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 8910.209882 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 165.071875 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 160.025936 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.271918 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.005038 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.004884 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.281839 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 8910.241595 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 495.387120 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 193.251747 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.271919 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.015118 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.005898 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.292935 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 899907 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 899928 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942309 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942309 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942334 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942334 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 931968 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 931989 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932036 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 931968 # number of overall hits -system.cpu.l2cache.overall_hits::total 931989 # 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number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 756496000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 30056000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 771160000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 801216000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 767624000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 797680000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 30056000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 771160000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 801216000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 767624000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 797680000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942309 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942309 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942334 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942334 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses @@ -347,16 +340,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 599 system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000313 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000955 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000238 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000879 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015663 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016264 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015591 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015663 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016264 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015591 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -376,41 +369,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # 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