diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm/linux')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt | 1128 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1460 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt | 130 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt | 430 |
4 files changed, 1596 insertions, 1552 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index ec3cdc9eb..effbf44c1 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,554 +1,56 @@ ---------- Begin Simulation Statistics ---------- -final_tick 61269894500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 246086 # Simulator instruction rate (inst/s) -host_mem_usage 426904 # Number of bytes of host memory used -host_op_rate 247853 # Simulator op (including micro ops) rate (op/s) -host_seconds 368.18 # Real time elapsed on the host -host_tick_rate 166415131 # Simulator tick rate (ticks/s) +sim_seconds 0.061144 # Number of seconds simulated +sim_ticks 61144411500 # Number of ticks simulated +final_tick 61144411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 253751 # Simulator instruction rate (inst/s) +host_op_rate 255015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171247115 # Simulator tick rate (ticks/s) +host_mem_usage 451144 # Number of bytes of host memory used +host_seconds 357.05 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated -sim_ops 91253402 # Number of ops (including micro ops) simulated -sim_seconds 0.061270 # Number of seconds simulated -sim_ticks 61269894500 # Number of ticks simulated +sim_ops 91054080 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.707356 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 8859613 # Number of BTB hits -system.cpu.branchPred.BTBLookups 8975636 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 1020 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 765388 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 17116903 # Number of conditional branches predicted -system.cpu.branchPred.lookups 20794461 # Number of BP lookups -system.cpu.branchPred.usedRAS 54785 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 90602849 # Number of instructions committed -system.cpu.committedOps 91253402 # Number of ops (including micro ops) committed -system.cpu.cpi 1.352494 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 22606743 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22606743 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13018.894340 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13018.894340 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11024.761855 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.761855 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 21691800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21691800 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11911546244 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11911546244 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040472 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040472 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 914943 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 914943 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11527 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11527 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9959946256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9959946256 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.039962 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039962 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903416 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903416 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31690.074425 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31690.074425 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28535.254491 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.254491 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 4661081 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4661081 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2341896500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2341896500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015607 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015607 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 73900 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73900 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27140 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334308500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334308500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009875 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009875 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46760 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46760 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 27341724 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27341724 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14414.262673 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14414.262673 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11886.487089 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11886.487089 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 26352881 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26352881 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 14253442744 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14253442744 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.036166 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036166 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 988843 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 988843 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 38667 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38667 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11294254756 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11294254756 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034752 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034752 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 950176 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 950176 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 27341724 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27341724 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14414.262673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14414.262673 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11886.487089 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11886.487089 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 26352881 # number of overall hits -system.cpu.dcache.overall_hits::total 26352881 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 14253442744 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14253442744 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.036166 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036166 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 988843 # number of overall misses -system.cpu.dcache.overall_misses::total 988843 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 38667 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38667 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11294254756 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11294254756 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034752 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034752 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 950176 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 950176 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 247 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2200 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1649 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 27.742918 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 55649172 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 3618.532737 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.883431 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.883431 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 946080 # number of replacements -system.cpu.dcache.tags.sampled_refs 950176 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 55649172 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 3618.532737 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26360655 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20496262250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 943298 # number of writebacks -system.cpu.dcache.writebacks::total 943298 # number of writebacks -system.cpu.discardedOps 2065378 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 27818907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27818907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68915.429630 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68915.429630 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66500.619753 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66500.619753 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 27818097 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27818097 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 55821498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 55821498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 810 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 810 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53865502 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 53865502 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 810 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 810 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 27818907 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27818907 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68915.429630 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68915.429630 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66500.619753 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66500.619753 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 27818097 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27818097 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 55821498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 55821498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 810 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 810 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53865502 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 53865502 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 810 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 810 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 27818907 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27818907 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68915.429630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68915.429630 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66500.619753 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66500.619753 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 27818097 # number of overall hits -system.cpu.icache.overall_hits::total 27818097 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 55821498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 55821498 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 810 # number of overall misses -system.cpu.icache.overall_misses::total 810 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53865502 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 53865502 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 810 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 810 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 748 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 34343.329630 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 55638624 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 696.774140 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.340222 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.340222 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.sampled_refs 810 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 55638624 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 696.774140 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27818097 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 13105167 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.739375 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46760 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46760 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65946.757667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65946.757667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53094.192683 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53094.192683 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 32218 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32218 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958997750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 958997750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.310992 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.310992 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 14542 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14542 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772095750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772095750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310992 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310992 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14542 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14542 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 904226 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904226 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69821.699905 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69821.699905 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57393.301435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57393.301435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 903173 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903173 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 73522250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 73522250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001165 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001165 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 1053 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1053 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 59976000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 59976000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001156 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001156 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1045 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1045 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 943298 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 943298 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 943298 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 943298 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 950986 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 950986 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66208.400128 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66208.400128 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53382.418041 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53382.418041 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 935391 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 935391 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 1032520000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1032520000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016399 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016399 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 15595 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15595 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832071750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 832071750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016390 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016390 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15587 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15587 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 950986 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 950986 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66208.400128 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66208.400128 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53382.418041 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53382.418041 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 935391 # number of overall hits -system.cpu.l2cache.overall_hits::total 935391 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 1032520000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1032520000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016399 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016399 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 15595 # number of overall misses -system.cpu.l2cache.overall_misses::total 15595 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832071750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 832071750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016390 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016390 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15587 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15587 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13889 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 117.618626 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 15216602 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 9366.525575 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 902.408366 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.285844 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.313383 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15570 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475159 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.sampled_refs 15570 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 15216602 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 10268.933941 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831322 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.numCycles 122539789 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 109434622 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 121234176 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1620 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843650 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2845270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1890440000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1382998 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428632744 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 1978690791 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121234176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 904226 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904226 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 943298 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46760 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46760 # Transaction distribution -system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 997568 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31174 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31174 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 21774500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 149672750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 16281536 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 997568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 997568 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 1045 # Transaction distribution -system.membus.trans_dist::ReadResp 1045 # Transaction distribution -system.membus.trans_dist::ReadExReq 14542 # Transaction distribution -system.membus.trans_dist::ReadExResp 14542 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 3930827.39 # Average gap between requests -system.physmem.avgMemAccLat 23360.33 # Average memory access latency per DRAM burst -system.physmem.avgQLat 4610.33 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.busUtil 0.13 # Data bus utilization in percentage -system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 816845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 816845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 16281536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16281536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16281536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16281536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 1547 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 643.557854 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 434.536592 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 403.240998 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 258 16.68% 16.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 197 12.73% 29.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 72 4.65% 34.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 3.68% 37.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 69 4.46% 42.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 102 6.59% 48.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 43 2.78% 51.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 57 3.68% 55.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 692 44.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1547 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 997568 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 997568 # Total read bytes from the system interface side +system.physmem.bytes_read::cpu.inst 996736 # Number of bytes read from this memory +system.physmem.bytes_read::total 996736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 15574 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 16301343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16301343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 811194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 811194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16301343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16301343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15574 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 50048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50048 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 997568 # Number of bytes read from this memory -system.physmem.bytes_read::total 997568 # Number of bytes read from this memory -system.physmem.memoryStateTime::IDLE 55978709750 # Time in different power states -system.physmem.memoryStateTime::REF 2045680000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 3241107750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 15587 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15587 # Number of read requests responded to by this memory -system.physmem.pageHitRate 90.01 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 994 # Per bank write bursts -system.physmem.perBankRdBursts::1 891 # Per bank write bursts -system.physmem.perBankRdBursts::2 951 # Per bank write bursts +system.physmem.perBankRdBursts::0 993 # Per bank write bursts +system.physmem.perBankRdBursts::1 890 # Per bank write bursts +system.physmem.perBankRdBursts::2 950 # Per bank write bursts system.physmem.perBankRdBursts::3 1028 # Per bank write bursts -system.physmem.perBankRdBursts::4 1052 # Per bank write bursts -system.physmem.perBankRdBursts::5 1115 # Per bank write bursts +system.physmem.perBankRdBursts::4 1050 # Per bank write bursts +system.physmem.perBankRdBursts::5 1113 # Per bank write bursts system.physmem.perBankRdBursts::6 1088 # Per bank write bursts system.physmem.perBankRdBursts::7 1088 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 941 # Per bank write bursts +system.physmem.perBankRdBursts::10 938 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 904 # Per bank write bursts -system.physmem.perBankRdBursts::13 869 # Per bank write bursts +system.physmem.perBankRdBursts::12 903 # Per bank write bursts +system.physmem.perBankRdBursts::13 867 # Per bank write bursts system.physmem.perBankRdBursts::14 877 # Per bank write bursts system.physmem.perBankRdBursts::15 904 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -567,8 +69,25 @@ system.physmem.perBankWrBursts::12 0 # Pe system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.rdQLenPdf::0 15468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 61144323500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 15574 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 15451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -599,22 +118,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 15587 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15587 # Read request sizes (log2) -system.physmem.readReqs 15587 # Number of read requests accepted -system.physmem.readRowHitRate 90.01 # Row buffer hit rate for reads -system.physmem.readRowHits 14030 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 77935000 # Total ticks spent in databus transfers -system.physmem.totGap 61269806500 # Total gap between requests -system.physmem.totMemAccLat 364117500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 71861250 # Total ticks spent queuing system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -679,17 +182,514 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.bytesPerActivate::samples 1531 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 649.865447 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 447.084914 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 397.724653 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 242 15.81% 15.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 164 10.71% 26.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94 6.14% 32.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 77 5.03% 37.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 65 4.25% 41.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 106 6.92% 48.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 51 3.33% 52.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 1.83% 54.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 704 45.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation +system.physmem.totQLat 71444000 # Total ticks spent queuing +system.physmem.totMemAccLat 363456500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4587.39 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 23337.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 16.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.30 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 14033 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.readRowHitRate 90.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 3926051.34 # Average gap between requests +system.physmem.pageHitRate 90.11 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 55905599000 # Time in different power states +system.physmem.memoryStateTime::REF 2041520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 3193563500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 16301343 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1030 # Transaction distribution +system.membus.trans_dist::ReadResp 1030 # Transaction distribution +system.membus.trans_dist::ReadExReq 14544 # Transaction distribution +system.membus.trans_dist::ReadExResp 14544 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 996736 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 21821000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 149563500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 20748985 # Number of BP lookups +system.cpu.branchPred.condPredicted 17053333 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 764055 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8969348 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8846034 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.625162 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 62305 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.numCycles 122288823 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 90602849 # Number of instructions committed +system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2027782 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.349724 # CPI: cycles per instruction +system.cpu.ipc 0.740892 # IPC: instructions per cycle +system.cpu.tickCycles 109176310 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13112513 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 5 # number of replacements +system.cpu.icache.tags.tagsinuse 690.927528 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27773576 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 34587.267746 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 690.927528 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.337367 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.337367 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 55549561 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55549561 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27773576 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27773576 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27773576 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27773576 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27773576 # number of overall hits +system.cpu.icache.overall_hits::total 27773576 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses +system.cpu.icache.overall_misses::total 803 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 55308998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 55308998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 55308998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 55308998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 55308998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 55308998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27774379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27774379 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27774379 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27774379 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27774379 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27774379 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68877.955168 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68877.955168 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68877.955168 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68877.955168 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53368002 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 53368002 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53368002 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 53368002 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53368002 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 53368002 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66460.774595 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66460.774595 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66460.774595 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66460.774595 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66460.774595 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66460.774595 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 1982677223 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904183 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904183 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 943269 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46761 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843551 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2845157 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121229632 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1890375500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1371998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1428578994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 10264.635484 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831263 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 117.713119 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9373.658869 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976615 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.286061 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027190 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.313252 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15216022 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15216022 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 903145 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903145 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 943269 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 943269 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 32217 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32217 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 935362 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 935362 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 935362 # number of overall hits +system.cpu.l2cache.overall_hits::total 935362 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1038 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1038 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 14544 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15582 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15582 # number of overall misses +system.cpu.l2cache.overall_misses::total 15582 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71727250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71727250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959621000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 959621000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1031348250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1031348250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1031348250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1031348250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 904183 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 904183 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 943269 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 943269 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46761 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46761 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 950944 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 950944 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 950944 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 950944 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001148 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001148 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.311028 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.311028 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69101.396917 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69101.396917 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65980.541804 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65980.541804 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.438583 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66188.438583 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.438583 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66188.438583 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14544 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15574 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15574 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58365000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58365000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772683000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772683000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831048000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 831048000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831048000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 831048000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001139 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.311028 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311028 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56665.048544 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56665.048544 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53127.268977 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53127.268977 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.243097 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53361.243097 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.243097 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53361.243097 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 946045 # number of replacements +system.cpu.dcache.tags.tagsinuse 3618.157159 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26265609 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 950141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.643907 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20427116250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 3618.157159 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.883339 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.883339 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2250 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 55458945 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55458945 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 21596750 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21596750 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 4661085 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4661085 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 26257835 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26257835 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 26257835 # number of overall hits +system.cpu.dcache.overall_hits::total 26257835 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 914897 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 914897 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 73896 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 73896 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 988793 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 988793 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 988793 # number of overall misses +system.cpu.dcache.overall_misses::total 988793 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11909486494 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11909486494 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342585500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2342585500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 14252071994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14252071994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 14252071994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14252071994 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 22511647 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22511647 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 27246628 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27246628 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 27246628 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27246628 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040641 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040641 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015606 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015606 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.036290 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31701.113727 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31701.113727 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14413.605268 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14413.605268 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 943269 # number of writebacks +system.cpu.dcache.writebacks::total 943269 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11517 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11517 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27135 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27135 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 38652 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38652 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 38652 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38652 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903380 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903380 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46761 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46761 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 950141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 950141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 950141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958325256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958325256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334905750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334905750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293231006 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11293231006 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293231006 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11293231006 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040129 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009876 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034872 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.416651 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.416651 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index b6a9feb5d..dd39737d4 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026894 # Number of seconds simulated -sim_ticks 26894328500 # Number of ticks simulated -final_tick 26894328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026367 # Number of seconds simulated +sim_ticks 26367385000 # Number of ticks simulated +final_tick 26367385000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165934 # Simulator instruction rate (inst/s) -host_op_rate 167125 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49262466 # Simulator tick rate (ticks/s) -host_mem_usage 394132 # Number of bytes of host memory used -host_seconds 545.94 # Real time elapsed on the host +host_inst_rate 125019 # Simulator instruction rate (inst/s) +host_op_rate 125641 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36388385 # Simulator tick rate (ticks/s) +host_mem_usage 387112 # Number of bytes of host memory used +host_seconds 724.61 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated -sim_ops 91240351 # Number of ops (including micro ops) simulated +sim_ops 91041029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 45184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory -system.physmem.bytes_read::total 992640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45184 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 706 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1680057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35228840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36908897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1680057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1680057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1680057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35228840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36908897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15510 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 44608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory +system.physmem.bytes_read::total 992448 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44608 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 697 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15507 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1691787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35947440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37639227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1691787 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1691787 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1691787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35947440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 37639227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15507 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15510 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15507 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 992640 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 992448 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 992640 # Total read bytes from the system interface side +system.physmem.bytesReadSys 992448 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 987 # Per bank write bursts -system.physmem.perBankRdBursts::1 885 # Per bank write bursts -system.physmem.perBankRdBursts::2 942 # Per bank write bursts -system.physmem.perBankRdBursts::3 1029 # Per bank write bursts -system.physmem.perBankRdBursts::4 1048 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 989 # Per bank write bursts +system.physmem.perBankRdBursts::1 884 # Per bank write bursts +system.physmem.perBankRdBursts::2 939 # Per bank write bursts +system.physmem.perBankRdBursts::3 1031 # Per bank write bursts +system.physmem.perBankRdBursts::4 1047 # Per bank write bursts system.physmem.perBankRdBursts::5 1105 # Per bank write bursts system.physmem.perBankRdBursts::6 1078 # Per bank write bursts -system.physmem.perBankRdBursts::7 1080 # Per bank write bursts +system.physmem.perBankRdBursts::7 1078 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 957 # Per bank write bursts -system.physmem.perBankRdBursts::10 936 # Per bank write bursts +system.physmem.perBankRdBursts::9 961 # Per bank write bursts +system.physmem.perBankRdBursts::10 931 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 905 # Per bank write bursts -system.physmem.perBankRdBursts::13 863 # Per bank write bursts -system.physmem.perBankRdBursts::14 876 # Per bank write bursts +system.physmem.perBankRdBursts::12 906 # Per bank write bursts +system.physmem.perBankRdBursts::13 864 # Per bank write bursts +system.physmem.perBankRdBursts::14 875 # Per bank write bursts system.physmem.perBankRdBursts::15 896 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26894128500 # Total gap between requests +system.physmem.totGap 26367229500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15510 # Read request sizes (log2) +system.physmem.readPktSize::6 15507 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 9831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,74 +186,74 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1366 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 726.489019 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 530.637647 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.552146 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 153 11.20% 11.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 146 10.69% 21.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 54 3.95% 25.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 4.76% 30.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 57 4.17% 34.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 41 3.00% 37.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 35 2.56% 40.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 33 2.42% 42.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 782 57.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1366 # Bytes accessed per row activation -system.physmem.totQLat 88775250 # Total ticks spent queuing -system.physmem.totMemAccLat 379587750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5723.74 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 734.553002 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 545.014262 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 382.702300 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 137 10.16% 10.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 142 10.53% 20.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 57 4.23% 24.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 62 4.60% 29.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 68 5.04% 34.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 2.74% 37.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 30 2.22% 39.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 2.08% 41.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 788 58.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation +system.physmem.totQLat 76352250 # Total ticks spent queuing +system.physmem.totMemAccLat 367108500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4923.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24473.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23673.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 37.64 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.91 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 37.64 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.29 # Data bus utilization in percentage system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14143 # Number of row buffer hits during reads +system.physmem.readRowHits 14147 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads +system.physmem.readRowHitRate 91.23 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1733986.36 # Average gap between requests -system.physmem.pageHitRate 91.19 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 24303280500 # Time in different power states -system.physmem.memoryStateTime::REF 898040000 # Time in different power states +system.physmem.avgGap 1700343.68 # Average gap between requests +system.physmem.pageHitRate 91.23 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 23819655750 # Time in different power states +system.physmem.memoryStateTime::REF 880360000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1692660750 # Time in different power states +system.physmem.memoryStateTime::ACT 1664500500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 36908897 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 972 # Transaction distribution -system.membus.trans_dist::ReadResp 972 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1 # Transaction distribution +system.membus.throughput 37639227 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 969 # Transaction distribution +system.membus.trans_dist::ReadResp 969 # Transaction distribution +system.membus.trans_dist::UpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31022 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31022 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992640 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 992640 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 992640 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31020 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31020 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 992448 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 992448 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 18401000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 18431500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145166999 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 144905497 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 27364118 # Number of BP lookups -system.cpu.branchPred.condPredicted 22575249 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 843312 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11626081 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11546341 # Number of BTB hits +system.cpu.branchPred.lookups 29708806 # Number of BP lookups +system.cpu.branchPred.condPredicted 24486950 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 848073 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12459505 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12380967 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.314128 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 70079 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 187 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.369654 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 77225 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 105 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -339,515 +339,517 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53788658 # number of cpu cycles simulated +system.cpu.numCycles 52734771 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14474692 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 130915195 # Number of instructions fetch has processed -system.cpu.fetch.Branches 27364118 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11616420 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24576695 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5106515 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 9886759 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14156505 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 349331 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53187301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.478661 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.235073 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15504828 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 141696019 # Number of instructions fetch has processed +system.cpu.fetch.Branches 29708806 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12458192 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 36323119 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1712998 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 10 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 15157439 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 317484 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 52684513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.702798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.249702 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 28648969 53.86% 53.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3469200 6.52% 60.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2052434 3.86% 64.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1567853 2.95% 67.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1679873 3.16% 70.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3021837 5.68% 76.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1566641 2.95% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1116795 2.10% 81.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10063699 18.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25447326 48.30% 48.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3927834 7.46% 55.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2643597 5.02% 60.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1975703 3.75% 64.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2124397 4.03% 68.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2942984 5.59% 74.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1825722 3.47% 77.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1288988 2.45% 80.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10507962 19.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53187301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.508734 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.433881 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16310855 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8657573 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 23455900 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 522552 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4240421 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4543490 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8671 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 129206748 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42514 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4240421 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17921369 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2850180 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 191379 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 22351654 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5632298 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 126131712 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 134 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1889841 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 3251328 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 563418 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3246 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 146876533 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 549573070 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 512042051 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 826 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 39462347 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4633 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4631 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9072079 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30275485 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5599467 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2184620 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1363504 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 120806561 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8485 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105954089 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 91175 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 29372689 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73925597 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 267 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53187301 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.992094 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.919550 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 52684513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.563363 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.686956 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11541183 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18148303 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18363246 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3783966 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 847815 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4787740 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8797 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 133953704 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39951 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 847815 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13130783 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 7261973 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 198650 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20259912 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10985380 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 130534992 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3194 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4661957 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 5208173 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 864876 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 151632066 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 568616751 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 140291234 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 824 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 44319147 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4700 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4700 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 18678634 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 31297749 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5707560 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2464961 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1558957 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 125335435 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8504 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107771373 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 19311 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34045700 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 86545264 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 286 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 52684513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.045599 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.948200 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15526622 29.19% 29.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10753574 20.22% 49.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8641028 16.25% 65.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6157106 11.58% 77.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5949684 11.19% 88.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2742880 5.16% 93.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2429206 4.57% 98.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 538839 1.01% 99.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 448362 0.84% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15278150 29.00% 29.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10252049 19.46% 48.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8069131 15.32% 63.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6193349 11.76% 75.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6619102 12.56% 88.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3132844 5.95% 94.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1926333 3.66% 97.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 606051 1.15% 98.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 607504 1.15% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53187301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 52684513 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 44574 8.99% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.01% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 174239 35.13% 44.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 277108 55.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 313366 33.84% 33.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 287772 31.08% 64.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 324774 35.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 75094311 70.87% 70.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10550 0.01% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 140 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 196 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25720178 24.27% 95.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5128709 4.84% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 76600270 71.08% 71.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10764 0.01% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 144 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 193 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25964378 24.09% 95.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5195603 4.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105954089 # Type of FU issued -system.cpu.iq.rate 1.969822 # Inst issue rate -system.cpu.iq.fu_busy_cnt 495948 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.004681 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 265681854 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 150192687 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 103425723 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 748 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1061 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 319 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106449666 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 371 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 469381 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107771373 # Type of FU issued +system.cpu.iq.rate 2.043649 # Inst issue rate +system.cpu.iq.fu_busy_cnt 925939 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008592 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 269171739 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 159396970 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 104914190 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 770 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1077 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 346 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 108696926 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 386 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 461125 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7701519 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7870 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6982 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 854623 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8821838 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5647 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 8949 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 962716 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30068 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 15326 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 231326 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4240421 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 731718 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 478226 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 120827778 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309730 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30275485 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5599467 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4597 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 72415 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 359917 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6982 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 447833 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 447193 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 895026 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104954211 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25387781 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 999878 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 847815 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5127616 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 500104 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 125356607 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 320162 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 31297749 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5707560 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4616 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 66442 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 385113 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 8949 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 454051 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 452935 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 906986 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106740965 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25734173 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1030408 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12732 # number of nop insts executed -system.cpu.iew.exec_refs 30458601 # number of memory reference insts executed -system.cpu.iew.exec_branches 21526378 # Number of branches executed -system.cpu.iew.exec_stores 5070820 # Number of stores executed -system.cpu.iew.exec_rate 1.951233 # Inst execution rate -system.cpu.iew.wb_sent 103717343 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 103426042 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62672484 # num instructions producing a value -system.cpu.iew.wb_consumers 105780863 # num instructions consuming a value +system.cpu.iew.exec_nop 12668 # number of nop insts executed +system.cpu.iew.exec_refs 30844738 # number of memory reference insts executed +system.cpu.iew.exec_branches 21924000 # Number of branches executed +system.cpu.iew.exec_stores 5110565 # Number of stores executed +system.cpu.iew.exec_rate 2.024110 # Inst execution rate +system.cpu.iew.wb_sent 105227967 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 104914536 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63175597 # num instructions producing a value +system.cpu.iew.wb_consumers 106448562 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.922823 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.592475 # average fanout of values written-back +system.cpu.iew.wb_rate 1.989476 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.593485 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 29588025 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34317785 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 834722 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 48946880 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.864326 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.553843 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 839389 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 47813008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.904370 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.590937 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19590544 40.02% 40.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13003525 26.57% 66.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4154420 8.49% 75.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3492472 7.14% 82.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1473630 3.01% 85.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 727145 1.49% 86.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 923215 1.89% 88.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 261788 0.53% 89.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5320141 10.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19048029 39.84% 39.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12579538 26.31% 66.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4065916 8.50% 74.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3224325 6.74% 81.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1531590 3.20% 84.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 701376 1.47% 86.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1004304 2.10% 88.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253211 0.53% 88.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5404719 11.30% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 48946880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 47813008 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed -system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27318810 # Number of memory references committed -system.cpu.commit.loads 22573966 # Number of loads committed +system.cpu.commit.refs 27220755 # Number of memory references committed +system.cpu.commit.loads 22475911 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed system.cpu.commit.branches 18732304 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. +system.cpu.commit.int_insts 72326352 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 63923653 70.05% 70.05% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.06% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 22573966 24.74% 94.80% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 4744844 5.20% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 63822386 70.09% 70.09% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 91252960 # Class of committed instruction -system.cpu.commit.bw_lim_events 5320141 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction +system.cpu.commit.bw_lim_events 5404719 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 164461990 # The number of ROB reads -system.cpu.rob.rob_writes 245943119 # The number of ROB writes -system.cpu.timesIdled 58216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 601357 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 167773978 # The number of ROB reads +system.cpu.rob.rob_writes 255639290 # The number of ROB writes +system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50258 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated -system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.593761 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.593761 # CPI: Total CPI of All Threads -system.cpu.ipc 1.684180 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.684180 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 499033245 # number of integer regfile reads -system.cpu.int_regfile_writes 121427335 # number of integer regfile writes -system.cpu.fp_regfile_reads 166 # number of floating regfile reads -system.cpu.fp_regfile_writes 402 # number of floating regfile writes -system.cpu.misc_regfile_reads 29301616 # number of misc regfile reads +system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.582127 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.582127 # CPI: Total CPI of All Threads +system.cpu.ipc 1.717838 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.717838 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115515398 # number of integer regfile reads +system.cpu.int_regfile_writes 62074294 # number of integer regfile writes +system.cpu.fp_regfile_reads 287 # number of floating regfile reads +system.cpu.fp_regfile_writes 460 # number of floating regfile writes +system.cpu.cc_regfile_reads 391234324 # number of cc regfile reads +system.cpu.cc_regfile_writes 61185455 # number of cc regfile writes +system.cpu.misc_regfile_reads 29410043 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4500548582 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 907410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 907410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 40933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 40933 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838119 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120992384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121039168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121039168 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888514500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1215999 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 4590653188 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 911002 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 911001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 37393 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 37393 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1448 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839705 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120997056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121043200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121043200 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 320 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1888566500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 7.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1205249 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424171240 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 631.006365 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14155509 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 731 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19364.581395 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 1424155994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 5.4 # Layer utilization (%) +system.cpu.icache.tags.replacements 2 # number of replacements +system.cpu.icache.tags.tagsinuse 624.324849 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15156433 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 721 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 21021.404993 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 631.006365 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.308109 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.308109 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 728 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 624.324849 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.304846 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.304846 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 719 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 673 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.355469 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 28313740 # Number of tag accesses -system.cpu.icache.tags.data_accesses 28313740 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 14155509 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14155509 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14155509 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14155509 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14155509 # number of overall hits -system.cpu.icache.overall_hits::total 14155509 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 995 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 995 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 995 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 995 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 995 # number of overall misses -system.cpu.icache.overall_misses::total 995 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 67178998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 67178998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 67178998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 67178998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 67178998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 67178998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14156504 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14156504 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14156504 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14156504 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14156504 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14156504 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67516.580905 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67516.580905 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67516.580905 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67516.580905 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67516.580905 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 593 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 666 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.351074 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 30315604 # Number of tag accesses +system.cpu.icache.tags.data_accesses 30315604 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 15156433 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15156433 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15156433 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15156433 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15156433 # number of overall hits +system.cpu.icache.overall_hits::total 15156433 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1006 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1006 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1006 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1006 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1006 # number of overall misses +system.cpu.icache.overall_misses::total 1006 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 68127998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 68127998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 68127998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 68127998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 68127998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 68127998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15157439 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15157439 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15157439 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15157439 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15157439 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15157439 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67721.667992 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67721.667992 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67721.667992 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67721.667992 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67721.667992 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67721.667992 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 475 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.300000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.181818 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 263 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 263 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 263 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 263 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 263 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 263 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 732 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 732 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 732 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 732 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 732 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 732 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50814250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50814250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50814250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50814250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50814250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50814250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69418.374317 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69418.374317 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69418.374317 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69418.374317 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69418.374317 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69418.374317 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 279 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 279 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 279 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 279 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 279 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 727 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 727 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 727 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 727 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 727 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 727 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50452500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50452500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50452500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50452500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50452500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50452500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000048 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000048 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000048 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000048 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000048 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000048 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69398.211829 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69398.211829 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69398.211829 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69398.211829 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69398.211829 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69398.211829 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10751.524012 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1834202 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15494 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 118.381438 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10760.665120 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1837803 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15490 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 118.644480 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9904.575959 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 617.996997 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 228.951056 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.302264 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018860 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006987 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.328110 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15494 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1306 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13614 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.472839 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15186331 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15186331 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 9918.109380 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 609.591474 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 232.964266 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.302677 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018603 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007110 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.328389 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15490 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 502 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1303 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13612 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.472717 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15183333 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15183333 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 906402 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 906426 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942895 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942895 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26395 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26395 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 909994 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 910018 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942911 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942911 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 22855 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 22855 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932797 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932821 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932849 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932873 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932797 # number of overall hits -system.cpu.l2cache.overall_hits::total 932821 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 707 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 276 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 983 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses +system.cpu.l2cache.overall_hits::cpu.data 932849 # number of overall hits +system.cpu.l2cache.overall_hits::total 932873 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 698 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 281 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 979 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 707 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14814 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15521 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 707 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14814 # number of overall misses -system.cpu.l2cache.overall_misses::total 15521 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49834500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21050250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 70884750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 978125750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 978125750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 49834500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 999176000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1049010500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 49834500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 999176000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1049010500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 731 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 906678 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 907409 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 942895 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 942895 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 40933 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 40933 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 731 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 947611 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 948342 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 731 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 947611 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 948342 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967168 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000304 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001083 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.355166 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.355166 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967168 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015633 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016366 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967168 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015633 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016366 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70487.270156 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76269.021739 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72110.630722 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67280.626634 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67280.626634 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70487.270156 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67448.089645 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67586.527930 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70487.270156 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67448.089645 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67586.527930 # average overall miss latency +system.cpu.l2cache.demand_misses::cpu.inst 698 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14819 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15517 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 698 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14819 # number of overall misses +system.cpu.l2cache.overall_misses::total 15517 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49485750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20358500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 69844250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 967191000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 967191000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 49485750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 987549500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1037035250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 49485750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 987549500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1037035250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 910275 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 910997 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 942911 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 942911 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 37393 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 37393 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 947668 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 948390 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 722 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947668 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948390 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.966759 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001075 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.600000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.388789 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.388789 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966759 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015637 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016361 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966759 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015637 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016361 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70896.489971 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72450.177936 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71342.441267 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66528.477095 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66528.477095 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70896.489971 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66640.765234 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66832.200168 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70896.489971 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66640.765234 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66832.200168 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -857,199 +859,215 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 706 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 266 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 972 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 697 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 706 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14804 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15510 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 706 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14804 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15510 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40933250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17118000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58051250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 795610750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 795610750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40933250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 812728750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 853662000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40933250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 812728750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 853662000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000293 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001071 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.355166 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.355166 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016355 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015622 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016355 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57979.107649 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64353.383459 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59723.508230 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 697 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14810 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15507 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 697 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14810 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15507 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40695500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16451000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 57146500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 785057000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 785057000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40695500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 801508000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 842203500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40695500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 801508000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 842203500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965374 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001064 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.388789 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.388789 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965374 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016351 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965374 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016351 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58386.657102 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60481.617647 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58974.716202 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54726.286284 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54726.286284 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57979.107649 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54899.267090 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55039.458414 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57979.107649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54899.267090 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55039.458414 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54000.343926 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54000.343926 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58386.657102 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54119.378798 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54311.182047 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58386.657102 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54119.378798 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54311.182047 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 943515 # number of replacements -system.cpu.dcache.tags.tagsinuse 3673.207831 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28229578 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 947611 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.790260 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7976079250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3673.207831 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896779 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896779 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 943572 # number of replacements +system.cpu.dcache.tags.tagsinuse 3673.474741 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28380480 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 947668 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.947703 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7812548250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3673.474741 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896844 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896844 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 452 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3133 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 478 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3177 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 441 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 60126081 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 60126081 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23676805 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23676805 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4544974 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4544974 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3910 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3910 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 60432712 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 60432712 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23814120 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23814120 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4557910 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4557910 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 634 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 634 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3911 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3911 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28221779 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28221779 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28221779 # number of overall hits -system.cpu.dcache.overall_hits::total 28221779 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1169644 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1169644 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 190007 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 190007 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28372030 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28372030 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28372664 # number of overall hits +system.cpu.dcache.overall_hits::total 28372664 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1184948 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1184948 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 177071 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 177071 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 33 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 33 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1359651 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1359651 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1359651 # number of overall misses -system.cpu.dcache.overall_misses::total 1359651 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13867675477 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13867675477 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8610605390 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8610605390 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 264500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 264500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22478280867 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22478280867 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22478280867 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22478280867 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24846449 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24846449 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1362019 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1362019 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1362052 # number of overall misses +system.cpu.dcache.overall_misses::total 1362052 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14093002232 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14093002232 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8425812922 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8425812922 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 265500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 265500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22518815154 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22518815154 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22518815154 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22518815154 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24999068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24999068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3918 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3918 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 667 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 667 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29581430 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29581430 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29581430 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29581430 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047075 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047075 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040128 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.040128 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002042 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002042 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.045963 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.045963 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.045963 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.045963 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11856.321647 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11856.321647 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45317.306152 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45317.306152 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33062.500000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33062.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16532.390199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16532.390199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16532.390199 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 136970 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 24472 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.597009 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 29734049 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29734049 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29734716 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29734716 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047400 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047400 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037396 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037396 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.049475 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.049475 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002041 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002041 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.045807 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.045807 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.045807 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.045807 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11893.350790 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11893.350790 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47584.375318 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47584.375318 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33187.500000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33187.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16533.407503 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16533.407503 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16533.006929 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16533.006929 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 231027 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 25 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 44986 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.135531 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942895 # number of writebacks -system.cpu.dcache.writebacks::total 942895 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 262958 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 262958 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 149081 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 149081 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942911 # number of writebacks +system.cpu.dcache.writebacks::total 942911 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 274687 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 274687 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 139679 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 139679 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 412039 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 412039 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 412039 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 412039 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906686 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 906686 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40926 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 40926 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947612 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947612 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947612 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947612 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10019308761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10019308761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1304642257 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1304642257 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11323951018 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11323951018 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11323951018 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11323951018 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036492 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036492 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.008643 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.008643 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032034 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.472557 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.472557 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31878.078898 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31878.078898 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11949.986933 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11949.986933 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 414366 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 414366 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 414366 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 414366 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 910261 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 910261 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 37392 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 37392 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 20 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 20 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947653 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947653 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947673 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947673 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10074295509 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10074295509 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1254962842 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1254962842 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1219250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1219250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11329258351 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11329258351 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11330477601 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11330477601 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036412 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036412 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007897 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007897 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.029985 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.029985 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031871 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031871 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031871 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031871 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11067.480106 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11067.480106 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33562.335312 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33562.335312 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 60962.500000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 60962.500000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11955.070422 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11955.070422 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11956.104691 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11956.104691 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 53bbc79f1..b4b101032 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.054241 # Number of seconds simulated -sim_ticks 54240661000 # Number of ticks simulated -final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.054141 # Number of seconds simulated +sim_ticks 54141000000 # Number of ticks simulated +final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1753346 # Simulator instruction rate (inst/s) -host_op_rate 1765935 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1049669772 # Simulator tick rate (ticks/s) -host_mem_usage 433744 # Number of bytes of host memory used -host_seconds 51.67 # Real time elapsed on the host +host_inst_rate 1737374 # Simulator instruction rate (inst/s) +host_op_rate 1746027 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1038196846 # Simulator tick rate (ticks/s) +host_mem_usage 439336 # Number of bytes of host memory used +host_seconds 52.15 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated -sim_ops 91252960 # Number of ops (including micro ops) simulated +sim_ops 91053638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory @@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 431323080 # Nu system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 22553294 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130384064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130292302 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7952024773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1659577821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9611602595 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7952024773 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7952024773 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 348597116 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 348597116 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7952024773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2008174937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9960199711 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9960199711 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 7966662603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1662632718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9629295321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7966662603 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7966662603 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 349238802 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 349238802 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9978534124 # Throughput (bytes/s) system.membus.data_through_bus 540247816 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 108481323 # number of cpu cycles simulated +system.cpu.numCycles 108282001 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602407 # Number of instructions committed -system.cpu.committedOps 91252960 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses +system.cpu.committedOps 91053638 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls -system.cpu.num_int_insts 72525674 # number of integer instructions +system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls +system.cpu.num_int_insts 72326352 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 396967282 # number of times the integer registers were read -system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written +system.cpu.num_int_register_reads 124257699 # number of times the integer registers were read +system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_mem_refs 27318810 # number of memory refs -system.cpu.num_load_insts 22573966 # Number of load instructions +system.cpu.num_cc_register_reads 271814240 # number of times the CC registers were read +system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written +system.cpu.num_mem_refs 27220755 # number of memory refs +system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 108481323 # Number of busy cycles +system.cpu.num_busy_cycles 108282001 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 18732304 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63924095 70.05% 70.05% # Class of executed instruction -system.cpu.op_class::IntMult 10474 0.01% 70.06% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 6 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 15 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::MemRead 22573966 24.74% 94.80% # Class of executed instruction -system.cpu.op_class::MemWrite 4744844 5.20% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction +system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction +system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91253402 # Class of executed instruction +system.cpu.op_class::total 91054080 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index a84dd1567..1dc1749e2 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.147136 # Number of seconds simulated -sim_ticks 147135976000 # Number of ticks simulated -final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.147041 # Number of seconds simulated +sim_ticks 147041218000 # Number of ticks simulated +final_tick 147041218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 805246 # Simulator instruction rate (inst/s) -host_op_rate 811020 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1308067541 # Simulator tick rate (ticks/s) -host_mem_usage 443480 # Number of bytes of host memory used -host_seconds 112.48 # Real time elapsed on the host +host_inst_rate 1067718 # Simulator instruction rate (inst/s) +host_op_rate 1073024 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1733318334 # Simulator tick rate (ticks/s) +host_mem_usage 449084 # Number of bytes of host memory used +host_seconds 84.83 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated -sim_ops 91226312 # Number of ops (including micro ops) simulated +sim_ops 91026990 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory @@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total 36992 # Nu system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 251414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6421054 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6672467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 251414 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 251414 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 251414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6421054 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6672467 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 6672467 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 251576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6425192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6676767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 251576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 251576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 251576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6425192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 6676767 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 792 # Transaction distribution system.membus.trans_dist::ReadResp 792 # Transaction distribution system.membus.trans_dist::ReadExReq 14548 # Transaction distribution @@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 981760 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 15340000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 138060000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -130,77 +130,79 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 294271952 # number of cpu cycles simulated +system.cpu.numCycles 294082436 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90576861 # Number of instructions committed -system.cpu.committedOps 91226312 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses +system.cpu.committedOps 91026990 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls -system.cpu.num_int_insts 72525674 # number of integer instructions +system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls +system.cpu.num_int_insts 72326352 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 464618159 # number of times the integer registers were read -system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written +system.cpu.num_int_register_reads 124237033 # number of times the integer registers were read +system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_mem_refs 27318810 # number of memory refs -system.cpu.num_load_insts 22573966 # Number of load instructions +system.cpu.num_cc_register_reads 339191618 # number of times the CC registers were read +system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written +system.cpu.num_mem_refs 27220755 # number of memory refs +system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 294271952 # Number of busy cycles +system.cpu.num_busy_cycles 294082436 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 18732304 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63924095 70.05% 70.05% # Class of executed instruction -system.cpu.op_class::IntMult 10474 0.01% 70.06% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 6 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 15 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.06% # Class of executed instruction -system.cpu.op_class::MemRead 22573966 24.74% 94.80% # Class of executed instruction -system.cpu.op_class::MemWrite 4744844 5.20% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction +system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction +system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction +system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91253402 # Class of executed instruction +system.cpu.op_class::total 91054080 # Class of executed instruction system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 510.120575 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 510.120575 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 215662141 # Number of tag accesses @@ -217,12 +219,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32063000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32063000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32063000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32063000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32063000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32063000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32073500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32073500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32073500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32073500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32073500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32073500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses @@ -235,12 +237,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53527.545910 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53527.545910 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53527.545910 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53527.545910 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53527.545910 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53527.545910 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.075125 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53545.075125 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.075125 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53545.075125 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.075125 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53545.075125 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -255,43 +257,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30875500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 30875500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30875500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 30875500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30875500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 30875500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51545.075125 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51545.075125 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51545.075125 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51545.075125 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51545.075125 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51545.075125 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9565.271881 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9567.852615 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172981 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233101 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015111 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.291988 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1478 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1468 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15179780 # Number of tag accesses @@ -320,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 15340 # nu system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14762 # number of overall misses system.cpu.l2cache.overall_misses::total 15340 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30056000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11128000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 41184000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756496000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 756496000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 30056000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 767624000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 797680000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 30056000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 767624000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 797680000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30066500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11130000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 41196500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756746500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 756746500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 30066500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 767876500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 797943000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 30066500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 767876500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 797943000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses) @@ -355,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.016192 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52018.166090 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52009.345794 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52015.782828 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52017.218862 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52017.218862 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52018.166090 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52017.104728 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52017.144720 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52018.166090 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52017.104728 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52017.144720 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -420,78 +422,86 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.217259 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26345364 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3565.593965 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.825750 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54410413000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593965 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1322 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2583 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1355 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55531122 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55531122 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26337590 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26337590 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26337590 # number of overall hits -system.cpu.dcache.overall_hits::total 26337590 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits +system.cpu.dcache.overall_hits::total 26245827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses -system.cpu.dcache.overall_misses::total 946798 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711445000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11711445000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1216933000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1216933000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12928378000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12928378000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12928378000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12928378000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses +system.cpu.dcache.overall_misses::total 946799 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711364000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11711364000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12928547500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12928547500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12928547500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12928547500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27284388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27284388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27284388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27284388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.984570 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.984570 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26109.399472 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26109.399472 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13654.842955 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13654.842955 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13655.050824 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13655.007557 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,40 +512,54 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks system.cpu.dcache.writebacks::total 942334 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 946798 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9910952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9910952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123965500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123965500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 117000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 117000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034917500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11034917500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11035034500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11035034500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 821979690 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 822509400 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution |