diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref/arm')
9 files changed, 555 insertions, 555 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index f9650cc7f..71cbbf675 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -514,9 +514,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index bd690b9dd..2d894fefb 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:17:26 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:02:50 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 30004011500 because target called exit() +Exiting @ tick 25988864000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index c606c0251..a17606260 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.030004 # Number of seconds simulated -sim_ticks 30004011500 # Number of ticks simulated -final_tick 30004011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025989 # Number of seconds simulated +sim_ticks 25988864000 # Number of ticks simulated +final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 194545 # Simulator instruction rate (inst/s) -host_op_rate 195941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64427791 # Simulator tick rate (ticks/s) -host_mem_usage 360100 # Number of bytes of host memory used -host_seconds 465.70 # Real time elapsed on the host -sim_insts 90599351 # Number of instructions simulated -sim_ops 91249905 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 997760 # Number of bytes read from this memory -system.physmem.bytes_inst_read 45184 # Number of instructions bytes read from this memory +host_inst_rate 238212 # Simulator instruction rate (inst/s) +host_op_rate 239922 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68332245 # Simulator tick rate (ticks/s) +host_mem_usage 357212 # Number of bytes of host memory used +host_seconds 380.33 # Real time elapsed on the host +sim_insts 90599356 # Number of instructions simulated +sim_ops 91249910 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 999040 # Number of bytes read from this memory +system.physmem.bytes_inst_read 46144 # Number of instructions bytes read from this memory system.physmem.bytes_written 2048 # Number of bytes written to this memory -system.physmem.num_reads 15590 # Number of read requests responded to by this memory +system.physmem.num_reads 15610 # Number of read requests responded to by this memory system.physmem.num_writes 32 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 33254220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1505932 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 68258 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 33322478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 38441080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1775530 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 78803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 38519883 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,316 +64,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 60008024 # number of cpu cycles simulated +system.cpu.numCycles 51977729 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 26814888 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22097408 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 908993 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11644795 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11349875 # Number of BTB hits +system.cpu.BPredUnit.lookups 27100787 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22324909 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 913851 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11625204 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11498872 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 60971 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 9988 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14353439 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128015722 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26814888 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11410846 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24114191 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4769366 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 17672895 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 61157 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 10323 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14508615 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 130146910 # Number of instructions fetch has processed +system.cpu.fetch.Branches 27100787 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11560029 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24493529 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4999674 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8879281 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1085 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 13983254 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 369829 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 59980295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.152543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.127200 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 50 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14156722 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 388066 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 51938784 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.527703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.247354 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 35906918 59.86% 59.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3423177 5.71% 65.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2008077 3.35% 68.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1555866 2.59% 71.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1665852 2.78% 74.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2959461 4.93% 79.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1530954 2.55% 81.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1083113 1.81% 83.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9846877 16.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 27487299 52.92% 52.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3456218 6.65% 59.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2037280 3.92% 63.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1594827 3.07% 66.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1702478 3.28% 69.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2979904 5.74% 75.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1536396 2.96% 78.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1112311 2.14% 80.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10032071 19.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 59980295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.446855 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.133310 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17244522 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15439127 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22437836 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1028996 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3829814 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4444165 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8973 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126393401 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 43020 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3829814 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19245787 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2026344 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8384525 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21437306 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5056519 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 122679258 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 280519 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3795375 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 346 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 142938307 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 534568737 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 534562281 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6456 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429471 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35508836 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 621620 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 624255 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13585300 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29418557 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5501060 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1379571 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 681227 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 117000498 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 611217 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 104991352 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 35829 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26158745 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 64243821 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 56369 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 59980295 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.750431 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.873941 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 51938784 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.521392 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.503898 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17258666 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6822276 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22930941 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 878432 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4048469 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4484484 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8960 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 128309268 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42973 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4048469 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19038937 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2026641 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 195067 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21988132 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4641538 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 124853766 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 286024 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3901771 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 441 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 145615724 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 543819179 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 543813062 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6117 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429479 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 38186245 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20008 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20006 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 11296413 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29738779 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5601526 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2062082 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1203344 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 119239629 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22672 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105633795 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 86270 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27804178 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 69103102 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12544 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 51938784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.033813 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.918657 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 20705588 34.52% 34.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13184290 21.98% 56.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8487470 14.15% 70.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6459646 10.77% 81.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4931435 8.22% 89.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2870978 4.79% 94.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2481638 4.14% 98.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 391274 0.65% 99.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 467976 0.78% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 14084713 27.12% 27.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11449450 22.04% 49.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8003608 15.41% 64.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6710442 12.92% 77.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5305637 10.22% 87.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2900837 5.59% 93.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2546575 4.90% 98.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 460556 0.89% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 476966 0.92% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 59980295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 51938784 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31457 4.81% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 343779 52.58% 57.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 278563 42.61% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 33927 5.08% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 354815 53.12% 58.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 279170 41.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74214604 70.69% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10958 0.01% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 3 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 201 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 251 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25591383 24.37% 95.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5173950 4.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74740578 70.75% 70.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10525 0.01% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 195 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 237 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25722669 24.35% 95.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5159588 4.88% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 104991352 # Type of FU issued -system.cpu.iq.rate 1.749622 # Inst issue rate -system.cpu.iq.fu_busy_cnt 653826 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006227 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 270651681 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 143770389 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102345485 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 973 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1384 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 418 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105644695 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 483 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 378050 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105633795 # Type of FU issued +system.cpu.iq.rate 2.032290 # Inst issue rate +system.cpu.iq.fu_busy_cnt 667939 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006323 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263959647 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 147067415 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102938725 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 936 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1347 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 404 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106301267 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 467 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 423068 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6842681 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 23943 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1595 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 754307 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7162902 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8413 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 3100 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 854772 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 497 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30477 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 39235 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3829814 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 196269 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 34070 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 117648153 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 398714 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29418557 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5501060 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 607315 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13787 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1140 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1595 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 486496 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 484094 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 970590 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 103957070 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25266637 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1034282 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4048469 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 193737 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 33246 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 119298911 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 399459 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29738779 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5601526 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18769 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13636 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1014 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 3100 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 499711 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 490212 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 989923 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104558374 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25377273 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1075421 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 36438 # number of nop insts executed -system.cpu.iew.exec_refs 30369134 # number of memory reference insts executed -system.cpu.iew.exec_branches 21275406 # Number of branches executed -system.cpu.iew.exec_stores 5102497 # Number of stores executed -system.cpu.iew.exec_rate 1.732386 # Inst execution rate -system.cpu.iew.wb_sent 102646599 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102345903 # cumulative count of insts written-back -system.cpu.iew.wb_producers 60560786 # num instructions producing a value -system.cpu.iew.wb_consumers 98602756 # num instructions consuming a value +system.cpu.iew.exec_nop 36610 # number of nop insts executed +system.cpu.iew.exec_refs 30470186 # number of memory reference insts executed +system.cpu.iew.exec_branches 21355608 # Number of branches executed +system.cpu.iew.exec_stores 5092913 # Number of stores executed +system.cpu.iew.exec_rate 2.011600 # Inst execution rate +system.cpu.iew.wb_sent 103258351 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102939129 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62202150 # num instructions producing a value +system.cpu.iew.wb_consumers 103963576 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.705537 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.614190 # average fanout of values written-back +system.cpu.iew.wb_rate 1.980447 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.598307 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 90611960 # The number of committed instructions -system.cpu.commit.commitCommittedOps 91262514 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26386952 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 554848 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 912021 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 56150482 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.625320 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.343724 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 90611965 # The number of committed instructions +system.cpu.commit.commitCommittedOps 91262519 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 28037719 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 10128 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 916929 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 47890316 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.905657 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.507554 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23848704 42.47% 42.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15483848 27.58% 70.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4738925 8.44% 78.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3887159 6.92% 85.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1619823 2.88% 88.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 955795 1.70% 90.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 662165 1.18% 91.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 224422 0.40% 91.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4729641 8.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17540600 36.63% 36.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13534361 28.26% 64.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4502880 9.40% 74.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3873758 8.09% 82.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1516151 3.17% 85.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 799389 1.67% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 846315 1.77% 88.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 253211 0.53% 89.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5023651 10.49% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 56150482 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90611960 # Number of instructions committed -system.cpu.commit.committedOps 91262514 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 47890316 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90611965 # Number of instructions committed +system.cpu.commit.committedOps 91262519 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322629 # Number of memory references committed -system.cpu.commit.loads 22575876 # Number of loads committed +system.cpu.commit.refs 27322631 # Number of memory references committed +system.cpu.commit.loads 22575877 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722470 # Number of branches committed +system.cpu.commit.branches 18722471 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533318 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4729641 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5023651 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 169064573 # The number of ROB reads -system.cpu.rob.rob_writes 239150312 # The number of ROB writes -system.cpu.timesIdled 1544 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27729 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90599351 # Number of Instructions Simulated -system.cpu.committedOps 91249905 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 90599351 # Number of Instructions Simulated -system.cpu.cpi 0.662345 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.662345 # CPI: Total CPI of All Threads -system.cpu.ipc 1.509787 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.509787 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 494492343 # number of integer regfile reads -system.cpu.int_regfile_writes 120192106 # number of integer regfile writes -system.cpu.fp_regfile_reads 207 # number of floating regfile reads -system.cpu.fp_regfile_writes 538 # number of floating regfile writes -system.cpu.misc_regfile_reads 181239075 # number of misc regfile reads -system.cpu.misc_regfile_writes 11602 # number of misc regfile writes +system.cpu.rob.rob_reads 162161169 # The number of ROB reads +system.cpu.rob.rob_writes 242671240 # The number of ROB writes +system.cpu.timesIdled 1828 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 38945 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90599356 # Number of Instructions Simulated +system.cpu.committedOps 91249910 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 90599356 # Number of Instructions Simulated +system.cpu.cpi 0.573710 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.573710 # CPI: Total CPI of All Threads +system.cpu.ipc 1.743042 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.743042 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 497076309 # number of integer regfile reads +system.cpu.int_regfile_writes 120895703 # number of integer regfile writes +system.cpu.fp_regfile_reads 198 # number of floating regfile reads +system.cpu.fp_regfile_writes 527 # number of floating regfile writes +system.cpu.misc_regfile_reads 183813486 # number of misc regfile reads +system.cpu.misc_regfile_writes 11604 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 625.228438 # Cycle average of tags in use -system.cpu.icache.total_refs 13982297 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 731 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19127.629275 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 649.670012 # Cycle average of tags in use +system.cpu.icache.total_refs 14155750 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 749 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 18899.532710 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 625.228438 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.305287 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.305287 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13982297 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13982297 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13982297 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13982297 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13982297 # number of overall hits -system.cpu.icache.overall_hits::total 13982297 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses -system.cpu.icache.overall_misses::total 957 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33318000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33318000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33318000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33318000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33318000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33318000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13983254 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13983254 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13983254 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13983254 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13983254 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13983254 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000068 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000068 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000068 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34815.047022 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34815.047022 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34815.047022 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 649.670012 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.317222 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.317222 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14155750 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14155750 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14155750 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14155750 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14155750 # number of overall hits +system.cpu.icache.overall_hits::total 14155750 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 972 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 972 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 972 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 972 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 972 # number of overall misses +system.cpu.icache.overall_misses::total 972 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33892500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33892500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33892500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33892500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33892500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33892500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14156722 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14156722 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14156722 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14156722 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14156722 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14156722 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34868.827160 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,214 +382,214 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 226 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 226 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 226 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 226 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 731 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 731 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 731 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 731 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 731 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 731 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25047000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25047000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25047000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25047000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25047000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25047000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34264.021888 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34264.021888 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34264.021888 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 749 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 749 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 749 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 749 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 749 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25625000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25625000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25625000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25625000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25625000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25625000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34212.283044 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943524 # number of replacements -system.cpu.dcache.tagsinuse 3583.229064 # Cycle average of tags in use -system.cpu.dcache.total_refs 28391066 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947620 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.960391 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 10655820000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3583.229064 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.874812 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.874812 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23819030 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23819030 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4560353 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4560353 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5887 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5796 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5796 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28379383 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28379383 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28379383 # number of overall hits -system.cpu.dcache.overall_hits::total 28379383 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 991638 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 991638 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 174628 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 174628 # number of WriteReq misses +system.cpu.dcache.replacements 943602 # number of replacements +system.cpu.dcache.tagsinuse 3646.405021 # Cycle average of tags in use +system.cpu.dcache.total_refs 28436874 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947698 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 30.006261 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8214901000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3646.405021 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.890236 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.890236 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23866253 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23866253 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4558926 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4558926 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5898 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5898 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5797 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5797 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 28425179 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28425179 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28425179 # number of overall hits +system.cpu.dcache.overall_hits::total 28425179 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1004103 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1004103 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 176055 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 176055 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1166266 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1166266 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1166266 # number of overall misses -system.cpu.dcache.overall_misses::total 1166266 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5615598500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5615598500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4530256968 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4530256968 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 129500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 129500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10145855468 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10145855468 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10145855468 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10145855468 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24810668 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24810668 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1180158 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1180158 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1180158 # number of overall misses +system.cpu.dcache.overall_misses::total 1180158 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5784178500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5784178500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4612267011 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4612267011 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 129000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 129000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10396445511 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10396445511 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10396445511 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10396445511 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24870356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24870356 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5796 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5796 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29545649 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29545649 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29545649 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29545649 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039968 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.036880 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001357 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.039473 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5662.952106 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25942.328653 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8699.435179 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8699.435179 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23124041 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5906 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5906 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5797 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5797 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 29605337 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29605337 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29605337 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29605337 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040373 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037182 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001355 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.039863 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039863 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5760.542992 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26197.875726 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16125 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23104055 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8085 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.116388 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.120698 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942876 # number of writebacks -system.cpu.dcache.writebacks::total 942876 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87943 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 87943 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 130703 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 130703 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942908 # number of writebacks +system.cpu.dcache.writebacks::total 942908 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 99918 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 99918 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 132542 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 132542 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 218646 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 218646 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 218646 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 218646 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903695 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903695 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43925 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43925 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947620 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947620 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947620 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947620 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2331156500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2331156500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1079888101 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1079888101 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3411044601 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3411044601 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3411044601 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3411044601 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036424 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032073 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032073 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2579.583266 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24584.817325 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3599.591187 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3599.591187 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 232460 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 232460 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 232460 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 232460 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904185 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 904185 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43513 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43513 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947698 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947698 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947698 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947698 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2402147500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2402147500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1077084130 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1077084130 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3479231630 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3479231630 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3479231630 # 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miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34272.984441 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34209.269663 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34352.593204 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34272.984441 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.167450 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34272.984441 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.167450 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 9634.775304 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 182.147356 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 200.243688 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.294030 # 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number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 749 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 947698 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 948447 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963952 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000403 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.325962 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963952 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015720 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963952 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015720 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.396122 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34262.362637 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34352.380625 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,50 +601,50 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks system.cpu.l2cache.writebacks::total 32 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 706 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 346 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1052 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 706 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14884 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15590 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 706 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14884 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15590 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21938500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10782000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32720500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 452176000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 452176000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21938500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462958000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 484896500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21938500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462958000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 484896500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000383 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.321993 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015707 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965800 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015707 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31074.362606 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31161.849711 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31103.040308 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31074.362606 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31104.407417 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31074.362606 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31104.407417 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 721 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 355 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14534 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14534 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 721 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14889 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15610 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 721 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14889 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15610 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22414000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11074500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 33488500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 452032500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 452032500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22414000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 463107000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 485521000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22414000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 463107000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 485521000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000393 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.325962 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.378641 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31195.774648 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31101.726985 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 4140383de..4c0e3ba04 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -100,9 +100,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout index f67da13a2..439b5027c 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:51:19 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:03:02 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 336dcb8a1..1ec302d05 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu sim_ticks 54240666000 # Number of ticks simulated final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2969105 # Simulator instruction rate (inst/s) -host_op_rate 2990423 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1777502999 # Simulator tick rate (ticks/s) -host_mem_usage 349280 # Number of bytes of host memory used -host_seconds 30.52 # Real time elapsed on the host +host_inst_rate 2795699 # Simulator instruction rate (inst/s) +host_op_rate 2815772 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1673691127 # Simulator tick rate (ticks/s) +host_mem_usage 346432 # Number of bytes of host memory used +host_seconds 32.41 # Real time elapsed on the host sim_insts 90602415 # Number of instructions simulated sim_ops 91252969 # Number of ops (including micro ops) simulated system.physmem.bytes_read 521339715 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 91252969 # Nu system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 96832 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15564339 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls system.cpu.num_int_insts 72525682 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_int_register_reads 396912516 # number of times the integer registers were read diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index 3779c19fc..f9dbf6b5f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -183,9 +183,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout index d74925785..d8b8bc833 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:51:58 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 17:03:45 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 4a03aab99..f3ad4a424 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.148086 # Nu sim_ticks 148086239000 # Number of ticks simulated final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1772363 # Simulator instruction rate (inst/s) -host_op_rate 1785070 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2897675173 # Simulator tick rate (ticks/s) -host_mem_usage 358192 # Number of bytes of host memory used -host_seconds 51.11 # Real time elapsed on the host +host_inst_rate 1876733 # Simulator instruction rate (inst/s) +host_op_rate 1890189 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3068313156 # Simulator tick rate (ticks/s) +host_mem_usage 355600 # Number of bytes of host memory used +host_seconds 48.26 # Real time elapsed on the host sim_insts 90576869 # Number of instructions simulated sim_ops 91226321 # Number of ops (including micro ops) simulated system.physmem.bytes_read 986112 # Number of bytes read from this memory @@ -72,7 +72,7 @@ system.cpu.committedOps 91226321 # Nu system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 96832 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15564339 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls system.cpu.num_int_insts 72525682 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read |