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-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini39
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/o3-timing/simout10
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt27
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini36
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout8
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini89
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/simple-timing/simout10
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt226
9 files changed, 246 insertions, 209 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index 80bca85f9..3c2994f97 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -522,9 +527,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/arm/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/gem5/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index 73d194ff5..f91e94134 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:47:37
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:55:20
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -23,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 26786364500 because target called exit()
+Exiting @ tick 26773408500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 5f24b4574..5f270b948 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.026773 # Nu
sim_ticks 26773408500 # Number of ticks simulated
final_tick 26773408500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 153523 # Simulator instruction rate (inst/s)
-host_op_rate 154625 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45373007 # Simulator tick rate (ticks/s)
-host_mem_usage 376436 # Number of bytes of host memory used
-host_seconds 590.07 # Real time elapsed on the host
+host_inst_rate 111467 # Simulator instruction rate (inst/s)
+host_op_rate 112267 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32943427 # Simulator tick rate (ticks/s)
+host_mem_usage 421388 # Number of bytes of host memory used
+host_seconds 812.71 # Real time elapsed on the host
sim_insts 90589798 # Number of instructions simulated
sim_ops 91240351 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 97.27 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 1726302.76 # Average gap between requests
+system.cpu.branchPred.lookups 26672080 # Number of BP lookups
+system.cpu.branchPred.condPredicted 21992542 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 842598 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11362388 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 11268059 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 99.169814 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 70167 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 188 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -231,14 +240,6 @@ system.cpu.workload.num_syscalls 442 # Nu
system.cpu.numCycles 53546818 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 26672080 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 21992542 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 842598 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 11362388 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 11268059 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 70167 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 188 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 14171508 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 127778991 # Number of instructions fetch has processed
system.cpu.fetch.Branches 26672080 # Number of branches that fetch encountered
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
index c70c9e062..4ab5b0af3 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -68,7 +71,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@@ -76,6 +79,23 @@ port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -84,7 +104,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@@ -100,9 +120,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
@@ -124,7 +144,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
index fa062edc0..6c1085aa7 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 14:03:25
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 20:04:57
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index 42f3c00f3..a3d57c71f 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu
sim_ticks 54240661000 # Number of ticks simulated
final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2374877 # Simulator instruction rate (inst/s)
-host_op_rate 2391929 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1421759359 # Simulator tick rate (ticks/s)
-host_mem_usage 351688 # Number of bytes of host memory used
-host_seconds 38.15 # Real time elapsed on the host
+host_inst_rate 1585065 # Simulator instruction rate (inst/s)
+host_op_rate 1596445 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 948925064 # Simulator tick rate (ticks/s)
+host_mem_usage 411788 # Number of bytes of host memory used
+host_seconds 57.16 # Real time elapsed on the host
sim_insts 90602407 # Number of instructions simulated
sim_ops 91252960 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
index 9c2aed7c6..75d632a3d 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,23 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -91,7 +89,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -101,23 +99,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -126,6 +119,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -134,7 +144,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -142,25 +152,20 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -169,10 +174,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -187,9 +192,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
@@ -211,7 +216,7 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
index 364027fbc..ceb59a6aa 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:45:02
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 20:06:05
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -23,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 148267705000 because target called exit()
+Exiting @ tick 147135976000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 91d2f15f8..866d0f0d0 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu
sim_ticks 147135976000 # Number of ticks simulated
final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1200528 # Simulator instruction rate (inst/s)
-host_op_rate 1209136 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1950176496 # Simulator tick rate (ticks/s)
-host_mem_usage 364464 # Number of bytes of host memory used
-host_seconds 75.45 # Real time elapsed on the host
+host_inst_rate 836188 # Simulator instruction rate (inst/s)
+host_op_rate 842183 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1358330065 # Simulator tick rate (ticks/s)
+host_mem_usage 420368 # Number of bytes of host memory used
+host_seconds 108.32 # Real time elapsed on the host
sim_insts 90576861 # Number of instructions simulated
sim_ops 91226312 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
@@ -170,114 +170,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 942702 # number of replacements
-system.cpu.dcache.tagsinuse 3565.217259 # Cycle average of tags in use
-system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.870414 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 26337590 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 26337590 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 26337590 # number of overall hits
-system.cpu.dcache.overall_hits::total 26337590 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
-system.cpu.dcache.overall_misses::total 946798 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711445000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11711445000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1216933000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1216933000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 12928378000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 12928378000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 12928378000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 12928378000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 27284388 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 27284388 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 27284388 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 27284388 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.984570 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.984570 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26109.399472 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 26109.399472 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13654.842955 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13654.842955 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks
-system.cpu.dcache.writebacks::total 942334 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 946798 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1827177 # Total number of references to valid blocks.
@@ -414,5 +306,113 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 942702 # number of replacements
+system.cpu.dcache.tagsinuse 3565.217259 # Cycle average of tags in use
+system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.870414 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 26337590 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 26337590 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 26337590 # number of overall hits
+system.cpu.dcache.overall_hits::total 26337590 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
+system.cpu.dcache.overall_misses::total 946798 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711445000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11711445000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1216933000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1216933000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 12928378000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 12928378000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 12928378000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 12928378000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::total 27284388 # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 27284388 # number of overall (read+write) accesses
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+system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses
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+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.984570 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.984570 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26109.399472 # average WriteReq miss latency
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 13654.842955 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks
+system.cpu.dcache.writebacks::total 942334 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses
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+system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------