diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref/sparc/linux')
-rw-r--r-- | tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt | 335 |
1 files changed, 171 insertions, 164 deletions
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 8cbe9f760..5dc111e3a 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.361489 # Number of seconds simulated -sim_ticks 361488536500 # Number of ticks simulated -final_tick 361488536500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.361598 # Number of seconds simulated +sim_ticks 361597758500 # Number of ticks simulated +final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1117046 # Simulator instruction rate (inst/s) -host_op_rate 1117092 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1656101101 # Simulator tick rate (ticks/s) -host_mem_usage 428664 # Number of bytes of host memory used -host_seconds 218.28 # Real time elapsed on the host +host_inst_rate 1135132 # Simulator instruction rate (inst/s) +host_op_rate 1135179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1683423955 # Simulator tick rate (ticks/s) +host_mem_usage 429008 # Number of bytes of host memory used +host_seconds 214.80 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 56256 # Nu system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 722977073 # number of cpu cycles simulated +system.cpu.numCycles 723195517 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 722977072.998000 # Number of busy cycles +system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched @@ -90,18 +90,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.469029 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134366269500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469029 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses @@ -126,16 +126,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613736000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11613736000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12832738000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12832738000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12832738000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12832738000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) @@ -156,16 +156,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.386401 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.386401 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13658.140399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13658.140399 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,16 +186,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720879000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720879000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1172292000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1172292000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 90000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 90000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893171000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11893171000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893171000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11893171000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.386401 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.386401 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22500 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.412972 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.412972 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id @@ -246,12 +246,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 48389500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 48389500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 48389500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 48389500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 48389500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 48389500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses @@ -264,12 +264,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54863.378685 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54863.378685 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54863.378685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54863.378685 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,44 +278,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 25 # number of writebacks +system.cpu.icache.writebacks::total 25 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47507500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47507500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47507500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47507500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47507500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47507500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53863.378685 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53863.378685 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9730.625106 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670068 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635584 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319455 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id @@ -325,8 +327,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits @@ -351,20 +355,22 @@ system.cpu.l2cache.demand_misses::total 15603 # nu system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses system.cpu.l2cache.overall_misses::total 15603 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 46150500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 46150500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8242500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8242500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 46150500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 819160500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 46150500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 819160500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses) @@ -389,18 +395,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016591 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.412969 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.412969 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.192271 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.192271 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -421,18 +427,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15603 system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 619097500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 619097500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 37360500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 37360500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6672500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6672500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37360500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 625770000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 663130500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37360500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 625770000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 663130500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses @@ -445,18 +451,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.412969 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.412969 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -465,8 +471,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 233 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 208 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution @@ -474,22 +481,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814616 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2816405 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1875953 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.001033 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1875951 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1875953 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1873242500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -514,9 +521,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15603 # Request fanout histogram -system.membus.reqLayer0.occupancy 15606000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 78018000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |