diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref/sparc/linux')
7 files changed, 115 insertions, 42 deletions
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini index addbca3ec..a0039b696 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout index 70118299e..c071d26fa 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:43:24 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:53:37 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index f04b9260d..804f585d6 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,23 +4,37 @@ sim_seconds 0.122216 # Nu sim_ticks 122215830000 # Number of ticks simulated final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1503519 # Simulator instruction rate (inst/s) -host_op_rate 1503581 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 753629165 # Simulator tick rate (ticks/s) -host_mem_usage 346024 # Number of bytes of host memory used -host_seconds 162.17 # Real time elapsed on the host +host_inst_rate 2951739 # Simulator instruction rate (inst/s) +host_op_rate 2951861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1479540198 # Simulator tick rate (ticks/s) +host_mem_usage 346528 # Number of bytes of host memory used +host_seconds 82.60 # Real time elapsed on the host sim_insts 243825163 # Number of instructions simulated sim_ops 243835278 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 1306360053 # Number of bytes read from this memory -system.physmem.bytes_inst_read 977686044 # Number of instructions bytes read from this memory -system.physmem.bytes_written 91606089 # Number of bytes written to this memory -system.physmem.num_reads 326641945 # Number of read requests responded to by this memory -system.physmem.num_writes 22901951 # Number of write requests responded to by this memory -system.physmem.num_other 3886 # Number of other requests responded to by this memory -system.physmem.bw_read 10688959466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999667834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 749543566 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11438503032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 977686044 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 328674009 # Number of bytes read from this memory +system.physmem.bytes_read::total 1306360053 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 977686044 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977686044 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory +system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 244421511 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 82220434 # Number of read requests responded to by this memory +system.physmem.num_reads::total 326641945 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory +system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory +system.physmem.num_other::total 3886 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2689291633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10688959466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 749543566 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 749543566 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3438835198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11438503032 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.numCycles 244431661 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini index 861290241..e29268380 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout index 4ee289cc3..2436d9105 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:44:07 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:55:10 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 300c74bea..9186661e0 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.362431 # Nu sim_ticks 362430887000 # Number of ticks simulated final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 628265 # Simulator instruction rate (inst/s) -host_op_rate 628291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 933876298 # Simulator tick rate (ticks/s) -host_mem_usage 354916 # Number of bytes of host memory used -host_seconds 388.09 # Real time elapsed on the host +host_inst_rate 1267775 # Simulator instruction rate (inst/s) +host_op_rate 1267827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1884467398 # Simulator tick rate (ticks/s) +host_mem_usage 355400 # Number of bytes of host memory used +host_seconds 192.33 # Real time elapsed on the host sim_insts 243825163 # Number of instructions simulated sim_ops 243835278 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 1001472 # Number of bytes read from this memory -system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2560 # Number of bytes written to this memory -system.physmem.num_reads 15648 # Number of read requests responded to by this memory -system.physmem.num_writes 40 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2763208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 155219 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 7063 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 2770272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 945216 # Number of bytes read from this memory +system.physmem.bytes_read::total 1001472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 2560 # Number of bytes written to this memory +system.physmem.bytes_written::total 2560 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14769 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15648 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 40 # Number of write requests responded to by this memory +system.physmem.num_writes::total 40 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2607990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2763208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7063 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7063 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2607990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2770272 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.numCycles 724861774 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 244421512 # nu system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55857.142857 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55857.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 46620000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 935475 # number of replacements system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use @@ -160,15 +185,25 @@ system.cpu.dcache.demand_accesses::total 105122385 # nu system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.502082 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14660.150899 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14660.150899 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,15 +235,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.502082 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 865 # number of replacements system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use @@ -273,18 +318,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 939571 system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001210 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016639 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016639 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,18 +372,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001210 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016639 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016639 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |