diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt | 1536 |
1 files changed, 770 insertions, 766 deletions
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 63290598f..d813cd17b 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,75 +1,75 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061602 # Number of seconds simulated -sim_ticks 61602281500 # Number of ticks simulated -final_tick 61602281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065987 # Number of seconds simulated +sim_ticks 65986743500 # Number of ticks simulated +final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60207 # Simulator instruction rate (inst/s) -host_op_rate 106015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23475786 # Simulator tick rate (ticks/s) -host_mem_usage 445092 # Number of bytes of host memory used -host_seconds 2624.08 # Real time elapsed on the host +host_inst_rate 126294 # Simulator instruction rate (inst/s) +host_op_rate 222383 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52748930 # Simulator tick rate (ticks/s) +host_mem_usage 414760 # Number of bytes of host memory used +host_seconds 1250.96 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory -system.physmem.bytes_read::total 1946944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 12160 # Number of bytes written to this memory -system.physmem.bytes_written::total 12160 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29423 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30421 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 190 # Number of write requests responded to by this memory -system.physmem.num_writes::total 190 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1036845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 30568218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 31605063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1036845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1036845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 197395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 197395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 197395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1036845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 30568218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 31802458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30421 # Number of read requests accepted -system.physmem.writeReqs 190 # Number of write requests accepted -system.physmem.readBursts 30421 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 190 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1941440 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5504 # Total number of bytes read from write queue -system.physmem.bytesWritten 10240 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1946944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12160 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 86 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory +system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 69440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 69440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 17920 # Number of bytes written to this memory +system.physmem.bytes_written::total 17920 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29537 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30622 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 280 # Number of write requests responded to by this memory +system.physmem.num_writes::total 280 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1052333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28647693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29700026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1052333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1052333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 271570 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 271570 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 271570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1052333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28647693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29971596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30622 # Number of read requests accepted +system.physmem.writeReqs 280 # Number of write requests accepted +system.physmem.readBursts 30622 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 280 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1952768 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue +system.physmem.bytesWritten 16064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1959808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 17920 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1928 # Per bank write bursts -system.physmem.perBankRdBursts::1 2059 # Per bank write bursts -system.physmem.perBankRdBursts::2 2023 # Per bank write bursts -system.physmem.perBankRdBursts::3 1928 # Per bank write bursts -system.physmem.perBankRdBursts::4 2025 # Per bank write bursts -system.physmem.perBankRdBursts::5 1901 # Per bank write bursts -system.physmem.perBankRdBursts::6 1952 # Per bank write bursts -system.physmem.perBankRdBursts::7 1864 # Per bank write bursts -system.physmem.perBankRdBursts::8 1938 # Per bank write bursts -system.physmem.perBankRdBursts::9 1931 # Per bank write bursts -system.physmem.perBankRdBursts::10 1804 # Per bank write bursts +system.physmem.perBankRdBursts::0 1932 # Per bank write bursts +system.physmem.perBankRdBursts::1 2084 # Per bank write bursts +system.physmem.perBankRdBursts::2 2041 # Per bank write bursts +system.physmem.perBankRdBursts::3 1935 # Per bank write bursts +system.physmem.perBankRdBursts::4 2086 # Per bank write bursts +system.physmem.perBankRdBursts::5 1909 # Per bank write bursts +system.physmem.perBankRdBursts::6 1974 # Per bank write bursts +system.physmem.perBankRdBursts::7 1865 # Per bank write bursts +system.physmem.perBankRdBursts::8 1948 # Per bank write bursts +system.physmem.perBankRdBursts::9 1940 # Per bank write bursts +system.physmem.perBankRdBursts::10 1806 # Per bank write bursts system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts -system.physmem.perBankRdBursts::13 1800 # Per bank write bursts -system.physmem.perBankRdBursts::14 1818 # Per bank write bursts -system.physmem.perBankRdBursts::15 1778 # Per bank write bursts +system.physmem.perBankRdBursts::13 1799 # Per bank write bursts +system.physmem.perBankRdBursts::14 1828 # Per bank write bursts +system.physmem.perBankRdBursts::15 1779 # Per bank write bursts system.physmem.perBankWrBursts::0 10 # Per bank write bursts -system.physmem.perBankWrBursts::1 78 # Per bank write bursts -system.physmem.perBankWrBursts::2 7 # Per bank write bursts -system.physmem.perBankWrBursts::3 28 # Per bank write bursts -system.physmem.perBankWrBursts::4 6 # Per bank write bursts -system.physmem.perBankWrBursts::5 7 # Per bank write bursts +system.physmem.perBankWrBursts::1 107 # Per bank write bursts +system.physmem.perBankWrBursts::2 30 # Per bank write bursts +system.physmem.perBankWrBursts::3 12 # Per bank write bursts +system.physmem.perBankWrBursts::4 60 # Per bank write bursts +system.physmem.perBankWrBursts::5 8 # Per bank write bursts system.physmem.perBankWrBursts::6 16 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts @@ -82,26 +82,26 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61602096500 # Total gap between requests +system.physmem.totGap 65986546500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30421 # Read request sizes (log2) +system.physmem.readPktSize::6 30622 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 190 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29853 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 280 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,322 +193,331 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2721 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 716.466005 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 515.355667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.992511 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 365 13.41% 13.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 230 8.45% 21.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 123 4.52% 26.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 120 4.41% 30.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 92 3.38% 34.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 132 4.85% 39.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 112 4.12% 43.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 67 2.46% 45.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1480 54.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2721 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3363.666667 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10055.376646 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.777778 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.765969 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.666667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 8 88.89% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads -system.physmem.totQLat 133021500 # Total ticks spent queuing -system.physmem.totMemAccLat 701802750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151675000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4385.08 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2831 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 694.731190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 483.360902 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 396.952113 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 443 15.65% 15.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 258 9.11% 24.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 108 3.81% 28.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 115 4.06% 32.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 113 3.99% 36.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 115 4.06% 40.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 137 4.84% 45.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 80 2.83% 48.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1462 51.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2831 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2175.285714 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 28.380874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 8064.070078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 13 92.86% 92.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 7.14% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 14 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.928571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.918266 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.615728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 7.14% 7.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 12 85.71% 92.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 7.14% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 14 # Writes before turning the bus around for reads +system.physmem.totQLat 136557750 # Total ticks spent queuing +system.physmem.totMemAccLat 708657750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152560000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4475.54 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23135.08 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 23225.54 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.59 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.27 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.25 # Data bus utilization in percentage -system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.23 # Data bus utilization in percentage +system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 15.67 # Average write queue length when enqueuing -system.physmem.readRowHits 27658 # Number of row buffer hits during reads -system.physmem.writeRowHits 106 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 56.08 # Row buffer hit rate for writes -system.physmem.avgGap 2012416.99 # Average gap between requests -system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 121984200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 984960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2835924705 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34470717000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41469713850 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.239327 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57330547250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.53 # Average write queue length when enqueuing +system.physmem.readRowHits 27745 # Number of row buffer hits during reads +system.physmem.writeRowHits 178 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 63.57 # Row buffer hit rate for writes +system.physmem.avgGap 2135348.73 # Average gap between requests +system.physmem.pageHitRate 90.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11551680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 6303000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 123130800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1574640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3035388510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36925944000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 44413430070 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.125124 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 61414409250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2203240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2211196750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2364289750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114199800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9805320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5350125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114441600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3020047245 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34309197750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41481566430 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.431898 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57061053250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states +system.physmem_1.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3171429270 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36806601750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 44417217345 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.182663 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 61216839000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2203240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2480893250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 36908905 # Number of BP lookups -system.cpu.branchPred.condPredicted 36908905 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 741640 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 21094596 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21013333 # Number of BTB hits +system.cpu.branchPred.lookups 40828848 # Number of BP lookups +system.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26813424 # Number of BTB lookups +system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.614769 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5443330 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4414 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6079027 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 92484 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26813424 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 21202389 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 123204564 # number of cpu cycles simulated +system.cpu.numCycles 131973488 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27815555 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 199030250 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36908905 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 26456663 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 94541896 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1553195 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 366 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5275 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 27443897 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 182895 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 123139703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.847279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.366421 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30825655 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 222121094 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40828848 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27281416 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 99433771 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3060135 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 329 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 6280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 112427 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29997924 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 374431 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 131908700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.964131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.412100 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 62945303 51.12% 51.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3649645 2.96% 54.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3480674 2.83% 56.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5913881 4.80% 61.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7544216 6.13% 67.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5413971 4.40% 72.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3251108 2.64% 74.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2020095 1.64% 76.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 28920810 23.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65727022 49.83% 49.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4068693 3.08% 52.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3626407 2.75% 55.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6133247 4.65% 60.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7782444 5.90% 66.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5574161 4.23% 70.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3387073 2.57% 73.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2926863 2.22% 75.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32682790 24.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 123139703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.299574 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.615445 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12941515 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63708297 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 35887575 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9825719 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 776597 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 331225446 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 776597 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18253426 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8529207 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16791 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 40202725 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55360957 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 325142954 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1786 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 778303 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48626694 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4947433 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 327068188 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 863737810 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 532004029 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 425 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131908700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309372 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.683074 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15512553 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64273138 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40712149 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9880793 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1530067 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 365468602 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1530067 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 21068463 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11448631 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17559 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44736331 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53107649 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355543189 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 24245 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 799476 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46595900 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4792588 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 358065930 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 942303414 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 580264608 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 22491 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47855441 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 492 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 490 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66412323 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36169392 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 49401722 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8500449 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322301392 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2340 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 306103027 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 44111268 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 63882734 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1895 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 123139703 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.485819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.139102 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 78853183 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 501 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 500 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64461317 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 113156478 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38725561 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51813945 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9109294 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 346336448 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4423 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 319025181 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 175223 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 68148407 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 106206343 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3978 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131908700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.418530 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.165753 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30259811 24.57% 24.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19566759 15.89% 40.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16687041 13.55% 54.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17331203 14.07% 68.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 14759381 11.99% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12567446 10.21% 90.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6273248 5.09% 95.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3904177 3.17% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1790637 1.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 35712645 27.07% 27.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20185531 15.30% 42.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17171104 13.02% 55.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17670057 13.40% 68.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15380757 11.66% 80.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12917935 9.79% 90.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6743014 5.11% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4104772 3.11% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2022885 1.53% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 123139703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131908700 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 338800 8.53% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 197610 4.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 364922 8.93% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3529438 86.37% 95.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 191983 4.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33341 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174121950 56.88% 56.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11182 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 343 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 98066351 32.04% 88.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33869829 11.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 182585704 57.23% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11686 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 478 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 321 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101596397 31.85% 89.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34797255 10.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 306103027 # Type of FU issued -system.cpu.iq.rate 2.484510 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3969927 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 739361233 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 366454635 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 304282658 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 310039433 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 58196288 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 319025181 # Type of FU issued +system.cpu.iq.rate 2.417343 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4086343 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012809 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 774202119 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 414517759 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 314637932 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 18509 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 33754 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4413 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 323069884 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8300 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57418928 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14556809 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 63678 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 41328 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4729640 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 22377093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67905 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 65034 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7285809 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3641 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 141544 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4034 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 140997 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 776597 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5329160 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3100599 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322303732 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36169392 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1101 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3102623 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 371679 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 414776 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 786455 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 305156727 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 97750586 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 946300 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1530067 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8343953 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3020633 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 346340871 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 136261 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 113156478 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38725561 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1825 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2944 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3026950 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 65034 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 548248 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1104057 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1652305 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 316487526 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100816589 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2537655 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131430384 # number of memory reference insts executed -system.cpu.iew.exec_branches 31401849 # Number of branches executed -system.cpu.iew.exec_stores 33679798 # Number of stores executed -system.cpu.iew.exec_rate 2.476830 # Inst execution rate -system.cpu.iew.wb_sent 304565843 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 304282791 # cumulative count of insts written-back -system.cpu.iew.wb_producers 230213909 # num instructions producing a value -system.cpu.iew.wb_consumers 333860423 # num instructions consuming a value -system.cpu.iew.wb_rate 2.469736 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.689551 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 44209690 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 135188403 # number of memory reference insts executed +system.cpu.iew.exec_branches 32185799 # Number of branches executed +system.cpu.iew.exec_stores 34371814 # Number of stores executed +system.cpu.iew.exec_rate 2.398114 # Inst execution rate +system.cpu.iew.wb_sent 315304152 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 314642345 # cumulative count of insts written-back +system.cpu.iew.wb_producers 238446717 # num instructions producing a value +system.cpu.iew.wb_consumers 344411432 # num instructions consuming a value +system.cpu.iew.wb_rate 2.384133 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692331 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68273083 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 742008 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 117118936 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.375299 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.092759 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1477187 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 122118176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.278059 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.046851 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52925822 45.19% 45.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15815600 13.50% 58.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 10978628 9.37% 68.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8749337 7.47% 75.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1860126 1.59% 77.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1720772 1.47% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 865935 0.74% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 690105 0.59% 79.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23512611 20.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 56957157 46.64% 46.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16546673 13.55% 60.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11180219 9.16% 69.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8765216 7.18% 76.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2116572 1.73% 78.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1764817 1.45% 79.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 934979 0.77% 80.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 730886 0.60% 81.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23121657 18.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 117118936 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 122118176 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -554,340 +563,337 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23512611 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 416008479 # The number of ROB reads -system.cpu.rob.rob_writes 650833820 # The number of ROB writes -system.cpu.timesIdled 568 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64861 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23121657 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 445462066 # The number of ROB reads +system.cpu.rob.rob_writes 702797421 # The number of ROB writes +system.cpu.timesIdled 887 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64788 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.779832 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.779832 # CPI: Total CPI of All Threads -system.cpu.ipc 1.282327 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.282327 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 491477136 # number of integer regfile reads -system.cpu.int_regfile_writes 239432261 # number of integer regfile writes -system.cpu.fp_regfile_reads 110 # number of floating regfile reads -system.cpu.fp_regfile_writes 84 # number of floating regfile writes -system.cpu.cc_regfile_reads 107533030 # number of cc regfile reads -system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes -system.cpu.misc_regfile_reads 195275946 # number of misc regfile reads +system.cpu.cpi 0.835336 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.835336 # CPI: Total CPI of All Threads +system.cpu.ipc 1.197123 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.197123 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 504041942 # number of integer regfile reads +system.cpu.int_regfile_writes 248656420 # number of integer regfile writes +system.cpu.fp_regfile_reads 4180 # number of floating regfile reads +system.cpu.fp_regfile_writes 782 # number of floating regfile writes +system.cpu.cc_regfile_reads 109261684 # number of cc regfile reads +system.cpu.cc_regfile_writes 65602098 # number of cc regfile writes +system.cpu.misc_regfile_reads 202573497 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2072312 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.008256 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 68071038 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076408 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32.783074 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 19455459500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.008256 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993166 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993166 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2073508 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077604 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.604569 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21372047500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.413497 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993265 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993265 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 633 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3336 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3404 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 143788642 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 143788642 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 36725212 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 36725212 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345825 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345825 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68071037 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68071037 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68071037 # number of overall hits -system.cpu.dcache.overall_hits::total 68071037 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2691153 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2691153 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93927 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93927 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2785080 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2785080 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2785080 # number of overall misses -system.cpu.dcache.overall_misses::total 2785080 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304195500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32304195500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956614994 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2956614994 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35260810494 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35260810494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35260810494 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35260810494 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 39416365 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 39416365 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31346019 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71894591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71894591 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71894591 # number of overall hits +system.cpu.dcache.overall_hits::total 71894591 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2693971 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2693971 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93733 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93733 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2787704 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2787704 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2787704 # number of overall misses +system.cpu.dcache.overall_misses::total 2787704 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32332975500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32332975500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2952822993 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2952822993 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35285798493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35285798493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35285798493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35285798493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 43242543 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 43242543 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 70856117 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 70856117 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 70856117 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 70856117 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002988 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.849465 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.849465 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.796523 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.796523 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12660.609567 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12660.609567 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 221476 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43220 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124387 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74682295 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74682295 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74682295 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74682295 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062299 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.062299 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037328 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037328 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037328 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037328 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12001.976079 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12001.976079 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31502.491044 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31502.491044 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12657.656083 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12657.656083 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 219202 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 497 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43207 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.073298 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 124.250000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066601 # number of writebacks -system.cpu.dcache.writebacks::total 2066601 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 696788 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 696788 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2066969 # number of writebacks +system.cpu.dcache.writebacks::total 2066969 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698217 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 698217 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 708671 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 708671 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 708671 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 708671 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994365 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994365 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82044 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076409 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076409 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076409 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076409 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24195923000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24195923000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995319995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26995319995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995319995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26995319995 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.143815 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.143815 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13000.964644 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.964644 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.964644 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13000.964644 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 710100 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 710100 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 710100 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 710100 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995754 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1995754 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81850 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81850 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2077604 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2077604 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2077604 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2077604 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24221413500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24221413500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2795777993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2795777993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27017191493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27017191493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27017191493 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27017191493 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046153 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046153 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002603 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002603 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027819 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.472481 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.472481 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 53 # number of replacements -system.cpu.icache.tags.tagsinuse 825.039758 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27442574 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 27090.398815 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 93 # number of replacements +system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1113 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26951.013477 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 825.039758 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.402851 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.402851 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 870.928206 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.425258 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.425258 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1020 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 870 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 54888808 # Number of tag accesses -system.cpu.icache.tags.data_accesses 54888808 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27442574 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27442574 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27442574 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27442574 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27442574 # number of overall hits -system.cpu.icache.overall_hits::total 27442574 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1323 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1323 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1323 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1323 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1323 # number of overall misses -system.cpu.icache.overall_misses::total 1323 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 97204000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 97204000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 97204000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 97204000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 97204000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 97204000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27443897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27443897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27443897 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27443897 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27443897 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27443897 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 34 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses +system.cpu.icache.tags.data_accesses 59996959 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 29996478 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 29996478 # number of overall hits +system.cpu.icache.overall_hits::total 29996478 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1445 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1445 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1445 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1445 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1445 # number of overall misses +system.cpu.icache.overall_misses::total 1445 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 106088999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 106088999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 106088999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 106088999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 106088999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 106088999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 29997923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 29997923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 29997923 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 29997923 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 29997923 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 29997923 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73472.411187 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73417.992388 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73417.992388 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73417.992388 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73417.992388 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73417.992388 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73417.992388 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 515 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # 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number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1014 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1014 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1014 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1014 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77418000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 77418000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77418000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 77418000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77418000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 77418000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 93 # number of writebacks +system.cpu.icache.writebacks::total 93 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 332 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 332 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 332 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 332 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 332 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 332 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1113 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1113 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1113 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1113 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1113 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1113 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 84684499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 84684499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 84684499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 84684499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 84684499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 84684499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76349.112426 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76349.112426 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76086.701707 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76086.701707 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 493 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20711.322176 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4035102 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30410 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.689970 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 650 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30622 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 131.854680 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19791.559632 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841856 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 244.920687 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.603990 # 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average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76228.110599 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78210.810811 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78210.810811 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76228.110599 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73144.412093 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73253.673829 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76228.110599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73144.412093 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73253.673829 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -896,123 +902,121 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 190 # number of writebacks -system.cpu.l2cache.writebacks::total 190 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 998 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 998 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 425 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 425 # 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number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28385000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65737000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856543000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1922280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65737000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856543000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1922280000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353337 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.984221 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000213 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000213 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.278916 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.278916 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65868.737475 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65868.737475 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66788.235294 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66788.235294 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 280 # number of writebacks +system.cpu.l2cache.writebacks::total 280 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28982 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28982 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1085 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1085 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 555 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 555 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1085 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29537 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30622 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1085 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29537 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30622 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827239500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827239500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 71857500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 71857500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 37857000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 37857000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71857500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1865096500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1936954000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71857500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1865096500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1936954000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353922 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353922 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974843 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000278 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014731 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014731 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63047.391484 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63047.391484 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66228.110599 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66228.110599 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68210.810811 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68210.810811 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4149788 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072369 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4152318 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073604 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1995353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2066791 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 53 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994339 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225130 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6227211 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265220864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 493 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2077916 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000156 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012505 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6909 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1113 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995716 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2319 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228716 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6231035 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265252672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265329856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 650 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2079367 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2077591 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 325 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2079019 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 348 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2077916 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4141548000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2079367 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4143221000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1670997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3114612500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1423 # Transaction distribution -system.membus.trans_dist::WritebackDirty 190 # Transaction distribution -system.membus.trans_dist::CleanEvict 24 # Transaction distribution -system.membus.trans_dist::ReadExReq 28998 # Transaction distribution -system.membus.trans_dist::ReadExResp 28998 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1423 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61056 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1959104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1959104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1959104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1640 # Transaction distribution +system.membus.trans_dist::WritebackDirty 280 # Transaction distribution +system.membus.trans_dist::CleanEvict 45 # Transaction distribution +system.membus.trans_dist::ReadExReq 28982 # Transaction distribution +system.membus.trans_dist::ReadExResp 28982 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1640 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61569 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1977728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1977728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1977728 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30635 # Request fanout histogram +system.membus.snoop_fanout::samples 30947 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30635 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30947 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30635 # Request fanout histogram -system.membus.reqLayer0.occupancy 42769000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30947 # Request fanout histogram +system.membus.reqLayer0.occupancy 43483000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 160316500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 161384500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |