diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref/x86/linux/o3-timing')
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini | 41 | ||||
| -rwxr-xr-x | tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout | 10 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt | 1562 |
3 files changed, 817 insertions, 796 deletions
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index fa42af61f..e54b7db9f 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -179,7 +179,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -552,7 +552,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -639,7 +639,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -756,6 +756,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -767,7 +768,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -775,29 +776,36 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -817,6 +825,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -826,7 +835,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -848,9 +857,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index e1bfb6d2d..9e929c5a5 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:18 -gem5 executing on e108600-lin, pid 18558 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:08:11 +gem5 executing on e108600-lin, pid 17630 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -21,11 +21,11 @@ active arcs : 1905 simplex iterations : 1502 info: Increasing stack size by one page. flow value : 4990014995 +info: Increasing stack size by one page. new implicit arcs : 23867 active arcs : 25772 -info: Increasing stack size by one page. simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 65986743500 because target called exit() +Exiting @ tick 66079350000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 1e87ba0e2..dac7009e5 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,80 +1,80 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065554 # Number of seconds simulated -sim_ticks 65553895500 # Number of ticks simulated -final_tick 65553895500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.066079 # Number of seconds simulated +sim_ticks 66079350000 # Number of ticks simulated +final_tick 66079350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122580 # Simulator instruction rate (inst/s) -host_op_rate 215844 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50862026 # Simulator tick rate (ticks/s) -host_mem_usage 417260 # Number of bytes of host memory used -host_seconds 1288.86 # Real time elapsed on the host +host_inst_rate 104457 # Simulator instruction rate (inst/s) +host_op_rate 183932 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43689609 # Simulator tick rate (ticks/s) +host_mem_usage 414668 # Number of bytes of host memory used +host_seconds 1512.47 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 69632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1890944 # Number of bytes read from this memory -system.physmem.bytes_read::total 1960576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 69632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 69632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 17920 # Number of bytes written to this memory -system.physmem.bytes_written::total 17920 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1088 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29546 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30634 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 280 # Number of write requests responded to by this memory -system.physmem.num_writes::total 280 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1062210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28845639 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29907849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1062210 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1062210 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 273363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 273363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 273363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1062210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28845639 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 30181212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30634 # Number of read requests accepted -system.physmem.writeReqs 280 # Number of write requests accepted -system.physmem.readBursts 30634 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 280 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1951616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue -system.physmem.bytesWritten 16000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1960576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 17920 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 69696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1892800 # Number of bytes read from this memory +system.physmem.bytes_read::total 1962496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 69696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 69696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 19520 # Number of bytes written to this memory +system.physmem.bytes_written::total 19520 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29575 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30664 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 305 # Number of write requests responded to by this memory +system.physmem.num_writes::total 305 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1054732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28644350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29699081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1054732 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1054732 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 295402 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 295402 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 295402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1054732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28644350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29994484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30664 # Number of read requests accepted +system.physmem.writeReqs 305 # Number of write requests accepted +system.physmem.readBursts 30664 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 305 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1952768 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue +system.physmem.bytesWritten 18368 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1962496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 19520 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1938 # Per bank write bursts -system.physmem.perBankRdBursts::1 2083 # Per bank write bursts +system.physmem.perBankRdBursts::0 1940 # Per bank write bursts +system.physmem.perBankRdBursts::1 2080 # Per bank write bursts system.physmem.perBankRdBursts::2 2040 # Per bank write bursts -system.physmem.perBankRdBursts::3 1941 # Per bank write bursts -system.physmem.perBankRdBursts::4 2041 # Per bank write bursts -system.physmem.perBankRdBursts::5 1918 # Per bank write bursts -system.physmem.perBankRdBursts::6 1976 # Per bank write bursts +system.physmem.perBankRdBursts::3 1947 # Per bank write bursts +system.physmem.perBankRdBursts::4 2062 # Per bank write bursts +system.physmem.perBankRdBursts::5 1911 # Per bank write bursts +system.physmem.perBankRdBursts::6 1975 # Per bank write bursts system.physmem.perBankRdBursts::7 1870 # Per bank write bursts system.physmem.perBankRdBursts::8 1951 # Per bank write bursts -system.physmem.perBankRdBursts::9 1940 # Per bank write bursts +system.physmem.perBankRdBursts::9 1941 # Per bank write bursts system.physmem.perBankRdBursts::10 1805 # Per bank write bursts system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1799 # Per bank write bursts -system.physmem.perBankRdBursts::14 1827 # Per bank write bursts +system.physmem.perBankRdBursts::14 1826 # Per bank write bursts system.physmem.perBankRdBursts::15 1779 # Per bank write bursts -system.physmem.perBankWrBursts::0 10 # Per bank write bursts -system.physmem.perBankWrBursts::1 107 # Per bank write bursts -system.physmem.perBankWrBursts::2 31 # Per bank write bursts -system.physmem.perBankWrBursts::3 25 # Per bank write bursts -system.physmem.perBankWrBursts::4 39 # Per bank write bursts -system.physmem.perBankWrBursts::5 13 # Per bank write bursts -system.physmem.perBankWrBursts::6 16 # Per bank write bursts +system.physmem.perBankWrBursts::0 26 # Per bank write bursts +system.physmem.perBankWrBursts::1 125 # Per bank write bursts +system.physmem.perBankWrBursts::2 27 # Per bank write bursts +system.physmem.perBankWrBursts::3 24 # Per bank write bursts +system.physmem.perBankWrBursts::4 54 # Per bank write bursts +system.physmem.perBankWrBursts::5 3 # Per bank write bursts +system.physmem.perBankWrBursts::6 18 # Per bank write bursts system.physmem.perBankWrBursts::7 1 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 5 # Per bank write bursts +system.physmem.perBankWrBursts::9 6 # Per bank write bursts system.physmem.perBankWrBursts::10 3 # Per bank write bursts system.physmem.perBankWrBursts::11 0 # Per bank write bursts system.physmem.perBankWrBursts::12 0 # Per bank write bursts @@ -83,28 +83,28 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 65553697500 # Total gap between requests +system.physmem.totGap 66079146500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30634 # Read request sizes (log2) +system.physmem.readPktSize::6 30664 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 280 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 305 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29931 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -147,24 +147,24 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,335 +194,347 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2859 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 687.860091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 477.665686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.129385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 441 15.42% 15.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 263 9.20% 24.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 134 4.69% 29.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 136 4.76% 34.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 118 4.13% 38.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 116 4.06% 42.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 85 2.97% 45.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 96 3.36% 48.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1470 51.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2859 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2173.928571 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 21.222071 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 8074.812153 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 13 92.86% 92.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 7.14% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 14 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.857143 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.849200 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.534522 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1 7.14% 7.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 13 92.86% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 14 # Writes before turning the bus around for reads -system.physmem.totQLat 136299000 # Total ticks spent queuing -system.physmem.totMemAccLat 708061500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 152470000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4469.70 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 685.122783 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 477.283945 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 398.354531 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 431 14.99% 14.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 281 9.77% 24.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 140 4.87% 29.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 134 4.66% 34.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 130 4.52% 38.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 125 4.35% 43.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 77 2.68% 45.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 84 2.92% 48.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1473 51.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2875 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 1904.687500 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.337942 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7552.888425 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 15 93.75% 93.75% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 6.25% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.937500 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.900644 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.181454 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3 18.75% 18.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 10 62.50% 81.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 6.25% 87.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 12.50% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads +system.physmem.totQLat 407578000 # Total ticks spent queuing +system.physmem.totMemAccLat 979678000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152560000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13357.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23219.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.91 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.27 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32107.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.28 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.62 # Average write queue length when enqueuing -system.physmem.readRowHits 27721 # Number of row buffer hits during reads -system.physmem.writeRowHits 161 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.91 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.50 # Row buffer hit rate for writes -system.physmem.avgGap 2120518.13 # Average gap between requests -system.physmem.pageHitRate 90.60 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 11740680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 6406125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 123169800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1568160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4281566640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3052855305 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36653676000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 44130982710 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.213820 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 60959756000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2188940000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2404016500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9873360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5387250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114558600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4281566640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3230070300 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36498224250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 44139732240 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.347293 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 60700713000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2188940000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2663059500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40360668 # Number of BP lookups -system.cpu.branchPred.condPredicted 40360668 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1392637 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26664097 # Number of BTB lookups +system.physmem.avgWrQLen 15.50 # Average write queue length when enqueuing +system.physmem.readRowHits 27718 # Number of row buffer hits during reads +system.physmem.writeRowHits 199 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.25 # Row buffer hit rate for writes +system.physmem.avgGap 2133719.09 # Average gap between requests +system.physmem.pageHitRate 90.59 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11095560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5886045 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 112990500 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1451160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 311007840.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 261882510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 17017920 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 979925760 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 266852640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 15064489440 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 17032599375 # Total energy per rank (pJ) +system.physmem_0.averagePower 257.759790 # Core power per rank (mW) +system.physmem_0.totalIdleTime 65460562250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 23034750 # Time in different power states +system.physmem_0.memoryStateTime::REF 131986000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 62616842500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 694916500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 463599750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 2148970500 # Time in different power states +system.physmem_1.actEnergy 9481920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5024580 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 104865180 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 46980 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 381691440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 255809160 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 19980960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1151008410 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 399268320 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14907041175 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 17234823375 # Total energy per rank (pJ) +system.physmem_1.averagePower 260.820111 # Core power per rank (mW) +system.physmem_1.totalIdleTime 65463256000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 30077000 # Time in different power states +system.physmem_1.memoryStateTime::REF 162078000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 61901089500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1039749000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 422083750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 2524272750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40670761 # Number of BP lookups +system.cpu.branchPred.condPredicted 40670761 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1447235 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26704882 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5988252 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 86625 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26664097 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 21157452 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5506645 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 511906 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 6058055 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 92918 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26704882 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 21174798 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5530084 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 547932 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 131107792 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 132158701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30523578 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 219647427 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40360668 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 27145704 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 98945290 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2900833 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 518 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 6239 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 114030 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 50 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 29742559 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 352958 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 20 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 131040277 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.949675 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.407509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30720551 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 221310466 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40670761 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27232853 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 99729501 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3011659 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 476 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 6367 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 115460 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 59 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 223 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29905952 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 367398 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 15 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 132078466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.949325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.409240 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65532629 50.01% 50.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4015050 3.06% 53.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3611452 2.76% 55.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6110552 4.66% 60.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7743592 5.91% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5553299 4.24% 70.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3377797 2.58% 73.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2818268 2.15% 75.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32277638 24.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66113924 50.06% 50.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4057337 3.07% 53.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3620378 2.74% 55.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6125698 4.64% 60.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7769884 5.88% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5562288 4.21% 70.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3378570 2.56% 73.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2898316 2.19% 75.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32552071 24.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131040277 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307843 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.675319 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15257836 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64260169 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 40205069 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9866787 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1450416 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 361840570 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1450416 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20789312 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11161609 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17754 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 44252475 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53368711 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 352352816 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 16475 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 802883 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 46797603 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4838735 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 354809982 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 933969547 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 575070468 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 25233 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 132078466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307742 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.674581 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15424627 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64723504 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40539404 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9885102 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1505829 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 364367574 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1505829 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20975204 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11377644 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18396 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44575622 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53625771 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 354569179 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 16511 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 791289 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46695905 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5223216 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 357047318 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 939748965 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 578695140 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 22535 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 75597235 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 487 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 488 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 64661942 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112312024 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38476139 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 51587404 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9144280 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343861767 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4715 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 317818488 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 169830 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 65674018 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 101673382 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4270 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131040277 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.425350 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.164581 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 77834571 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 494 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 495 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64563941 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112883257 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38651230 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51754424 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9024100 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 345545955 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4258 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 318634973 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 172634 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 67357749 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 104786759 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3813 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 132078466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.412467 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.166876 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 35194225 26.86% 26.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20112862 15.35% 42.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17093441 13.04% 55.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17641161 13.46% 68.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15328111 11.70% 80.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12869587 9.82% 90.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6689257 5.10% 95.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4093724 3.12% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2017909 1.54% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 36007190 27.26% 27.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20156467 15.26% 42.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17165000 13.00% 55.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17631185 13.35% 68.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15357300 11.63% 80.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12905365 9.77% 90.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6726655 5.09% 95.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4095436 3.10% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2033868 1.54% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131040277 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 132078466 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 366862 8.95% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3538662 86.29% 95.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 195200 4.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 366214 8.93% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3544036 86.42% 95.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 190508 4.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 181791277 57.20% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11724 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 408 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 305 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101272470 31.86% 89.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34708964 10.92% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 182328648 57.22% 57.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11540 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 353 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 275 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101489755 31.85% 89.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34771062 10.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 317818488 # Type of FU issued -system.cpu.iq.rate 2.424101 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4100724 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012903 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 770927721 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 409562927 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 313648272 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 20086 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 38326 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4607 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 321877132 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8740 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57541030 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 318634973 # Type of FU issued +system.cpu.iq.rate 2.411003 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4100758 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012870 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 773602517 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 412934380 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 314305089 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 19287 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 34996 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4478 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 322693854 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8537 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57471685 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 21532639 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67356 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 63407 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7036387 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 22103872 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67270 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 64283 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7211478 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3908 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 141249 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3969 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 140998 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1450416 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8045146 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3020269 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343866482 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 122594 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112312024 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38476139 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1910 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3213 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3025719 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 63407 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 529775 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1033204 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1562979 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 315414153 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100518036 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2404335 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1505829 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8247421 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3042364 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 345550213 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 133191 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112883257 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38651230 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1745 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2963 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3048582 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 64283 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 545574 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1082259 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1627833 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 316133024 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100718075 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2501949 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 134824639 # number of memory reference insts executed -system.cpu.iew.exec_branches 32104448 # Number of branches executed -system.cpu.iew.exec_stores 34306603 # Number of stores executed -system.cpu.iew.exec_rate 2.405762 # Inst execution rate -system.cpu.iew.wb_sent 314286106 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 313652879 # cumulative count of insts written-back -system.cpu.iew.wb_producers 237682188 # num instructions producing a value -system.cpu.iew.wb_consumers 343423954 # num instructions consuming a value -system.cpu.iew.wb_rate 2.392328 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 65797430 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 135067596 # number of memory reference insts executed +system.cpu.iew.exec_branches 32155475 # Number of branches executed +system.cpu.iew.exec_stores 34349521 # Number of stores executed +system.cpu.iew.exec_rate 2.392071 # Inst execution rate +system.cpu.iew.wb_sent 314966910 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 314309567 # cumulative count of insts written-back +system.cpu.iew.wb_producers 238188610 # num instructions producing a value +system.cpu.iew.wb_consumers 344086280 # num instructions consuming a value +system.cpu.iew.wb_rate 2.378274 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692235 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 67483313 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1399141 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 121633848 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.287130 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.051606 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1453904 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 122408865 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.272650 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.045643 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 56556051 46.50% 46.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16464352 13.54% 60.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11233282 9.24% 69.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8748892 7.19% 76.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2045691 1.68% 78.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1756798 1.44% 79.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 927336 0.76% 80.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 727466 0.60% 80.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23173980 19.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57244612 46.77% 46.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16526306 13.50% 60.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11253907 9.19% 69.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8747083 7.15% 76.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2074138 1.69% 78.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1764583 1.44% 79.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 930878 0.76% 80.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 726504 0.59% 81.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23140854 18.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 121633848 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 122408865 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -568,466 +580,466 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23173980 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 442449762 # The number of ROB reads -system.cpu.rob.rob_writes 697455131 # The number of ROB writes -system.cpu.timesIdled 919 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 67515 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23140854 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 444943788 # The number of ROB reads +system.cpu.rob.rob_writes 701094607 # The number of ROB writes +system.cpu.timesIdled 892 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 80235 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.829856 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.829856 # CPI: Total CPI of All Threads -system.cpu.ipc 1.205028 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.205028 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 502814986 # number of integer regfile reads -system.cpu.int_regfile_writes 247784196 # number of integer regfile writes -system.cpu.fp_regfile_reads 4396 # number of floating regfile reads -system.cpu.fp_regfile_writes 732 # number of floating regfile writes -system.cpu.cc_regfile_reads 109093589 # number of cc regfile reads -system.cpu.cc_regfile_writes 65488596 # number of cc regfile writes -system.cpu.misc_regfile_reads 201890594 # number of misc regfile reads +system.cpu.cpi 0.836508 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.836508 # CPI: Total CPI of All Threads +system.cpu.ipc 1.195446 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.195446 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 503639899 # number of integer regfile reads +system.cpu.int_regfile_writes 248370602 # number of integer regfile writes +system.cpu.fp_regfile_reads 4288 # number of floating regfile reads +system.cpu.fp_regfile_writes 677 # number of floating regfile writes +system.cpu.cc_regfile_reads 109192725 # number of cc regfile reads +system.cpu.cc_regfile_writes 65564647 # number of cc regfile writes +system.cpu.misc_regfile_reads 202344104 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2073601 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.108072 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71473739 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2077697 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.400463 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21041764500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.108072 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993190 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993190 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2073334 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.317880 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71743454 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077430 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.534715 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21320595500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.317880 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992998 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992998 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 507 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3433 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 505 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3441 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 150601371 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 150601371 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 40127755 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40127755 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345984 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345984 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71473739 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71473739 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71473739 # number of overall hits -system.cpu.dcache.overall_hits::total 71473739 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2694330 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2694330 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93768 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93768 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2788098 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2788098 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2788098 # number of overall misses -system.cpu.dcache.overall_misses::total 2788098 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32345718500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32345718500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2982305493 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2982305493 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35328023993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35328023993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35328023993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35328023993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42822085 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42822085 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 151138894 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 151138894 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 40397499 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40397499 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345955 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345955 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71743454 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71743454 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71743454 # number of overall hits +system.cpu.dcache.overall_hits::total 71743454 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2693481 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2693481 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93797 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93797 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2787278 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2787278 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2787278 # number of overall misses +system.cpu.dcache.overall_misses::total 2787278 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32417345000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32417345000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3182155993 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3182155993 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35599500993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35599500993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35599500993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35599500993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 43090980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 43090980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74261837 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74261837 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74261837 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74261837 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062919 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062919 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002982 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002982 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037544 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037544 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037544 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037544 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12005.106464 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12005.106464 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31805.152003 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31805.152003 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12671.012279 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12671.012279 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12671.012279 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12671.012279 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 218790 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 393 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43059 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74530732 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74530732 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74530732 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74530732 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062507 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.062507 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002983 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002983 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037398 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037398 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037398 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037398 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12035.483079 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12035.483079 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33925.989029 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33925.989029 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12772.138622 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12772.138622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12772.138622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12772.138622 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 219409 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 385 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43429 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.081168 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 98.250000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2067196 # number of writebacks -system.cpu.dcache.writebacks::total 2067196 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698496 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 698496 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11905 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11905 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 710401 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 710401 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 710401 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 710401 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995834 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1995834 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81863 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81863 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077697 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077697 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077697 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077697 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24223051500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24223051500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2825101993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2825101993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27048153493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27048153493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27048153493 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27048153493 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046608 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046608 # mshr miss rate for ReadReq accesses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.052131 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 96.250000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2066585 # number of writebacks +system.cpu.dcache.writebacks::total 2066585 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 697929 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 697929 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11919 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11919 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 709848 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 709848 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 709848 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 709848 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995552 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1995552 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81878 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81878 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2077430 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2077430 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2077430 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2077430 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24266554500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24266554500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3024734993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3024734993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27291289493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27291289493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27291289493 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27291289493 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046310 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046310 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002604 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002604 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027978 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027978 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027978 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027978 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.806718 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.806718 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34510.120482 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34510.120482 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13018.333998 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13018.333998 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13018.333998 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13018.333998 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 91 # number of replacements -system.cpu.icache.tags.tagsinuse 875.979350 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 29741086 # Total number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027873 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027873 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027873 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027873 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12160.321806 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12160.321806 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36941.974560 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36941.974560 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13137.044085 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13137.044085 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13137.044085 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13137.044085 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 94 # number of replacements +system.cpu.icache.tags.tagsinuse 871.416193 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29904477 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1117 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26625.860340 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 26772.136974 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 875.979350 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.427724 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.427724 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1026 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 914 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.500977 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59486235 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59486235 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 29741086 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 29741086 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 29741086 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 29741086 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 29741086 # number of overall hits -system.cpu.icache.overall_hits::total 29741086 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1473 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1473 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1473 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1473 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1473 # number of overall misses -system.cpu.icache.overall_misses::total 1473 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 110309999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 110309999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 110309999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 110309999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 110309999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 110309999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 29742559 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 29742559 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 29742559 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 29742559 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 29742559 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 29742559 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74887.983028 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74887.983028 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74887.983028 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74887.983028 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74887.983028 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74887.983028 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1013 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 871.416193 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.425496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.425496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1023 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 905 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.499512 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 59813021 # Number of tag accesses +system.cpu.icache.tags.data_accesses 59813021 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 29904477 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 29904477 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 29904477 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 29904477 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 29904477 # number of overall hits +system.cpu.icache.overall_hits::total 29904477 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1475 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1475 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1475 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1475 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1475 # number of overall misses +system.cpu.icache.overall_misses::total 1475 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 154630499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 154630499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 154630499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 154630499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 154630499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 154630499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 29905952 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 29905952 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 29905952 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 29905952 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 29905952 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 29905952 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000049 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000049 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000049 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000049 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 104834.236610 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 104834.236610 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 104834.236610 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 104834.236610 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 104834.236610 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 104834.236610 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3285 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 77.923077 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 219 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 91 # number of writebacks -system.cpu.icache.writebacks::total 91 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 356 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 356 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 356 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 356 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 356 # number of overall MSHR hits +system.cpu.icache.writebacks::writebacks 94 # number of writebacks +system.cpu.icache.writebacks::total 94 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 358 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 358 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 358 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 358 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 358 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1117 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 1117 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 1117 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 1117 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1117 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1117 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86959999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 86959999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86959999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 86959999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86959999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 86959999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000038 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000038 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000038 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77851.386750 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77851.386750 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77851.386750 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77851.386750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77851.386750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77851.386750 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 663 # number of replacements -system.cpu.l2cache.tags.tagsinuse 21665.639104 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4121840 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30651 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 134.476526 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 115157499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 115157499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 115157499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 115157499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 115157499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 115157499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 103095.343778 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 103095.343778 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 103095.343778 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 103095.343778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 103095.343778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 103095.343778 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 694 # number of replacements +system.cpu.l2cache.tags.tagsinuse 21600.967235 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4121275 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30681 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 134.326619 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # 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number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 36573000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74082000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1893079500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1967161500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74082000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1893079500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1967161500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.354004 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.354004 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974038 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000279 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000279 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014736 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014736 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64041.757218 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64041.757218 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68090.073529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68090.073529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65660.682226 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65660.682226 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68090.073529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64072.277127 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64214.973559 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68090.073529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64072.277127 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64214.973559 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4152506 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073696 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.writebacks::writebacks 305 # number of writebacks +system.cpu.l2cache.writebacks::total 305 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28997 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28997 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1089 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1089 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 578 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 578 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1089 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30664 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1089 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29575 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30664 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2055885500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2055885500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 102284000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 102284000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 81897000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 81897000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 102284000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2137782500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2240066500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 102284000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2137782500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2240066500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353937 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353937 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974933 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000290 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000290 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014236 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014753 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974933 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014236 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014753 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70899.937925 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70899.937925 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93924.701561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93924.701561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 141690.311419 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 141690.311419 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93924.701561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72283.431953 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73051.999087 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93924.701561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72283.431953 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73051.999087 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4151975 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073430 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 19 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 331 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1996925 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2067476 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 91 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81889 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1996620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2066890 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 94 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 7138 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81927 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81927 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 1117 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995808 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2325 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228995 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6231320 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265273152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265350464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 663 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 17920 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2079477 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000168 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012972 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995503 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2328 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6230522 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265216960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265294464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 694 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19520 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2079241 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000169 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.013010 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2079127 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 350 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2078889 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 352 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2079477 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4143540000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2079241 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4142666500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1675999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3116545500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 30966 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 332 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.respLayer1.occupancy 3116145000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 31027 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 363 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1645 # Transaction distribution -system.membus.trans_dist::WritebackDirty 280 # Transaction distribution -system.membus.trans_dist::CleanEvict 52 # Transaction distribution -system.membus.trans_dist::ReadExReq 28989 # Transaction distribution -system.membus.trans_dist::ReadExResp 28989 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1645 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61600 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61600 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61600 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1978496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1978496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1978496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 66079350000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1667 # Transaction distribution +system.membus.trans_dist::WritebackDirty 305 # Transaction distribution +system.membus.trans_dist::CleanEvict 58 # Transaction distribution +system.membus.trans_dist::ReadExReq 28997 # Transaction distribution +system.membus.trans_dist::ReadExResp 28997 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1667 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61691 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61691 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61691 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1982016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1982016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1982016 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30634 # Request fanout histogram +system.membus.snoop_fanout::samples 30664 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30634 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30664 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30634 # Request fanout histogram -system.membus.reqLayer0.occupancy 43502500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30664 # Request fanout histogram +system.membus.reqLayer0.occupancy 43847500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 161439750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 161573250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |