diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt | 78 |
1 files changed, 39 insertions, 39 deletions
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index c24d579f7..2cdeaff80 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.365989 # Number of seconds simulated -sim_ticks 365989063000 # Number of ticks simulated -final_tick 365989063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 365989064000 # Number of ticks simulated +final_tick 365989064000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 621192 # Simulator instruction rate (inst/s) -host_op_rate 1093819 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1439024491 # Simulator tick rate (ticks/s) -host_mem_usage 361884 # Number of bytes of host memory used -host_seconds 254.33 # Real time elapsed on the host +host_inst_rate 426513 # Simulator instruction rate (inst/s) +host_op_rate 751021 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 988040650 # Simulator tick rate (ticks/s) +host_mem_usage 411308 # Number of bytes of host memory used +host_seconds 370.42 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated -sim_ops 278192463 # Number of ops (including micro ops) simulated +sim_ops 278192464 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory @@ -35,35 +35,35 @@ system.physmem.bw_total::cpu.inst 140419 # To system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 731978126 # number of cpu cycles simulated +system.cpu.numCycles 731978128 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed -system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses +system.cpu.committedOps 278192464 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 278186173 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls -system.cpu.num_int_insts 278186171 # number of integer instructions +system.cpu.num_int_insts 278186173 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 739519993 # number of times the integer registers were read -system.cpu.num_int_register_writes 279212718 # number of times the integer registers were written +system.cpu.num_int_register_reads 739519998 # number of times the integer registers were read +system.cpu.num_int_register_writes 279212719 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_mem_refs 122219135 # number of memory refs +system.cpu.num_mem_refs 122219136 # number of memory refs system.cpu.num_load_insts 90779384 # Number of load instructions -system.cpu.num_store_insts 31439751 # Number of store instructions +system.cpu.num_store_insts 31439752 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 731978126 # Number of busy cycles +system.cpu.num_busy_cycles 731978128 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 665.632511 # Cycle average of tags in use +system.cpu.icache.tagsinuse 665.632509 # Cycle average of tags in use system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 665.632511 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 665.632509 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits @@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2062733 # number of replacements -system.cpu.dcache.tagsinuse 4076.488641 # Cycle average of tags in use -system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4076.488630 # Cycle average of tags in use +system.cpu.dcache.total_refs 120152369 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126079699000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.488641 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126079700000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.488630 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 120152368 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 120152368 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 120152368 # number of overall hits -system.cpu.dcache.overall_hits::total 120152368 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 120152369 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 120152369 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 120152369 # number of overall hits +system.cpu.dcache.overall_hits::total 120152369 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses @@ -170,12 +170,12 @@ system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 122219197 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 122219197 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 122219197 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 122219197 # number of overall (read+write) accesses +system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 122219198 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 122219198 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 122219198 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 122219198 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses @@ -236,13 +236,13 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 318 # number of replacements -system.cpu.l2cache.tagsinuse 20041.899874 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 20041.899820 # Cycle average of tags in use system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19330.353270 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 557.646384 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 19330.353217 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 557.646383 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 153.900220 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy |