diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref/x86')
9 files changed, 611 insertions, 400 deletions
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 546611c4c..f9591bc5c 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -442,20 +435,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -494,20 +480,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -531,14 +510,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 1c8484fc7..90035090e 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 9 2012 12:45:55 -gem5 started Feb 9 2012 12:46:40 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:13:01 +gem5 executing on zizzer +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 0040f922c..1bd6324e3 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.070047 # Nu sim_ticks 70046988500 # Number of ticks simulated final_tick 70046988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78701 # Simulator instruction rate (inst/s) -host_tick_rate 19816485 # Simulator tick rate (ticks/s) -host_mem_usage 388420 # Number of bytes of host memory used -host_seconds 3534.78 # Real time elapsed on the host -sim_insts 278192519 # Number of instructions simulated +host_inst_rate 120922 # Simulator instruction rate (inst/s) +host_op_rate 212925 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53613076 # Simulator tick rate (ticks/s) +host_mem_usage 355612 # Number of bytes of host memory used +host_seconds 1306.53 # Real time elapsed on the host +sim_insts 157988582 # Number of instructions simulated +sim_ops 278192519 # Number of ops (including micro ops) simulated system.physmem.bytes_read 3895936 # Number of bytes read from this memory system.physmem.bytes_inst_read 65216 # Number of instructions bytes read from this memory system.physmem.bytes_written 892288 # Number of bytes written to this memory @@ -236,7 +238,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 2.229177 # insts written-back per cycle system.cpu.iew.wb_fanout 0.730584 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions +system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions system.cpu.commit.commitSquashedInsts 65103374 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1332005 # The number of times a branch was mispredicted @@ -257,7 +260,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 130436298 # Number of insts commited each cycle -system.cpu.commit.count 278192519 # Number of instructions committed +system.cpu.commit.committedInsts 157988582 # Number of instructions committed +system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 122219139 # Number of memory references committed system.cpu.commit.loads 90779388 # Number of loads committed @@ -272,12 +276,13 @@ system.cpu.rob.rob_reads 457952368 # Th system.cpu.rob.rob_writes 695479183 # The number of ROB writes system.cpu.timesIdled 23894 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 787486 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 278192519 # Number of Instructions Simulated -system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated -system.cpu.cpi 0.503586 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.503586 # CPI: Total CPI of All Threads -system.cpu.ipc 1.985756 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.985756 # IPC: Total IPC of All Threads +system.cpu.committedInsts 157988582 # Number of Instructions Simulated +system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated +system.cpu.cpi 0.886735 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.886735 # CPI: Total CPI of All Threads +system.cpu.ipc 1.127733 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.127733 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 554395898 # number of integer regfile reads system.cpu.int_regfile_writes 279799467 # number of integer regfile writes system.cpu.fp_regfile_reads 352 # number of floating regfile reads @@ -289,26 +294,39 @@ system.cpu.icache.total_refs 28212585 # To system.cpu.icache.sampled_refs 1024 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 27551.352539 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 822.534021 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.401628 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28212585 # number of ReadReq hits -system.cpu.icache.demand_hits 28212585 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28212585 # number of overall hits -system.cpu.icache.ReadReq_misses 1300 # number of ReadReq misses -system.cpu.icache.demand_misses 1300 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1300 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 46952500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 46952500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 46952500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28213885 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28213885 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28213885 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36117.307692 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36117.307692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36117.307692 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 822.534021 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.401628 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.401628 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 28212585 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 28212585 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 28212585 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 28212585 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 28212585 # number of overall hits +system.cpu.icache.overall_hits::total 28212585 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1300 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1300 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1300 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1300 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1300 # number of overall misses +system.cpu.icache.overall_misses::total 1300 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 46952500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 46952500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 46952500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 46952500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 46952500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 46952500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 28213885 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 28213885 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 28213885 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 28213885 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 28213885 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 28213885 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000046 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000046 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000046 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36117.307692 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36117.307692 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36117.307692 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -317,27 +335,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 275 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 275 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 275 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1025 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1025 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1025 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 36071500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 36071500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 36071500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35191.707317 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35191.707317 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35191.707317 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 275 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 275 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 275 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 275 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 275 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1025 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1025 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1025 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1025 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1025 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36071500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36071500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36071500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35191.707317 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35191.707317 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35191.707317 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2072906 # number of replacements system.cpu.dcache.tagsinuse 4073.029614 # Cycle average of tags in use @@ -345,32 +366,49 @@ system.cpu.dcache.total_refs 77489413 # To system.cpu.dcache.sampled_refs 2077002 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 37.308300 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 23588256000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4073.029614 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994392 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 46135653 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 31353751 # number of WriteReq hits -system.cpu.dcache.demand_hits 77489404 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 77489404 # number of overall hits -system.cpu.dcache.ReadReq_misses 2289012 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 86000 # number of WriteReq misses -system.cpu.dcache.demand_misses 2375012 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2375012 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 13766771000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 1501245288 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 15268016288 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 15268016288 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 48424665 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 79864416 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 79864416 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.047270 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.002735 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.029738 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.029738 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 6014.285203 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17456.340558 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 6428.605956 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 6428.605956 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4073.029614 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994392 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994392 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 46135653 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46135653 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31353751 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31353751 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 77489404 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77489404 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77489404 # number of overall hits +system.cpu.dcache.overall_hits::total 77489404 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2289012 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2289012 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 86000 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 86000 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2375012 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2375012 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2375012 # number of overall misses +system.cpu.dcache.overall_misses::total 2375012 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13766771000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13766771000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1501245288 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1501245288 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15268016288 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15268016288 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15268016288 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15268016288 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 48424665 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 48424665 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 79864416 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 79864416 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 79864416 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 79864416 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047270 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002735 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.029738 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.029738 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6014.285203 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17456.340558 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 6428.605956 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 6428.605956 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,32 +417,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1880780 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 294089 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 3918 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 298007 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 298007 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1994923 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 82082 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2077005 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2077005 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5565133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1157645788 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6722779288 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6722779288 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.041196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.026007 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.026007 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2789.648272 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14103.528033 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3236.766059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3236.766059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 1880780 # number of writebacks +system.cpu.dcache.writebacks::total 1880780 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 294089 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 294089 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3918 # 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mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2789.648272 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14103.528033 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3236.766059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3236.766059 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 33246 # number of replacements system.cpu.l2cache.tagsinuse 18964.988080 # Cycle average of tags in use @@ -412,39 +458,80 @@ system.cpu.l2cache.total_refs 3764517 # To system.cpu.l2cache.sampled_refs 61253 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 61.458492 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 6037.038666 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 12927.949414 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.184236 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.394530 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1964445 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1880780 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 52709 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2017154 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2017154 # number of overall hits -system.cpu.l2cache.ReadReq_misses 31361 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 1 # 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average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,34 +540,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 13942 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 31361 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 29513 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 59855 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 60874 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31643000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 941211000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 972854000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 914925500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 914925500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31643000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856136500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1887779500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31643000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856136500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1887779500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015211 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358943 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028818 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028818 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.993131 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.071188 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.762376 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.993131 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.550497 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.993131 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.550497 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini index 96706c5cc..15b801d93 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,34 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[7] +pio=system.membus.port[6] [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +97,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic +cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +121,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout index eb189c10a..a3234c831 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 06:52:52 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:18:06 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index e99e16cd0..e6ec29e4a 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.168950 # Nu sim_ticks 168950072000 # Number of ticks simulated final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2042288 # Simulator instruction rate (inst/s) -host_tick_rate 1240309006 # Simulator tick rate (ticks/s) -host_mem_usage 339312 # Number of bytes of host memory used -host_seconds 136.22 # Real time elapsed on the host -sim_insts 278192520 # Number of instructions simulated +host_inst_rate 1605694 # Simulator instruction rate (inst/s) +host_op_rate 2827368 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1717098424 # Simulator tick rate (ticks/s) +host_mem_usage 344660 # Number of bytes of host memory used +host_seconds 98.39 # Real time elapsed on the host +sim_insts 157988583 # Number of instructions simulated +sim_ops 278192520 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2458815679 # Number of bytes read from this memory system.physmem.bytes_inst_read 1741569664 # Number of instructions bytes read from this memory system.physmem.bytes_written 243173115 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 444 # Nu system.cpu.numCycles 337900145 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 278192520 # Number of instructions executed +system.cpu.committedInsts 157988583 # Number of instructions committed +system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index 008adeebb..426472e17 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +104,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +118,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +149,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +171,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing egid=100 env= errout=cerr @@ -191,7 +203,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index e89b51a20..064d05227 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 06:55:19 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:19:55 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 59ae818d2..a57ebe258 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.370011 # Nu sim_ticks 370010840000 # Number of ticks simulated final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1163147 # Simulator instruction rate (inst/s) -host_tick_rate 1547047043 # Simulator tick rate (ticks/s) -host_mem_usage 348152 # Number of bytes of host memory used -host_seconds 239.17 # Real time elapsed on the host -sim_insts 278192520 # Number of instructions simulated +host_inst_rate 912216 # Simulator instruction rate (inst/s) +host_op_rate 1606265 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2136418129 # Simulator tick rate (ticks/s) +host_mem_usage 353708 # Number of bytes of host memory used +host_seconds 173.19 # Real time elapsed on the host +sim_insts 157988583 # Number of instructions simulated +sim_ops 278192520 # Number of ops (including micro ops) simulated system.physmem.bytes_read 4900800 # Number of bytes read from this memory system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory system.physmem.bytes_written 1885440 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 444 # Nu system.cpu.numCycles 740021680 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 278192520 # Number of instructions executed +system.cpu.committedInsts 157988583 # Number of instructions committed +system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -47,26 +50,39 @@ system.cpu.icache.total_refs 217695401 # To system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits -system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits -system.cpu.icache.overall_hits 217695401 # number of overall hits -system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses -system.cpu.icache.demand_misses 808 # number of demand (read+write) misses -system.cpu.icache.overall_misses 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 666.191948 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325289 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325289 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 217695401 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 217695401 # number of overall hits +system.cpu.icache.overall_hits::total 217695401 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses +system.cpu.icache.overall_misses::total 808 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 45248000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 45248000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 45248000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 45248000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 45248000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 45248000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 217696209 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2062733 # number of replacements system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use @@ -102,32 +116,49 @@ system.cpu.dcache.total_refs 120152372 # To system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits -system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 120152372 # number of overall hits -system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses -system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 3268793000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.003375 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4076.661903 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 120152372 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 120152372 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 120152372 # number of overall hits +system.cpu.dcache.overall_hits::total 120152372 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses +system.cpu.dcache.overall_misses::total 2066829 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28849058000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28849058000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3268793000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3268793000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32117851000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32117851000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32117851000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32117851000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 122219201 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 122219201 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 122219201 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 122219201 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1437080 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.016911 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 1437080 # number of writebacks +system.cpu.dcache.writebacks::total 1437080 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22966898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22966898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2950464500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2950464500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25917362500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25917362500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25917362500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25917362500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11713.502183 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27805.977815 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 49212 # number of replacements system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use @@ -167,36 +200,72 @@ system.cpu.l2cache.total_refs 3296079 # To system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 63651 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1991062 # number of overall hits -system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 42458 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 76575 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1774084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1437080 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 12062.804989 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 196.794797 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6355.003474 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.368128 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.006006 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.193939 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.568073 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 1927411 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1927411 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1437080 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1437080 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 63651 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 63651 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 1991062 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1991062 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 1991062 # number of overall hits +system.cpu.l2cache.overall_hits::total 1991062 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 33309 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 34117 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 42458 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 42458 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 808 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 75767 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 76575 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 808 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 75767 # number of overall misses +system.cpu.l2cache.overall_misses::total 76575 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42016000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1732068000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1774084000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2207845500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2207845500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 42016000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3939913500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 3981929500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 42016000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3939913500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 3981929500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1437080 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1437080 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.016988 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.400136 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.036659 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.036659 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.694804 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,30 +274,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 29460 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 29460 # number of writebacks +system.cpu.l2cache.writebacks::total 29460 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33309 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 34117 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42458 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 42458 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 75767 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 76575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 75767 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 76575 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1332360000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1364680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1698320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1698320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3030680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3063000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3030680000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 3063000000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.016988 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.400136 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |