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-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini4
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt1144
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini4
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/simple-timing/simout6
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt180
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini4
-rwxr-xr-xtests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout6
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt194
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini4
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/o3-timing/simout9
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt1100
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini4
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-timing/simout6
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt182
15 files changed, 1427 insertions, 1426 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index 354c87304..a0763b2c7 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -497,7 +497,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -529,7 +529,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index e2beccd27..48d145b85 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:41:22
+gem5 compiled Jul 2 2012 09:08:16
+gem5 started Jul 2 2012 15:39:45
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 25878583500 because target called exit()
+Exiting @ tick 28553466500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 507566fcc..8d85ceff7 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,32 +1,32 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.025879 # Number of seconds simulated
-sim_ticks 25878583500 # Number of ticks simulated
-final_tick 25878583500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.028553 # Number of seconds simulated
+sim_ticks 28553466500 # Number of ticks simulated
+final_tick 28553466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 220420 # Simulator instruction rate (inst/s)
-host_op_rate 222002 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 62960153 # Simulator tick rate (ticks/s)
-host_mem_usage 367872 # Number of bytes of host memory used
-host_seconds 411.03 # Real time elapsed on the host
-sim_insts 90599358 # Number of instructions simulated
-sim_ops 91249911 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 45504 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory
-system.physmem.bytes_read::total 992960 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 45504 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 45504 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 711 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15515 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1758365 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 36611587 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 38369952 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1758365 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1758365 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1758365 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 36611587 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 38369952 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 181848 # Simulator instruction rate (inst/s)
+host_op_rate 183154 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 57311644 # Simulator tick rate (ticks/s)
+host_mem_usage 367800 # Number of bytes of host memory used
+host_seconds 498.21 # Real time elapsed on the host
+sim_insts 90599368 # Number of instructions simulated
+sim_ops 91249921 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 45312 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory
+system.physmem.bytes_read::total 992896 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 45312 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 45312 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 708 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1586918 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 33186303 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 34773221 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1586918 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1586918 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1586918 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 33186303 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 34773221 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -70,322 +70,322 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 51757168 # number of cpu cycles simulated
+system.cpu.numCycles 57106934 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 26984015 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 22232491 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 888214 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 11580024 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 11447482 # Number of BTB hits
+system.cpu.BPredUnit.lookups 27012699 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 22277532 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 889694 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 11653286 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 11426819 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 71474 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 416 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 14414928 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 129560918 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 26984015 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11518956 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 24378433 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4928329 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 8911472 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 72452 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 358 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 14542606 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 129803697 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 27012699 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 11499271 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 24399920 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5015488 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 14039908 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 24 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 14076190 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 379999 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 51715551 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.525564 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.245999 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 14144138 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 347071 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 57042317 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.294103 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.179417 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 27375149 52.93% 52.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3448740 6.67% 59.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2025913 3.92% 63.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1592010 3.08% 66.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1693129 3.27% 69.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2969374 5.74% 75.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1533811 2.97% 78.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1107315 2.14% 80.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9970110 19.28% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 32680363 57.29% 57.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3435885 6.02% 63.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2022812 3.55% 66.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1588688 2.79% 69.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1698003 2.98% 72.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 3014546 5.28% 77.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1479172 2.59% 80.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1109191 1.94% 82.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 10013657 17.55% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 51715551 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.521358 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.503246 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 17151536 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 6845661 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 22836822 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 879705 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 4001827 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4473928 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 9005 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 127743952 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 42919 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 4001827 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18918146 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2041479 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 194552 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21908799 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4650748 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 124387508 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 285864 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 3910791 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 369 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 145115578 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 541729246 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 541723014 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 6232 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 37686096 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 18180 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 18178 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 11273342 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29662115 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5564551 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2120620 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1233720 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 118944023 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 22020 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 105456921 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 87203 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 27512358 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 68343356 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 11890 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 51715551 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.039172 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.917652 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 57042317 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.473020 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.272994 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 17762369 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 11471319 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 22339470 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1418238 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4050921 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4486769 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 9087 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 127953392 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 42856 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4050921 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 19506799 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 5508085 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 206847 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 21544530 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6225135 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 124612804 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1000 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 540301 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4835980 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 10850 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 145164650 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 542855215 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 542847680 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 7535 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 107429498 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 37735152 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 18216 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 18214 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 14341922 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29837938 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 5556896 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2142306 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1236219 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 119143027 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 22051 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 105690693 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 78779 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 27699280 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 68606056 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 11919 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 57042317 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.852847 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.854849 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 13904878 26.89% 26.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 11456546 22.15% 49.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7969137 15.41% 64.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6724396 13.00% 77.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 5314058 10.28% 87.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2865211 5.54% 93.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2534987 4.90% 98.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 474000 0.92% 99.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 472338 0.91% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 17381718 30.47% 30.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13049544 22.88% 53.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 8518143 14.93% 68.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6991208 12.26% 80.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 5292177 9.28% 89.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2744999 4.81% 94.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2144277 3.76% 98.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 490134 0.86% 99.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 430117 0.75% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 51715551 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 57042317 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 33403 5.02% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 27 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 354808 53.31% 58.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 277311 41.67% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 40944 6.13% 6.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 27 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 349072 52.27% 58.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 277751 41.59% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 74629419 70.77% 70.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10524 0.01% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 188 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 232 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25677872 24.35% 95.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5138682 4.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 74708862 70.69% 70.69% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 10518 0.01% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 221 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 275 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 25829491 24.44% 95.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 5141321 4.86% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 105456921 # Type of FU issued
-system.cpu.iq.rate 2.037533 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 665549 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006311 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 263381228 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 146480266 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 102833498 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 917 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1333 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 399 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 106122017 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 453 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 424644 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 105690693 # Type of FU issued
+system.cpu.iq.rate 1.850751 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 667794 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006318 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 269169203 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 146866507 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 102954305 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1073 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1626 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 453 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 106357959 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 528 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 425504 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 7086237 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 8981 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 4129 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 817795 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 7262058 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7178 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 4608 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 810138 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 39333 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 165527 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 4001827 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 198669 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 33921 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 119002430 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 339181 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29662115 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5564551 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 18117 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 13618 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1230 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 4129 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 473445 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 489320 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 962765 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 104433557 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25350982 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1023364 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4050921 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 893670 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 117044 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 119201460 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 342636 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 29837938 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 5556896 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 18147 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 49262 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 15777 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 4608 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 477903 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 486113 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 964016 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 104633146 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25499061 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1057547 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 36387 # number of nop insts executed
-system.cpu.iew.exec_refs 30425523 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21334984 # Number of branches executed
-system.cpu.iew.exec_stores 5074541 # Number of stores executed
-system.cpu.iew.exec_rate 2.017760 # Inst execution rate
-system.cpu.iew.wb_sent 103141450 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 102833897 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 62142858 # num instructions producing a value
-system.cpu.iew.wb_consumers 103855994 # num instructions consuming a value
+system.cpu.iew.exec_nop 36382 # number of nop insts executed
+system.cpu.iew.exec_refs 30575453 # number of memory reference insts executed
+system.cpu.iew.exec_branches 21352915 # Number of branches executed
+system.cpu.iew.exec_stores 5076392 # Number of stores executed
+system.cpu.iew.exec_rate 1.832232 # Inst execution rate
+system.cpu.iew.wb_sent 103240911 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 102954758 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 61949538 # num instructions producing a value
+system.cpu.iew.wb_consumers 102898807 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.986853 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.598356 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.802842 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.602043 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 90611967 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 91262520 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 27741223 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 891236 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 47713725 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.912710 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.511102 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 90611977 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 91262530 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 27941572 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 10132 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 892650 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 52991397 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.722214 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.475842 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 17393373 36.45% 36.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13510296 28.32% 64.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4501215 9.43% 74.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3866271 8.10% 82.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1517173 3.18% 85.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 785983 1.65% 87.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 854820 1.79% 88.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 253298 0.53% 89.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5031296 10.54% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 23013346 43.43% 43.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13498664 25.47% 68.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4267920 8.05% 76.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 3605539 6.80% 83.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1555941 2.94% 86.70% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::6 916105 1.73% 89.76% # Number of insts commited each cycle
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@@ -394,246 +394,246 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.l2cache.overall_miss_latency::total 533119000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 737 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 903336 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 904073 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 942950 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 942950 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 44347 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 44347 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 737 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 947683 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 948420 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 737 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 947683 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 948420 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.966079 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25363000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10310000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 35673000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 499681500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 499681500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 25363000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 509991500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 535354500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 25363000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 509991500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 535354500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 734 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 912369 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 913103 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 942869 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 942869 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 35239 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 35239 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 734 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 947608 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 948342 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 734 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 947608 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 948342 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967302 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000308 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.001095 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.327779 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.327779 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966079 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.015632 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.016370 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966079 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.015632 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.016370 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34275.983146 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34244.604317 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34267.171717 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34341.944139 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34341.944139 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34275.983146 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34340.117456 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34337.176349 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34275.983146 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34340.117456 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34337.176349 # average overall miss latency
+system.cpu.l2cache.ReadReq_miss_rate::total 0.001085 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.412469 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.412469 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967302 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.015635 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.016372 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967302 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.015635 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.016372 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35722.535211 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36690.391459 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35996.972755 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34377.812178 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34377.812178 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35722.535211 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34421.672516 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34481.160634 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35722.535211 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34421.672516 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34481.160634 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -642,59 +642,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 711 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 268 # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::total 12 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 708 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 979 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14536 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 14536 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 711 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 14804 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 15515 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 711 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 14804 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 15515 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22107000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8364000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 30471000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 452118500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 452118500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22107000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 460482500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 482589500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22107000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 460482500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 482589500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14535 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 14535 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 708 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 14806 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 15514 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 708 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 14806 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 15514 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23086000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9134000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32220000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 453439000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 453439000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23086000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462573000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 485659000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23086000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462573000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 485659000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964578 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000297 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001083 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.327779 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.327779 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001072 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412469 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412469 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964578 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964578 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31092.827004 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31208.955224 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31124.616956 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31103.364062 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31103.364062 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31092.827004 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31105.275601 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31104.705124 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31092.827004 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31105.275601 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31104.705124 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32607.344633 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33704.797048 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32911.133810 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31196.353629 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31196.353629 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32607.344633 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31242.266649 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31304.563620 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32607.344633 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31242.266649 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31304.563620 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
index 8e4e9dec7..172c79802 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -166,7 +166,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -198,7 +198,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
index 78b502a64..092850ece 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:44:41
+gem5 compiled Jul 2 2012 09:08:16
+gem5 started Jul 2 2012 15:40:44
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 148083373000 because target called exit()
+Exiting @ tick 148267705000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 63806d746..4b16c09c3 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.148083 # Number of seconds simulated
-sim_ticks 148083373000 # Number of ticks simulated
-final_tick 148083373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.148268 # Number of seconds simulated
+sim_ticks 148267705000 # Number of ticks simulated
+final_tick 148267705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1433979 # Simulator instruction rate (inst/s)
-host_op_rate 1444261 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2344399916 # Simulator tick rate (ticks/s)
-host_mem_usage 365828 # Number of bytes of host memory used
-host_seconds 63.16 # Real time elapsed on the host
+host_inst_rate 1021914 # Simulator instruction rate (inst/s)
+host_op_rate 1029241 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1672798092 # Simulator tick rate (ticks/s)
+host_mem_usage 365748 # Number of bytes of host memory used
+host_seconds 88.63 # Real time elapsed on the host
sim_insts 90576861 # Number of instructions simulated
sim_ops 91226312 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 36992 # Nu
system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 249805 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 6379974 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6629779 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 249805 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 249805 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 249805 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 6379974 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6629779 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 249495 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 6372042 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 6621536 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 249495 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 249495 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 249495 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 6372042 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6621536 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 296166746 # number of cpu cycles simulated
+system.cpu.numCycles 296535410 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90576861 # Number of instructions committed
@@ -89,18 +89,18 @@ system.cpu.num_mem_refs 27318810 # nu
system.cpu.num_load_insts 22573966 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 296166746 # Number of busy cycles
+system.cpu.num_busy_cycles 296535410 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 2 # number of replacements
-system.cpu.icache.tagsinuse 510.334547 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 510.369252 # Cycle average of tags in use
system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.334547 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.249187 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.249187 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 510.369252 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.249204 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.249204 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits
@@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n
system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
system.cpu.icache.overall_misses::total 599 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 32662000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 32662000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 32662000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 32662000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 32662000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 32662000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 32709000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 32709000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 32709000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 32709000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 32709000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 32709000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses
@@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006
system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54527.545910 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54527.545910 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54527.545910 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54606.010017 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 54606.010017 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54606.010017 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 54606.010017 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54606.010017 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 54606.010017 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -151,34 +151,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599
system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30912000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 30912000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30912000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 30912000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30912000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 30912000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51606.010017 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51606.010017 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51606.010017 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 51606.010017 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51606.010017 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 51606.010017 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 942702 # number of replacements
-system.cpu.dcache.tagsinuse 3568.539568 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 3568.972050 # Cycle average of tags in use
system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 54479146000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3568.539568 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.871225 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.871225 # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle 54491057000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3568.972050 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.871331 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.871331 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
@@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data 946798 # n
system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
system.cpu.dcache.overall_misses::total 946798 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 12611634000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 12611634000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1263542000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1263542000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 13875176000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 13875176000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 13875176000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 13875176000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 12648933000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 12648933000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1288595000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1288595000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 13937528000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 13937528000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 13937528000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 13937528000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
@@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034701
system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.984570 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.984570 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 27109.399472 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.842955 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14654.842955 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.842955 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14654.842955 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14051.419202 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14051.419202 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27646.913686 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 27646.913686 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14720.698607 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14720.698607 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14720.698607 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14720.698607 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946798
system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9948366000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9948366000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148768000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148768000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11097134000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 11097134000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11097134000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 11097134000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
@@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701
system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11051.419202 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11051.419202 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24646.913686 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24646.913686 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11720.698607 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11720.698607 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11720.698607 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11720.698607 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 9598.880462 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 9602.986186 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1827210 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 119.246231 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 8910.241595 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 495.387120 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 193.251747 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.271919 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.015118 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 8914.312589 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 495.421771 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 193.251826 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.272043 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.015119 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.005898 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.292935 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.293060 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index 8e6bba913..2ba8ced6e 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -180,7 +180,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.physmem.port[0]
slave=system.system_port system.cpu.l2cache.mem_side
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
index 8432da315..f34d81d26 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 28 2012 22:06:58
-gem5 started Jun 28 2012 22:55:42
+gem5 compiled Jul 2 2012 08:54:18
+gem5 started Jul 2 2012 12:31:43
gem5 executing on zizzer
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 362428997000 because target called exit()
+Exiting @ tick 362481577000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 75faf8d15..5f77178bc 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.362429 # Number of seconds simulated
-sim_ticks 362428997000 # Number of ticks simulated
-final_tick 362428997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.362482 # Number of seconds simulated
+sim_ticks 362481577000 # Number of ticks simulated
+final_tick 362481577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1801112 # Simulator instruction rate (inst/s)
-host_op_rate 1801186 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2677225778 # Simulator tick rate (ticks/s)
-host_mem_usage 354292 # Number of bytes of host memory used
-host_seconds 135.37 # Real time elapsed on the host
+host_inst_rate 1217197 # Simulator instruction rate (inst/s)
+host_op_rate 1217247 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1809539933 # Simulator tick rate (ticks/s)
+host_mem_usage 354248 # Number of bytes of host memory used
+host_seconds 200.32 # Real time elapsed on the host
sim_insts 243825163 # Number of instructions simulated
sim_ops 243835278 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
@@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 56256 # Nu
system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2600057 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2755276 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2600057 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2755276 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 155197 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2599680 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2754877 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 155197 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 155197 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 155197 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2599680 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2754877 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 443 # Number of system calls
-system.cpu.numCycles 724857994 # number of cpu cycles simulated
+system.cpu.numCycles 724963154 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 243825163 # Number of instructions committed
@@ -47,18 +47,18 @@ system.cpu.num_mem_refs 105711442 # nu
system.cpu.num_load_insts 82803522 # Number of load instructions
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 724857994 # Number of busy cycles
+system.cpu.num_busy_cycles 724963154 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 25 # number of replacements
-system.cpu.icache.tagsinuse 725.567220 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 725.564686 # Cycle average of tags in use
system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 725.567220 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 725.564686 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.354280 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.354280 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits
@@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n
system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
system.cpu.icache.overall_misses::total 882 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 49266000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 49266000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 49266000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 49266000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 49266000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 49266000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 49333000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 49333000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 49333000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 49333000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 49333000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 49333000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses
@@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55857.142857 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55857.142857 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55933.106576 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55933.106576 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55933.106576 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55933.106576 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55933.106576 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55933.106576 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -109,34 +109,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 882
system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46687000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 46687000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46687000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 46687000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46687000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 46687000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52933.106576 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52933.106576 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 935475 # number of replacements
-system.cpu.dcache.tagsinuse 3563.821484 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 3563.804804 # Cycle average of tags in use
system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3563.821484 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle 134384281000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3563.804804 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.870070 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.870070 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
@@ -157,16 +157,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 12506592000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 12506592000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 13772304000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 13772304000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 13772304000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 13772304000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 12510586000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 12510586000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1267548000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1267548000 # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 13778134000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 13778134000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 13778134000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 13778134000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
@@ -187,16 +187,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.385281 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.385281 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14658.139334 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14658.139334 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14011.858562 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14011.858562 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27136.544637 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 27136.544637 # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14664.344320 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14664.344320 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14664.344320 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14664.344320 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -217,16 +217,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9832015000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9832015000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1127418000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1127418000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 89000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total 89000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10959433000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10959433000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10959433000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10959433000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
@@ -237,30 +237,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11011.858562 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11011.858562 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24136.544637 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24136.544637 # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22250 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22250 # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 9744.405217 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 9744.633089 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 8861.272475 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 738.802087 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 144.330654 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.270425 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 8861.504688 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 738.799807 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 144.328594 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.270432 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.022546 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.004405 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.297376 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.297383 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index 4ff330a09..02825e2f4 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -500,7 +500,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -532,7 +532,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index ec0229a1c..dec2c9148 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 28 2012 22:08:09
-gem5 started Jun 28 2012 23:13:04
+gem5 compiled Jul 2 2012 08:58:39
+gem5 started Jul 2 2012 13:12:36
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@@ -21,7 +21,8 @@ new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
flow value : 3080014995
-info: Increasing stack size by one page.
checksum : 68389
optimal
-Exiting @ tick 66545720000 because target called exit()
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+Exiting @ tick 68340167000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 1baa4dbca..4e7a26f12 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,279 +1,279 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.066546 # Number of seconds simulated
-sim_ticks 66545720000 # Number of ticks simulated
-final_tick 66545720000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.068340 # Number of seconds simulated
+sim_ticks 68340167000 # Number of ticks simulated
+final_tick 68340167000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 128459 # Simulator instruction rate (inst/s)
-host_op_rate 226196 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 54107733 # Simulator tick rate (ticks/s)
-host_mem_usage 365700 # Number of bytes of host memory used
-host_seconds 1229.87 # Real time elapsed on the host
+host_inst_rate 107513 # Simulator instruction rate (inst/s)
+host_op_rate 189313 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 46506224 # Simulator tick rate (ticks/s)
+host_mem_usage 365660 # Number of bytes of host memory used
+host_seconds 1469.48 # Real time elapsed on the host
sim_insts 157988582 # Number of instructions simulated
sim_ops 278192519 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1892992 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1961344 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 68352 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 68352 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 20032 # Number of bytes written to this memory
-system.physmem.bytes_written::total 20032 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1068 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 29578 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 30646 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 313 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 313 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1027143 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 28446488 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 29473631 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1027143 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1027143 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 301026 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 301026 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 301026 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1027143 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 28446488 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 29774657 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 68608 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1893120 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1961728 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 68608 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 68608 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 20288 # Number of bytes written to this memory
+system.physmem.bytes_written::total 20288 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 1072 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 29580 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 30652 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 317 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 317 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1003919 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 27701425 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 28705344 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1003919 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1003919 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 296868 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 296868 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 296868 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1003919 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 27701425 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 29002212 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 133091441 # number of cpu cycles simulated
+system.cpu.numCycles 136680335 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 36127369 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 36127369 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1087558 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 25661122 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 25550646 # Number of BTB hits
+system.cpu.BPredUnit.lookups 36129289 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 36129289 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1086629 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 25668657 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 25566381 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 27995643 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 196446977 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 36127369 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 25550646 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 59425857 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 8408654 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 38346383 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 123 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 27275955 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 142407 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 133058866 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.595223 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.362713 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 28038648 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 196448149 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 36129289 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 25566381 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 59446336 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 8437809 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 41835148 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 182 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 27320717 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 151811 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 136641889 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.527241 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.343736 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 76373838 57.40% 57.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2167538 1.63% 59.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2997061 2.25% 61.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 4104688 3.08% 64.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8024100 6.03% 70.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 5043618 3.79% 74.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2895035 2.18% 76.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1466845 1.10% 77.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 29986143 22.54% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 79944033 58.51% 58.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2167208 1.59% 60.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2997757 2.19% 62.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 4111297 3.01% 65.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8027988 5.88% 71.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 5053640 3.70% 74.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2897429 2.12% 76.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1474644 1.08% 78.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 29967893 21.93% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 133058866 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.271448 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.476030 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 40459991 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 29238616 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 46513629 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9555795 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 7290835 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 341218691 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 7290835 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 45832356 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 4342736 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 9009 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 50371616 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 25212314 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 337359064 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 3751 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 23039182 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 70135 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 414697998 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1009810700 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1009808348 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2352 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 136641889 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.264334 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.437282 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 40756149 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 32464330 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 46271327 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 9828540 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 7321543 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 341364323 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 7321543 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 46061495 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 6368629 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 8995 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 50367831 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 26513396 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 337564097 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5026 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 24245573 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 73928 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 414895608 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1010438546 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1010435932 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2614 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 341010940 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 73687058 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 73884668 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 483 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 55957632 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 108146065 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 37162932 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 46284047 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 7887005 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 331670931 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2660 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 311367761 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 187011 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 53218475 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 92468498 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 133058866 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.340075 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.723307 # Number of insts issued each cycle
+system.cpu.rename.tempSerializingInsts 475 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 57387793 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 108215751 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 37227533 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 46388866 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 7855106 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 331925513 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2461 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 311467723 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 186069 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 53480941 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 93052835 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 2015 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 136641889 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.279445 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.722907 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 27262165 20.49% 20.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 17087897 12.84% 33.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 25427949 19.11% 52.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 31141299 23.40% 75.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 17714013 13.31% 89.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 9070422 6.82% 95.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 3766330 2.83% 98.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1516401 1.14% 99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 72390 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 29493706 21.58% 21.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 18268502 13.37% 34.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 26067174 19.08% 54.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 31248056 22.87% 76.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 17426975 12.75% 89.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 8824728 6.46% 96.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 3769643 2.76% 98.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1473533 1.08% 99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 69572 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 133058866 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 136641889 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 23137 1.10% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1959411 92.81% 93.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 128735 6.10% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 22788 1.09% 1.09% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1944579 92.77% 93.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 128653 6.14% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 31371 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 177167866 56.90% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 103 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 99703270 32.02% 88.93% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 34465151 11.07% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 29247 0.01% 0.01% # Type of FU issued
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+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.92% # Type of FU issued
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+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 99693088 32.01% 88.93% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 34487693 11.07% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 311367761 # Type of FU issued
-system.cpu.iq.rate 2.339503 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2111283 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006781 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 758091805 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 384922588 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 308230879 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 877 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1235 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 288 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 313447268 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 405 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 52556752 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 311467723 # Type of FU issued
+system.cpu.iq.rate 2.278804 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2096020 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006729 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 761858485 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 385440526 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 308377955 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 939 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1362 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 296 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 313534078 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 418 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 52563213 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 17366677 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 97430 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 32398 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 5723181 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 17436363 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 94862 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 33518 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 5787782 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 3328 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 3855 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3294 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 766 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 7290835 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 316808 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 29284 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 331673591 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 45940 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 108146065 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 37162932 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 478 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 230 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 5075 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 32398 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 615271 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 578255 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1193526 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 309404440 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 99168969 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1963321 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 7321543 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 823106 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 106434 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 331927974 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 49382 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 108215751 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 37227533 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1169 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 29139 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 33518 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 614396 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 578149 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1192545 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 309546199 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 99164124 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1921524 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 133248637 # number of memory reference insts executed
-system.cpu.iew.exec_branches 31530009 # Number of branches executed
-system.cpu.iew.exec_stores 34079668 # Number of stores executed
-system.cpu.iew.exec_rate 2.324751 # Inst execution rate
-system.cpu.iew.wb_sent 308773966 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 308231167 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 227547609 # num instructions producing a value
-system.cpu.iew.wb_consumers 467201547 # num instructions consuming a value
+system.cpu.iew.exec_refs 133270548 # number of memory reference insts executed
+system.cpu.iew.exec_branches 31554842 # Number of branches executed
+system.cpu.iew.exec_stores 34106424 # Number of stores executed
+system.cpu.iew.exec_rate 2.264746 # Inst execution rate
+system.cpu.iew.wb_sent 308908711 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 308378251 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 227159905 # num instructions producing a value
+system.cpu.iew.wb_consumers 466461304 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.315935 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.487044 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.256201 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.486986 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions
system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 53483171 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 53739498 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1087573 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 125768031 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.211949 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.676987 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1086653 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 129320346 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.151189 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.664667 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 45423361 36.12% 36.12% # Number of insts commited each cycle
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system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -284,69 +284,69 @@ system.cpu.commit.branches 29309710 # Nu
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
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system.cpu.committedInsts 157988582 # Number of Instructions Simulated
system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated
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-system.cpu.cpi_total 0.842412 # CPI: Total CPI of All Threads
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@@ -355,94 +355,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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@@ -451,140 +451,140 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.l2cache.Writeback_accesses::total 2064802 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 82133 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 82133 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1079 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 2076192 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2077271 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2076249 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2077328 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1079 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 2076192 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2077271 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.989805 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000293 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.000829 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.800000 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.800000 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352782 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.352782 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.989805 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.014246 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.014753 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.989805 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.014246 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.014753 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.322097 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34218.803419 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34250.151240 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34084.158245 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34084.158245 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.322097 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34086.821286 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34093.111662 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.322097 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34086.821286 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34093.111662 # average overall miss latency
+system.cpu.l2cache.overall_accesses::cpu.data 2076249 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2077328 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993513 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000295 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.000832 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.666667 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.666667 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352988 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.352988 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993513 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.014247 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.014755 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993513 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.014247 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.014755 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35626.399254 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35507.653061 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35584.337349 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34123.223648 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34123.223648 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35626.399254 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34150.743746 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34202.352212 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35626.399254 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34150.743746 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34202.352212 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -593,60 +593,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 313 # number of writebacks
-system.cpu.l2cache.writebacks::total 313 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1068 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 585 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1653 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 4 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28993 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 28993 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 1068 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 29578 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 30646 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 29578 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 30646 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33172000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18151500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51323500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 124000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 124000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 898797500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 898797500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33172000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 916949000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 950121000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33172000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 916949000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 950121000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.989805 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000293 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000829 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800000 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352782 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352782 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.989805 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014246 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.014753 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.989805 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014246 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.014753 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31059.925094 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31028.205128 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31048.699335 # average ReadReq mshr miss latency
+system.cpu.l2cache.writebacks::writebacks 317 # number of writebacks
+system.cpu.l2cache.writebacks::total 317 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1072 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 588 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1660 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28992 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 28992 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1072 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 29580 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 30652 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 1072 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 29580 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34797000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19023000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53820000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 62000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 62000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899044500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899044500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34797000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918067500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 952864500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34797000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918067500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 952864500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993513 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000832 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.666667 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.666667 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352988 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352988 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993513 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.014755 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993513 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32459.888060 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32352.040816 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32421.686747 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.500121 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.500121 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31059.925094 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.048076 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31003.099915 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31059.925094 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.048076 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31003.099915 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.088990 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.088990 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32459.888060 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31036.764706 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31086.535952 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32459.888060 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31036.764706 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31086.535952 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index 4b59eaf01..44c2b2c0a 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -169,7 +169,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -201,7 +201,7 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
+width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index 894e40d36..85144f91b 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 28 2012 22:08:09
-gem5 started Jun 28 2012 23:17:22
+gem5 compiled Jul 2 2012 08:58:39
+gem5 started Jul 2 2012 13:28:56
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 368062166000 because target called exit()
+Exiting @ tick 368209254000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index 896f57262..cca34d6d0 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.368062 # Number of seconds simulated
-sim_ticks 368062166000 # Number of ticks simulated
-final_tick 368062166000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.368209 # Number of seconds simulated
+sim_ticks 368209254000 # Number of ticks simulated
+final_tick 368209254000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 915530 # Simulator instruction rate (inst/s)
-host_op_rate 1612102 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2132888263 # Simulator tick rate (ticks/s)
-host_mem_usage 362628 # Number of bytes of host memory used
-host_seconds 172.57 # Real time elapsed on the host
+host_inst_rate 606195 # Simulator instruction rate (inst/s)
+host_op_rate 1067413 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1412802854 # Simulator tick rate (ticks/s)
+host_mem_usage 363612 # Number of bytes of host memory used
+host_seconds 260.62 # Real time elapsed on the host
sim_insts 157988583 # Number of instructions simulated
sim_ops 278192520 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory
@@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data 29370 # Nu
system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory
system.physmem.num_writes::total 227 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 140498 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 5106963 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 5247461 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 140498 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 140498 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 39472 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 39472 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 39472 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 140498 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5106963 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 5286933 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 140442 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 5104923 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 5245365 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 140442 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 140442 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 39456 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 39456 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 39456 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 140442 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 5104923 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 5284821 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 736124332 # number of cpu cycles simulated
+system.cpu.numCycles 736418508 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988583 # Number of instructions committed
@@ -54,16 +54,16 @@ system.cpu.num_mem_refs 122219139 # nu
system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_store_insts 31439751 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 736124332 # Number of busy cycles
+system.cpu.num_busy_cycles 736418508 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements
-system.cpu.icache.tagsinuse 665.896557 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 665.897663 # Cycle average of tags in use
system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 665.896557 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 665.897663 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.325145 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.325145 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits
@@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
system.cpu.icache.overall_misses::total 808 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 45248000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 45248000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 45248000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 45248000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 45248000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 45248000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 45336000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 45336000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 45336000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 45336000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 45336000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 45336000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses
@@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56108.910891 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56108.910891 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56108.910891 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56108.910891 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56108.910891 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56108.910891 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42912000 # number of ReadReq MSHR miss cycles
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+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42912000 # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42912000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 42912000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53108.910891 # average ReadReq mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53108.910891 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53108.910891 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2062733 # number of replacements
-system.cpu.dcache.tagsinuse 4076.559519 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4076.463091 # Cycle average of tags in use
system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4076.559519 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.995254 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.995254 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
@@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 27464486000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 27464486000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 2704691000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 2704691000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 30169177000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 30169177000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 30169177000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 30169177000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 27487330000 # number of ReadReq miss cycles
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+system.cpu.dcache.WriteReq_miss_latency::cpu.data 2708348000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 2708348000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 30195678000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 30195678000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 30195678000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 30195678000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
@@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.347301 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.347301 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25489.741681 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 25489.741681 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14596.842313 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14596.842313 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14596.842313 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14596.842313 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14018.998123 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14018.998123 # average ReadReq miss latency
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+system.cpu.dcache.WriteReq_avg_miss_latency::total 25524.206241 # average WriteReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 14609.664370 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14609.664370 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14609.664370 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386362500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
@@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1081 # number of replacements
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system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.ReadReq_hits::cpu.data 1960377 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1960377 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2061794 # number of Writeback hits