diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt | 564 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1486 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt | 344 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt | 1508 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt | 464 |
5 files changed, 2196 insertions, 2170 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index ef2534218..2d36751f4 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.062409 # Number of seconds simulated -sim_ticks 62408957500 # Number of ticks simulated -final_tick 62408957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.062421 # Number of seconds simulated +sim_ticks 62420912500 # Number of ticks simulated +final_tick 62420912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176281 # Simulator instruction rate (inst/s) -host_op_rate 177159 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 121425676 # Simulator tick rate (ticks/s) -host_mem_usage 399932 # Number of bytes of host memory used -host_seconds 513.97 # Real time elapsed on the host +host_inst_rate 255603 # Simulator instruction rate (inst/s) +host_op_rate 256876 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 176097831 # Simulator tick rate (ticks/s) +host_mem_usage 405340 # Number of bytes of host memory used +host_seconds 354.47 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory system.physmem.bytes_read::total 996736 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 49472 # Nu system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 792707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15178334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15971041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 792707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 792707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 792707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15178334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15971041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 792555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15175427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15967982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 792555 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 792555 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 792555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15175427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15967982 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 62408863500 # Total gap between requests +system.physmem.totGap 62420817500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 15459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 642.437702 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 437.017774 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 401.182344 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 251 16.20% 16.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 185 11.94% 28.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 90 5.81% 33.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 67 4.33% 38.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 77 4.97% 43.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 93 6.00% 49.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 42 2.71% 51.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 43 2.78% 54.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 701 45.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation -system.physmem.totQLat 75120250 # Total ticks spent queuing -system.physmem.totMemAccLat 367132750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 645.984416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 440.038624 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 401.127365 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 251 16.30% 16.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 179 11.62% 27.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 84 5.45% 33.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 75 4.87% 38.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 76 4.94% 43.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 73 4.74% 47.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 57 3.70% 51.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 48 3.12% 54.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 697 45.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation +system.physmem.totQLat 72080000 # Total ticks spent queuing +system.physmem.totMemAccLat 364092500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4823.44 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4628.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23573.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23378.23 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.97 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.97 # Average system read bandwidth in MiByte/s @@ -217,48 +217,48 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14020 # Number of row buffer hits during reads +system.physmem.readRowHits 14024 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4007246.92 # Average gap between requests -system.physmem.pageHitRate 90.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6395760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3489750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4008014.48 # Average gap between requests +system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6335280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3456750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63648000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2565881505 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 35193459000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41909107215 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.544396 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 58537353750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2083900000 # Time in different power states +system.physmem_0.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2557911195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 35205114000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41913082185 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.524455 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 58558754750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2084160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1785901250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1773814250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5292000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2887500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2571480045 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 35188548000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41901860400 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.428274 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 58529558500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2083900000 # Time in different power states +system.physmem_1.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2600892900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 35167410750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41910562710 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.484088 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 58497118250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2084160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1793609000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1836331750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 20808236 # Number of BP lookups -system.cpu.branchPred.condPredicted 17115622 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 20808241 # Number of BP lookups +system.cpu.branchPred.condPredicted 17115627 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8965652 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8840815 # Number of BTB hits +system.cpu.branchPred.BTBLookups 8965661 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8840824 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.607608 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 98.607610 # BTB Hit Percentage system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. @@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 24795 # Nu system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 62408957500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 124817915 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 124841825 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2182474 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2182225 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.377638 # CPI: cycles per instruction -system.cpu.ipc 0.725880 # IPC: instructions per cycle +system.cpu.cpi 1.377902 # CPI: cycles per instruction +system.cpu.ipc 0.725741 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction @@ -432,60 +432,60 @@ system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91054081 # Class of committed instruction -system.cpu.tickCycles 110516717 # Number of cycles that the object actually ticked -system.cpu.idleCycles 14301198 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 110516273 # Number of cycles that the object actually ticked +system.cpu.idleCycles 14325552 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 946101 # number of replacements -system.cpu.dcache.tags.tagsinuse 3621.431844 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26274920 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3621.404220 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26274921 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.652076 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20702462500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3621.431844 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.884139 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.884139 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 27.652077 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20706654500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3621.404220 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.884132 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.884132 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2203 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1651 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2205 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1649 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55461267 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55461267 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21605941 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21605941 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660697 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660697 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55461265 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55461265 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21605938 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21605938 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660701 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660701 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26266638 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26266638 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26267146 # number of overall hits -system.cpu.dcache.overall_hits::total 26267146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906327 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74284 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74284 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 26266639 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26266639 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26267147 # number of overall hits +system.cpu.dcache.overall_hits::total 26267147 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906329 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906329 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74280 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74280 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 980611 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 980611 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 980615 # number of overall misses -system.cpu.dcache.overall_misses::total 980615 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11805097500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11805097500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2540928500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2540928500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14346026000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14346026000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14346026000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14346026000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22512268 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22512268 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 980609 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 980609 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 980613 # number of overall misses +system.cpu.dcache.overall_misses::total 980613 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11804222500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11804222500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566012000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2566012000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14370234500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14370234500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14370234500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14370234500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22512267 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22512267 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) @@ -494,28 +494,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27247249 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27247249 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27247761 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27247761 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27247248 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27247248 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27247760 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27247760 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015688 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015688 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015687 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015687 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.035989 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.035989 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.207789 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.207789 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34205.596091 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34205.596091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14629.680883 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14629.680883 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14629.621207 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14629.621207 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13024.213613 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13024.213613 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34545.126548 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34545.126548 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.397930 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14654.397930 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.338154 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14654.338154 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -524,14 +524,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks system.cpu.dcache.writebacks::total 943282 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2897 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2897 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27520 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27520 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 30417 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 30417 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 30417 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 30417 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2899 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27516 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27516 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 30415 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 30415 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 30415 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 30415 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses @@ -542,16 +542,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950194 system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10863020500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10863020500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1482579500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1482579500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345600000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12345600000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12345756000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12345756000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862380000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862380000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1495373500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1495373500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 158000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 158000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12357753500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12357753500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12357911500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12357911500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -562,71 +562,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12024.197226 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12024.197226 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31703.436404 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31703.436404 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.715172 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.715172 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.838327 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.838327 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.488261 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.488261 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31977.022924 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31977.022924 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13005.505718 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13005.505718 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13005.630938 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13005.630938 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 689.591924 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27835291 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 689.589449 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27835051 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34750.675406 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34750.375780 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 689.591924 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.336715 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.336715 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 689.589449 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.336714 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.336714 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55672985 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55672985 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 27835291 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27835291 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27835291 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27835291 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27835291 # number of overall hits -system.cpu.icache.overall_hits::total 27835291 # number of overall hits +system.cpu.icache.tags.tag_accesses 55672505 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55672505 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 27835051 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27835051 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27835051 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27835051 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27835051 # number of overall hits +system.cpu.icache.overall_hits::total 27835051 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses system.cpu.icache.overall_misses::total 801 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60446000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60446000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60446000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60446000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60446000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60446000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27836092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27836092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27836092 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27836092 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27836092 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27836092 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60780500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60780500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60780500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60780500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60780500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60780500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27835852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27835852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27835852 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27835852 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27835852 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27835852 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75463.171036 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75463.171036 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75463.171036 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75463.171036 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75880.774032 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75880.774032 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75880.774032 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75880.774032 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,48 +641,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 801 system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59645000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59645000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59645000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59645000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59645000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59645000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59979500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59979500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59979500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59979500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59979500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59979500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74463.171036 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74463.171036 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74880.774032 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74880.774032 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10294.680667 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1834001 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 117.889117 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 11312.672856 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9404.439964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.596313 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.644390 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.287001 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.593915 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10638.078941 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006581 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.314169 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.data 0.324648 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.345235 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15237953 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15237953 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits @@ -711,18 +709,18 @@ system.cpu.l2cache.demand_misses::total 15581 # nu system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses system.cpu.l2cache.overall_misses::total 15581 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1068633000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1068633000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58136500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 58136500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22289000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 22289000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58136500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1090922000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1149058500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58136500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1090922000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1149058500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1081439500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1081439500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58471000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 58471000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21652500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21652500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 58471000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1103092000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1161563000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 58471000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1103092000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1161563000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) @@ -751,18 +749,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016384 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73475.866337 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73475.866337 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75111.757106 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75111.757106 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84749.049430 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84749.049430 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73747.416725 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73747.416725 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74356.401265 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74356.401265 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75543.927649 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75543.927649 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82328.897338 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82328.897338 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74549.964701 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74549.964701 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -791,18 +789,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 923193000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 923193000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50340000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50340000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19328000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19328000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50340000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 942521000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 992861000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50340000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 942521000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 992861000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 935999500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 935999500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50673500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50673500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18685500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18685500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50673500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 954685000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1005358500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50673500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 954685000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1005358500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses @@ -815,25 +813,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63475.866337 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63475.866337 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65122.897801 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65122.897801 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75206.225681 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75206.225681 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64356.401265 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64356.401265 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65554.333765 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65554.333765 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72706.225681 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72706.225681 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution @@ -867,7 +865,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 1201999 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 15574 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution @@ -888,9 +892,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21833000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21795000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82137750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82138750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 0313fa682..a9bdce95d 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058199 # Number of seconds simulated -sim_ticks 58199030500 # Number of ticks simulated -final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058328 # Number of seconds simulated +sim_ticks 58328364500 # Number of ticks simulated +final_tick 58328364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122100 # Simulator instruction rate (inst/s) -host_op_rate 122709 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78442850 # Simulator tick rate (ticks/s) -host_mem_usage 487108 # Number of bytes of host memory used -host_seconds 741.93 # Real time elapsed on the host +host_inst_rate 135523 # Simulator instruction rate (inst/s) +host_op_rate 136198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87259482 # Simulator tick rate (ticks/s) +host_mem_usage 492508 # Number of bytes of host memory used +host_seconds 668.45 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory -system.physmem.bytes_read::total 1057024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory -system.physmem.bytes_written::total 11200 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 693 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1369 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 16516 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 175 # Number of write requests responded to by this memory -system.physmem.num_writes::total 175 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 762075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1505455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15894698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 18162227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 762075 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 762075 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 192443 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 192443 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 192443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 762075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1505455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15894698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18354670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 16517 # Number of read requests accepted -system.physmem.writeReqs 175 # Number of write requests accepted -system.physmem.readBursts 16517 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 175 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1048320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue -system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1057088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11200 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 218752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 921408 # Number of bytes read from this memory +system.physmem.bytes_read::total 1184896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5696 # Number of bytes written to this memory +system.physmem.bytes_written::total 5696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3418 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14397 # Number of read requests responded to by this memory +system.physmem.num_reads::total 18514 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 89 # Number of write requests responded to by this memory +system.physmem.num_writes::total 89 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 766968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3750354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15796911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 20314233 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 766968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 766968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 97654 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 97654 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 97654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 766968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3750354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15796911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20411887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 18515 # Number of read requests accepted +system.physmem.writeReqs 89 # Number of write requests accepted +system.physmem.readBursts 18515 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 89 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1179904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5056 # Total number of bytes read from write queue +system.physmem.bytesWritten 4480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1184960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5696 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 79 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1166 # Per bank write bursts -system.physmem.perBankRdBursts::1 920 # Per bank write bursts -system.physmem.perBankRdBursts::2 953 # Per bank write bursts +system.physmem.perBankRdBursts::0 3247 # Per bank write bursts +system.physmem.perBankRdBursts::1 921 # Per bank write bursts +system.physmem.perBankRdBursts::2 949 # Per bank write bursts system.physmem.perBankRdBursts::3 1031 # Per bank write bursts system.physmem.perBankRdBursts::4 1061 # Per bank write bursts -system.physmem.perBankRdBursts::5 1122 # Per bank write bursts -system.physmem.perBankRdBursts::6 1094 # Per bank write bursts -system.physmem.perBankRdBursts::7 1089 # Per bank write bursts -system.physmem.perBankRdBursts::8 1025 # Per bank write bursts +system.physmem.perBankRdBursts::5 1117 # Per bank write bursts +system.physmem.perBankRdBursts::6 1095 # Per bank write bursts +system.physmem.perBankRdBursts::7 1097 # Per bank write bursts +system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 933 # Per bank write bursts -system.physmem.perBankRdBursts::11 900 # Per bank write bursts -system.physmem.perBankRdBursts::12 903 # Per bank write bursts -system.physmem.perBankRdBursts::13 900 # Per bank write bursts -system.physmem.perBankRdBursts::14 1411 # Per bank write bursts -system.physmem.perBankRdBursts::15 910 # Per bank write bursts -system.physmem.perBankWrBursts::0 2 # Per bank write bursts +system.physmem.perBankRdBursts::10 932 # Per bank write bursts +system.physmem.perBankRdBursts::11 899 # Per bank write bursts +system.physmem.perBankRdBursts::12 902 # Per bank write bursts +system.physmem.perBankRdBursts::13 896 # Per bank write bursts +system.physmem.perBankRdBursts::14 1399 # Per bank write bursts +system.physmem.perBankRdBursts::15 904 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 6 # Per bank write bursts +system.physmem.perBankWrBursts::2 2 # Per bank write bursts system.physmem.perBankWrBursts::3 1 # Per bank write bursts -system.physmem.perBankWrBursts::4 3 # Per bank write bursts -system.physmem.perBankWrBursts::5 16 # Per bank write bursts -system.physmem.perBankWrBursts::6 40 # Per bank write bursts -system.physmem.perBankWrBursts::7 7 # Per bank write bursts +system.physmem.perBankWrBursts::4 2 # Per bank write bursts +system.physmem.perBankWrBursts::5 9 # Per bank write bursts +system.physmem.perBankWrBursts::6 10 # Per bank write bursts +system.physmem.perBankWrBursts::7 8 # Per bank write bursts system.physmem.perBankWrBursts::8 2 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 2 # Per bank write bursts -system.physmem.perBankWrBursts::11 2 # Per bank write bursts +system.physmem.perBankWrBursts::10 3 # Per bank write bursts +system.physmem.perBankWrBursts::11 3 # Per bank write bursts system.physmem.perBankWrBursts::12 2 # Per bank write bursts -system.physmem.perBankWrBursts::13 17 # Per bank write bursts -system.physmem.perBankWrBursts::14 37 # Per bank write bursts -system.physmem.perBankWrBursts::15 7 # Per bank write bursts +system.physmem.perBankWrBursts::13 9 # Per bank write bursts +system.physmem.perBankWrBursts::14 13 # Per bank write bursts +system.physmem.perBankWrBursts::15 6 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58199022000 # Total gap between requests +system.physmem.totGap 58328356000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 16517 # Read request sizes (log2) +system.physmem.readPktSize::6 18515 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 175 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 11454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 292 # What read queue length does an incoming req see +system.physmem.writePktSize::6 89 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 13470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 283 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -149,24 +149,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -198,98 +198,102 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1812 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 582.746137 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 353.648277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 424.722034 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 448 24.72% 24.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 213 11.75% 36.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96 5.30% 41.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 72 3.97% 45.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 56 3.09% 48.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 67 3.70% 52.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 61 3.37% 55.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 48 2.65% 58.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 751 41.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1812 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2016.250000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 98.342741 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 5441.040729 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 7 87.50% 87.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 12.50% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads -system.physmem.totQLat 175730624 # Total ticks spent queuing -system.physmem.totMemAccLat 482855624 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 81900000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10728.37 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 3107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 380.704216 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.847183 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 402.867268 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1088 35.02% 35.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 865 27.84% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94 3.03% 65.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 72 2.32% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 65 2.09% 70.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 68 2.19% 72.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 56 1.80% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 51 1.64% 75.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 748 24.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 3107 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 4608 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 1496.681558 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7484.705695 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 1 25.00% 25.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 1 25.00% 50.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.500000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.477704 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 25.00% 25.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3 75.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads +system.physmem.totQLat 204802662 # Total ticks spent queuing +system.physmem.totMemAccLat 550477662 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 92180000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11108.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29478.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 18.01 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 18.16 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29858.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 20.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 20.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage -system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.16 # Data bus utilization in percentage +system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing -system.physmem.readRowHits 14651 # Number of row buffer hits during reads -system.physmem.writeRowHits 51 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.82 # Row buffer hit rate for writes -system.physmem.avgGap 3486641.62 # Average gap between requests -system.physmem.pageHitRate 88.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 65512200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 486000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2714701095 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32535498750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39129012390 # Total energy per rank (pJ) -system.physmem_0.averagePower 672.381118 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54114607553 # Time in different power states -system.physmem_0.memoryStateTime::REF 1943240000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.38 # Average write queue length when enqueuing +system.physmem.readRowHits 15382 # Number of row buffer hits during reads +system.physmem.writeRowHits 10 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 11.49 # Row buffer hit rate for writes +system.physmem.avgGap 3135258.87 # Average gap between requests +system.physmem.pageHitRate 83.10 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 17803800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 9714375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 81876600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 162000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3809622960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6575109030 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29228595750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39722884515 # Total energy per rank (pJ) +system.physmem_0.averagePower 681.036990 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48583441495 # Time in different power states +system.physmem_0.memoryStateTime::REF 1947660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2137743447 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7795971005 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6017760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3283500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 61916400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 447120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2480426820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32741002500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39094071540 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.780705 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54458056984 # Time in different power states -system.physmem_1.memoryStateTime::REF 1943240000 # Time in different power states +system.physmem_1.actEnergy 5609520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3060750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 61760400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 187920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3809622960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2425538385 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32868570000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39174349935 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.632528 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54671634140 # Time in different power states +system.physmem_1.memoryStateTime::REF 1947660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1708703360 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 28233538 # Number of BP lookups -system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11829354 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11747655 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 28233990 # Number of BP lookups +system.cpu.branchPred.condPredicted 23266525 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 835401 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11829630 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11747896 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.309354 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 74541 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 92 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 27216 # Number of indirect predictor lookups. +system.cpu.branchPred.BTBHitPct 99.309074 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 74550 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 27225 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 25478 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 1747 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -319,7 +323,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -349,7 +353,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -379,7 +383,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -410,84 +414,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 116398062 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 116656730 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 746143 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134906479 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28233538 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11847674 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 114760827 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1674187 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 805 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32275055 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 562 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116345779 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.164712 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.318875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 746133 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134907690 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28233990 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11847924 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115018036 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1674227 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 853 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 829 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32275439 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 555 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116602964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.162155 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.318550 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58810972 50.55% 50.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13933527 11.98% 62.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9228064 7.93% 70.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34373216 29.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 59067374 50.66% 50.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13933709 11.95% 62.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9228635 7.91% 70.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34373246 29.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116345779 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.242560 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.159010 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8834252 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64111694 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33013656 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9560800 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825377 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4097950 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114395383 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1985420 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825377 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15270485 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49952350 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109536 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35410349 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14777682 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110872417 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1412237 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11132933 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1144918 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1526969 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 486977 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129945519 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483152587 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119447216 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116602964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242026 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.156450 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8835100 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64368120 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33012562 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9561783 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 825399 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4097891 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11814 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114395515 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1985251 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 825399 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15271601 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50089085 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 110009 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35409630 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14897240 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110872720 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1412183 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11133547 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1231881 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1645196 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 486344 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129945840 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483153679 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119447461 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 433 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22632600 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22632921 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21510749 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26805153 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5347343 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 519410 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 254099 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109667150 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21513680 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26805319 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5347286 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 522469 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 256366 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109667529 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101366848 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074801 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18634403 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41667039 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101366370 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074686 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18634782 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41671490 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116345779 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.871255 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.989200 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 116602964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.869329 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.988911 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54714850 47.03% 47.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31358235 26.95% 73.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22007860 18.92% 92.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7066756 6.07% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197765 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54969091 47.14% 47.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31363076 26.90% 74.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22007447 18.87% 92.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7065313 6.06% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197724 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -495,9 +499,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116345779 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116602964 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9784213 48.67% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9783594 48.67% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available @@ -526,13 +530,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9614548 47.83% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 702998 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9615674 47.83% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 702930 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71970791 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10698 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71970691 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued @@ -556,86 +560,86 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24337715 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5047462 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24337594 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5047205 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101366848 # Type of FU issued -system.cpu.iq.rate 0.870864 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20101822 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198308 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340255638 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128310520 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99608490 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 101366370 # Type of FU issued +system.cpu.iq.rate 0.868929 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20102261 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340512191 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128311283 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99607990 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 624 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121468430 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 288068 # Number of loads that had data forwarded from stores +system.cpu.iq.fp_inst_queue_writes 628 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121468392 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 288047 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4329242 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1500 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1342 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602499 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4329408 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 602442 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7579 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130663 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130712 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825377 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8119454 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 685980 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109688255 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 825399 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8206553 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 706266 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109688634 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26805153 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5347343 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26805319 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5347286 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 180270 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 342292 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1342 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 435059 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412404 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 847463 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100109842 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23803071 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1257006 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 180569 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 362078 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 435086 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412401 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 847487 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100109489 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23802993 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1256881 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12822 # number of nop insts executed -system.cpu.iew.exec_refs 28718921 # number of memory reference insts executed -system.cpu.iew.exec_branches 20621209 # Number of branches executed -system.cpu.iew.exec_stores 4915850 # Number of stores executed -system.cpu.iew.exec_rate 0.860065 # Inst execution rate -system.cpu.iew.wb_sent 99693752 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99608605 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59691637 # num instructions producing a value -system.cpu.iew.wb_consumers 95527463 # num instructions consuming a value -system.cpu.iew.wb_rate 0.855758 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624864 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17362842 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 28718621 # number of memory reference insts executed +system.cpu.iew.exec_branches 20621294 # Number of branches executed +system.cpu.iew.exec_stores 4915628 # Number of stores executed +system.cpu.iew.exec_rate 0.858154 # Inst execution rate +system.cpu.iew.wb_sent 99693258 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99608103 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59691284 # num instructions producing a value +system.cpu.iew.wb_consumers 95529167 # num instructions consuming a value +system.cpu.iew.wb_rate 0.853856 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624849 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17363279 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 823674 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113658017 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.801119 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.737711 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 823687 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113915056 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.799312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.736114 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77235221 67.95% 67.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18611593 16.38% 84.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7151823 6.29% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3469408 3.05% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1644636 1.45% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 541902 0.48% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 703188 0.62% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 178974 0.16% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4121272 3.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77490817 68.03% 68.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18611366 16.34% 84.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7154135 6.28% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3469454 3.05% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644903 1.44% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541342 0.48% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 703110 0.62% 96.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178773 0.16% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4121156 3.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113658017 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113915056 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -681,80 +685,80 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4121272 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 217947492 # The number of ROB reads -system.cpu.rob.rob_writes 219521309 # The number of ROB writes -system.cpu.timesIdled 570 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 52283 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4121156 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 218205084 # The number of ROB reads +system.cpu.rob.rob_writes 219522331 # The number of ROB writes +system.cpu.timesIdled 576 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53766 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.284891 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.284891 # CPI: Total CPI of All Threads -system.cpu.ipc 0.778276 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.778276 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108097873 # number of integer regfile reads -system.cpu.int_regfile_writes 58692304 # number of integer regfile writes -system.cpu.fp_regfile_reads 59 # number of floating regfile reads -system.cpu.fp_regfile_writes 96 # number of floating regfile writes -system.cpu.cc_regfile_reads 369004699 # number of cc regfile reads -system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes -system.cpu.misc_regfile_reads 28410105 # number of misc regfile reads +system.cpu.cpi 1.287747 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.287747 # CPI: Total CPI of All Threads +system.cpu.ipc 0.776550 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.776550 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108097252 # number of integer regfile reads +system.cpu.int_regfile_writes 58691902 # number of integer regfile writes +system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.fp_regfile_writes 93 # number of floating regfile writes +system.cpu.cc_regfile_reads 369002875 # number of cc regfile reads +system.cpu.cc_regfile_writes 58686679 # number of cc regfile writes +system.cpu.misc_regfile_reads 28409649 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 5470634 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5471146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.335565 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 35796500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.784091 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999578 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 5470636 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.779483 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18249262 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5471148 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.335545 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 36545500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.779483 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999569 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999569 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353747 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61906894 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61906894 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 13887138 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13887138 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353836 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353836 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18241078 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18241078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18241600 # number of overall hits -system.cpu.dcache.overall_hits::total 18241600 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9587264 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9587264 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381234 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381234 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18240974 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18240974 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18241496 # number of overall hits +system.cpu.dcache.overall_hits::total 18241496 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9587451 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9587451 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381145 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381145 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9968498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9968498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9968505 # number of overall misses -system.cpu.dcache.overall_misses::total 9968505 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88773272500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88773272500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000795875 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4000795875 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 291000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 291000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92774068375 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92774068375 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92774068375 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92774068375 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23474595 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23474595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9968596 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9968596 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9968603 # number of overall misses +system.cpu.dcache.overall_misses::total 9968603 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88929958000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88929958000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000514273 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4000514273 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 284000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 284000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92930472273 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92930472273 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92930472273 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92930472273 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23474589 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23474589 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -763,470 +767,474 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28209576 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28209576 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28210105 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28210105 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080514 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080514 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28209570 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28209570 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28210099 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28210099 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408418 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408418 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353373 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353373 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353366 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353366 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9259.500156 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9259.500156 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10494.331238 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10494.331238 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19400 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19400 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9306.724882 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9306.724882 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9306.718347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9306.718347 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 329915 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 108865 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121409 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.353376 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353376 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353370 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353370 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9275.662322 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9275.662322 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10496.042905 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10496.042905 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20285.714286 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20285.714286 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9322.323051 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9322.323051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9322.316504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9322.316504 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 330469 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 108734 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121517 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717385 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.479903 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 5470634 # number of writebacks -system.cpu.dcache.writebacks::total 5470634 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338603 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4338603 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158750 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158750 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4497353 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4497353 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4497353 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4497353 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248661 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248661 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222484 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222484 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.719529 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.469699 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 5470636 # number of writebacks +system.cpu.dcache.writebacks::total 5470636 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338792 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4338792 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158657 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158657 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4497449 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4497449 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4497449 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4497449 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248659 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248659 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222488 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222488 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43288788000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43288788000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285573254 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285573254 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45574361254 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45574361254 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45574575754 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45574575754 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5471147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5471147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5471151 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5471151 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43429617000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43429617000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285050165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285050165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 217500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 217500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45714667165 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45714667165 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45714884665 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45714884665 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223589 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223589 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046987 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046987 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8247.586956 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8247.586956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8274.421524 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8274.421524 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.442294 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.442294 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54375 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54375 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8355.591097 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8355.591097 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8355.624742 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8355.624742 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 447 # number of replacements -system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 427.481000 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32274286 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35701.214602 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 35701.643805 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 427.448157 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.834860 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.834860 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 427.481000 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.834924 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.834924 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 457 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32273898 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32273898 # number of overall hits -system.cpu.icache.overall_hits::total 32273898 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1145 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1145 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1145 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1145 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1145 # number of overall misses -system.cpu.icache.overall_misses::total 1145 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60302481 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60302481 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60302481 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60302481 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60302481 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60302481 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32275043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32275043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32275043 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32275043 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32275043 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32275043 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64551760 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64551760 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 32274286 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32274286 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32274286 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32274286 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32274286 # number of overall hits +system.cpu.icache.overall_hits::total 32274286 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1142 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1142 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1142 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1142 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1142 # number of overall misses +system.cpu.icache.overall_misses::total 1142 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61976480 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61976480 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61976480 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61976480 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61976480 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61976480 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32275428 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32275428 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32275428 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32275428 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32275428 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32275428 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52665.922271 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52665.922271 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52665.922271 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52665.922271 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 18953 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54270.122592 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54270.122592 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54270.122592 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54270.122592 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54270.122592 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54270.122592 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 19008 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 148 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 219 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 86.543379 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.794521 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29.600000 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 447 # number of writebacks system.cpu.icache.writebacks::total 447 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 240 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 240 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 240 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 240 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 240 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 240 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 237 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 237 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 237 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 237 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 237 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 237 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 905 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 905 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 905 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 905 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 905 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 905 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49734485 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49734485 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49734485 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49734485 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49734485 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49734485 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50842984 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50842984 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50842984 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50842984 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50842984 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50842984 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56180.092818 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56180.092818 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56180.092818 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 56180.092818 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56180.092818 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 56180.092818 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 4982437 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5296601 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 273114 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 248 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 14915 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 356.578880 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14074231 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 123 # number of replacements +system.cpu.l2cache.tags.tagsinuse 11197.361342 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5291777 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 14677 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 360.548954 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 174.301588 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.675141 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010639 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.685780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 181 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14486 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 168 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3489 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9544 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 884 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 17033 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 226019 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 226019 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 210 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 210 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243562 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5243562 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 210 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5469581 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5469791 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 210 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5469581 # number of overall hits -system.cpu.l2cache.overall_hits::total 5469791 # number of overall hits +system.cpu.l2cache.tags.occ_blocks::writebacks 11137.339599 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 60.021743 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.679769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003663 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.683433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 61 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14493 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3478 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9594 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 118 # 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number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 866631987 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 46500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 46500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32627500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32627500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44309000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44309000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 208942500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 208942500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44309000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 241570000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 285879000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44309000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 241570000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 866631987 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1152510987 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.766851 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000196 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000196 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000377 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001505 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001505 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.773481 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000625 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000753 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000625 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058141 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2697.430895 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13833.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13833.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95745.614035 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95745.614035 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62242.795389 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62242.795389 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61881.809339 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058605 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2737.542327 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2737.542327 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95681.818182 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95681.818182 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63298.571429 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63298.571429 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67882.553606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67882.553606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63298.571429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70655.162328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69404.952658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63298.571429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70655.162328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2737.542327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3593.825187 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 10943139 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_filter.tot_snoops 302176 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302175 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1794 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 317966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5457869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13303 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318447 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226521 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226521 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 905 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244627 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2256 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16415192 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412942 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16415198 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700360640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 319939 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 11456 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5791989 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.053010 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.224658 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700360896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318574 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5952 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5790626 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052683 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.223400 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485738 94.71% 94.71% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305466 5.27% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 785 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485560 94.73% 94.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305065 5.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5791989 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10942648515 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5790626 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10942652515 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1357497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206727492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 16175 # Transaction distribution -system.membus.trans_dist::WritebackDirty 175 # Transaction distribution -system.membus.trans_dist::CleanEvict 63 # Transaction distribution +system.membus.snoop_filter.tot_requests 18642 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 3008 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 18174 # Transaction distribution +system.membus.trans_dist::WritebackDirty 89 # Transaction distribution +system.membus.trans_dist::CleanEvict 34 # Transaction distribution system.membus.trans_dist::UpgradeReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 341 # Transaction distribution -system.membus.trans_dist::ReadExResp 341 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 16176 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 33275 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 33275 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1068224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1068224 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 340 # Transaction distribution +system.membus.trans_dist::ReadExResp 340 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 18175 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 37156 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1190592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1190592 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 16759 # Request fanout histogram +system.membus.snoop_fanout::samples 18519 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16759 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 18519 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16759 # Request fanout histogram -system.membus.reqLayer0.occupancy 27529285 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 86434816 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_fanout::total 18519 # Request fanout histogram +system.membus.reqLayer0.occupancy 29524488 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 97237655 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index b912f8d81..b27dfcb1b 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.361598 # Number of seconds simulated -sim_ticks 361597758500 # Number of ticks simulated -final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.361613 # Number of seconds simulated +sim_ticks 361613361500 # Number of ticks simulated +final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1165746 # Simulator instruction rate (inst/s) -host_op_rate 1165794 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1728825291 # Simulator tick rate (ticks/s) -host_mem_usage 381188 # Number of bytes of host memory used -host_seconds 209.16 # Real time elapsed on the host +host_inst_rate 1370596 # Simulator instruction rate (inst/s) +host_op_rate 1370653 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2032709522 # Simulator tick rate (ticks/s) +host_mem_usage 385816 # Number of bytes of host memory used +host_seconds 177.90 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory system.physmem.bytes_read::total 998592 # Number of bytes read from this memory @@ -22,19 +22,19 @@ system.physmem.bytes_inst_read::total 56256 # Nu system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 155569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2605921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2761491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155569 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155569 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2605921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2761491 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 361597758500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 723195517 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 361613361500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 723226723 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles +system.cpu.num_busy_cycles 723226722.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched @@ -92,25 +92,25 @@ system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3562.404243 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 134415942500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.404243 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869728 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869728 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits @@ -131,16 +131,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614992000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11614992000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1335530000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1335530000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 102000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 102000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12950522000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12950522000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12950522000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12950522000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) @@ -161,16 +161,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.793121 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.793121 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28591.950332 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28591.950332 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25500 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 25500 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13783.500272 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13783.500272 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -189,16 +189,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10722135000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10722135000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1288820000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1288820000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 98000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 98000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12010955000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12010955000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12010955000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12010955000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses @@ -209,26 +209,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.793121 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.793121 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27591.950332 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27591.950332 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 725.403723 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 725.403723 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354201 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354201 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id @@ -237,7 +237,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 781 system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits @@ -250,12 +250,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 55422500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 55422500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 55422500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 55422500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 55422500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 55422500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses @@ -268,12 +268,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62837.301587 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62837.301587 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62837.301587 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62837.301587 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -288,48 +288,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 882 system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54540500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 54540500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54540500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 54540500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54540500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 54540500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61837.301587 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61837.301587 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10855.563013 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1860349 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15603 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 119.230212 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.626846 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10116.936167 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.data 0.308744 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.331285 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15603 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15465 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.476166 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15023219 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15023219 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits @@ -358,18 +356,18 @@ system.cpu.l2cache.demand_misses::total 15603 # nu system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses system.cpu.l2cache.overall_misses::total 15603 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 881303500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 881303500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53183000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 53183000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9498500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 9498500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 53183000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 890802000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 943985000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 53183000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 890802000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 943985000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses) @@ -398,18 +396,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016591 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.224316 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.224316 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -428,18 +426,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15603 system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 735633500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 735633500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44393000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44393000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7928500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7928500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44393000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 743562000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 787955000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44393000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 743562000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 787955000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses @@ -452,25 +450,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution @@ -504,7 +502,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 1323000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 15603 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1036 # Transaction distribution system.membus.trans_dist::ReadExReq 14567 # Transaction distribution system.membus.trans_dist::ReadExResp 14567 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 4b965d579..1e87ba0e2 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,78 +1,78 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065987 # Number of seconds simulated -sim_ticks 65986743500 # Number of ticks simulated -final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065554 # Number of seconds simulated +sim_ticks 65553895500 # Number of ticks simulated +final_tick 65553895500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86207 # Simulator instruction rate (inst/s) -host_op_rate 151797 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36005878 # Simulator tick rate (ticks/s) -host_mem_usage 411344 # Number of bytes of host memory used -host_seconds 1832.67 # Real time elapsed on the host +host_inst_rate 122580 # Simulator instruction rate (inst/s) +host_op_rate 215844 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50862026 # Simulator tick rate (ticks/s) +host_mem_usage 417260 # Number of bytes of host memory used +host_seconds 1288.86 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory -system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 69440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 69440 # Number of instructions bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 69632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1890944 # Number of bytes read from this memory +system.physmem.bytes_read::total 1960576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 69632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 69632 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 17920 # Number of bytes written to this memory system.physmem.bytes_written::total 17920 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1085 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29537 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30622 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1088 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29546 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30634 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 280 # Number of write requests responded to by this memory system.physmem.num_writes::total 280 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1052333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28647693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29700026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1052333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1052333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 271570 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 271570 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 271570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1052333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28647693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29971596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30622 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 1062210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28845639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29907849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1062210 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1062210 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 273363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 273363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 273363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1062210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28845639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30181212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30634 # Number of read requests accepted system.physmem.writeReqs 280 # Number of write requests accepted -system.physmem.readBursts 30622 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 30634 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 280 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1952768 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue -system.physmem.bytesWritten 16064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1959808 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 1951616 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue +system.physmem.bytesWritten 16000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1960576 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 17920 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1932 # Per bank write bursts -system.physmem.perBankRdBursts::1 2084 # Per bank write bursts -system.physmem.perBankRdBursts::2 2041 # Per bank write bursts -system.physmem.perBankRdBursts::3 1935 # Per bank write bursts -system.physmem.perBankRdBursts::4 2086 # Per bank write bursts -system.physmem.perBankRdBursts::5 1909 # Per bank write bursts -system.physmem.perBankRdBursts::6 1974 # Per bank write bursts -system.physmem.perBankRdBursts::7 1865 # Per bank write bursts -system.physmem.perBankRdBursts::8 1948 # Per bank write bursts +system.physmem.perBankRdBursts::0 1938 # Per bank write bursts +system.physmem.perBankRdBursts::1 2083 # Per bank write bursts +system.physmem.perBankRdBursts::2 2040 # Per bank write bursts +system.physmem.perBankRdBursts::3 1941 # Per bank write bursts +system.physmem.perBankRdBursts::4 2041 # Per bank write bursts +system.physmem.perBankRdBursts::5 1918 # Per bank write bursts +system.physmem.perBankRdBursts::6 1976 # Per bank write bursts +system.physmem.perBankRdBursts::7 1870 # Per bank write bursts +system.physmem.perBankRdBursts::8 1951 # Per bank write bursts system.physmem.perBankRdBursts::9 1940 # Per bank write bursts -system.physmem.perBankRdBursts::10 1806 # Per bank write bursts +system.physmem.perBankRdBursts::10 1805 # Per bank write bursts system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1799 # Per bank write bursts -system.physmem.perBankRdBursts::14 1828 # Per bank write bursts +system.physmem.perBankRdBursts::14 1827 # Per bank write bursts system.physmem.perBankRdBursts::15 1779 # Per bank write bursts system.physmem.perBankWrBursts::0 10 # Per bank write bursts system.physmem.perBankWrBursts::1 107 # Per bank write bursts -system.physmem.perBankWrBursts::2 30 # Per bank write bursts -system.physmem.perBankWrBursts::3 12 # Per bank write bursts -system.physmem.perBankWrBursts::4 60 # Per bank write bursts -system.physmem.perBankWrBursts::5 8 # Per bank write bursts +system.physmem.perBankWrBursts::2 31 # Per bank write bursts +system.physmem.perBankWrBursts::3 25 # Per bank write bursts +system.physmem.perBankWrBursts::4 39 # Per bank write bursts +system.physmem.perBankWrBursts::5 13 # Per bank write bursts system.physmem.perBankWrBursts::6 16 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 1 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 5 # Per bank write bursts system.physmem.perBankWrBursts::10 3 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 65986546500 # Total gap between requests +system.physmem.totGap 65553697500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30622 # Read request sizes (log2) +system.physmem.readPktSize::6 30634 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,11 +98,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 280 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29999 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 29978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -147,18 +147,18 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see @@ -194,336 +194,335 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 694.731190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 483.360902 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 396.952113 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 443 15.65% 15.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 258 9.11% 24.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 108 3.81% 28.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 115 4.06% 32.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 113 3.99% 36.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 115 4.06% 40.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 137 4.84% 45.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 80 2.83% 48.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1462 51.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2831 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2859 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 687.860091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 477.665686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 399.129385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 441 15.42% 15.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 263 9.20% 24.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 134 4.69% 29.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 136 4.76% 34.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 118 4.13% 38.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 116 4.06% 42.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 85 2.97% 45.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 96 3.36% 48.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1470 51.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2859 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2175.285714 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 28.380874 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 8064.070078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2173.928571 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.222071 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 8074.812153 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 13 92.86% 92.86% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 7.14% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 14 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.928571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.918266 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.615728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.857143 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.849200 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.534522 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 1 7.14% 7.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 12 85.71% 92.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 7.14% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 13 92.86% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 14 # Writes before turning the bus around for reads -system.physmem.totQLat 136557750 # Total ticks spent queuing -system.physmem.totMemAccLat 708657750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 152560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4475.54 # Average queueing delay per DRAM burst +system.physmem.totQLat 136299000 # Total ticks spent queuing +system.physmem.totMemAccLat 708061500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152470000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4469.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23225.54 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.59 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23219.70 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.27 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.53 # Average write queue length when enqueuing -system.physmem.readRowHits 27745 # Number of row buffer hits during reads -system.physmem.writeRowHits 178 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 63.57 # Row buffer hit rate for writes -system.physmem.avgGap 2135348.73 # Average gap between requests -system.physmem.pageHitRate 90.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 11551680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 6303000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 123130800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1574640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3035388510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36925944000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 44413430070 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.125124 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 61414409250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2203240000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.62 # Average write queue length when enqueuing +system.physmem.readRowHits 27721 # Number of row buffer hits during reads +system.physmem.writeRowHits 161 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.50 # Row buffer hit rate for writes +system.physmem.avgGap 2120518.13 # Average gap between requests +system.physmem.pageHitRate 90.60 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11740680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 6406125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 123169800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1568160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4281566640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3052855305 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36653676000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 44130982710 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.213820 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 60959756000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2188940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2364289750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2404016500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9805320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5350125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114441600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9873360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5387250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114558600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3171429270 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36806601750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 44417217345 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.182663 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 61216839000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2203240000 # Time in different power states +system.physmem_1.refreshEnergy 4281566640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3230070300 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36498224250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 44139732240 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.347293 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 60700713000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2188940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2663059500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40828848 # Number of BP lookups -system.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26813424 # Number of BTB lookups +system.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40360668 # Number of BP lookups +system.cpu.branchPred.condPredicted 40360668 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1392637 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26664097 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6079027 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 92484 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26813424 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 21202389 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 5988252 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 86625 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26664097 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 21157452 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5506645 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 511906 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 131973488 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 131107792 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30825655 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 222121094 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40828848 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 27281416 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 99433771 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3060135 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 329 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 6280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 112427 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 29997924 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 374431 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 131908700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.964131 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.412100 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30523578 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219647427 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40360668 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27145704 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 98945290 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2900833 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 518 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 6239 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 114030 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 50 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29742559 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 352958 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 20 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 131040277 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.949675 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.407509 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65727022 49.83% 49.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4068693 3.08% 52.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3626407 2.75% 55.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6133247 4.65% 60.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7782444 5.90% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5574161 4.23% 70.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3387073 2.57% 73.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2926863 2.22% 75.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32682790 24.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65532629 50.01% 50.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4015050 3.06% 53.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3611452 2.76% 55.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6110552 4.66% 60.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7743592 5.91% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5553299 4.24% 70.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3377797 2.58% 73.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2818268 2.15% 75.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32277638 24.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131908700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309372 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.683074 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15512553 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64273138 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 40712149 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9880793 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1530067 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 365468602 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1530067 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 21068463 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11448631 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17559 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 44736331 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53107649 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355543189 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 24245 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 799476 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 46595900 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4792588 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 358065930 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 942303414 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 580264608 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 22491 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131040277 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307843 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.675319 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15257836 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64260169 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40205069 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9866787 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1450416 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 361840570 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1450416 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20789312 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11161609 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17754 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44252475 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53368711 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 352352816 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 16475 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 802883 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46797603 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4838735 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 354809982 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 933969547 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 575070468 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 25233 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78853183 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 501 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 500 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 64461317 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 113156478 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38725561 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 51813945 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9109294 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 346336448 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4423 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 319025181 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 175223 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 68148407 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 106206343 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3978 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131908700 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.418530 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.165753 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 75597235 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 487 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 488 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64661942 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112312024 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38476139 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51587404 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9144280 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343861767 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4715 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 317818488 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 169830 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65674018 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 101673382 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4270 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131040277 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.425350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.164581 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 35712645 27.07% 27.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20185531 15.30% 42.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17171104 13.02% 55.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17670057 13.40% 68.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15380757 11.66% 80.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12917935 9.79% 90.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6743014 5.11% 95.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4104772 3.11% 98.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2022885 1.53% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 35194225 26.86% 26.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20112862 15.35% 42.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17093441 13.04% 55.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17641161 13.46% 68.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15328111 11.70% 80.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12869587 9.82% 90.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6689257 5.10% 95.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4093724 3.12% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2017909 1.54% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131908700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131040277 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 364922 8.93% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3529438 86.37% 95.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 191983 4.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 366862 8.95% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3538662 86.29% 95.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 195200 4.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 182585704 57.23% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11686 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 478 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 321 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101596397 31.85% 89.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34797255 10.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 181791277 57.20% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11724 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 408 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 305 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101272470 31.86% 89.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34708964 10.92% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 319025181 # Type of FU issued -system.cpu.iq.rate 2.417343 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4086343 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012809 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 774202119 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 414517759 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 314637932 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 18509 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 33754 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4413 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 323069884 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8300 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57418928 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 317818488 # Type of FU issued +system.cpu.iq.rate 2.424101 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4100724 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012903 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 770927721 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 409562927 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 313648272 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 20086 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 38326 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4607 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 321877132 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8740 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57541030 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 22377093 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67905 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 65034 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7285809 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21532639 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67356 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 63407 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7036387 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4034 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 140997 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3908 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 141249 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1530067 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8343953 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3020633 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 346340871 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 136261 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 113156478 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38725561 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1825 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2944 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3026950 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 65034 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 548248 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1104057 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1652305 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 316487526 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100816589 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2537655 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1450416 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8045146 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3020269 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343866482 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 122594 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112312024 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38476139 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1910 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3213 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3025719 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 63407 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 529775 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1033204 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1562979 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 315414153 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100518036 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2404335 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 135188403 # number of memory reference insts executed -system.cpu.iew.exec_branches 32185799 # Number of branches executed -system.cpu.iew.exec_stores 34371814 # Number of stores executed -system.cpu.iew.exec_rate 2.398114 # Inst execution rate -system.cpu.iew.wb_sent 315304152 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 314642345 # cumulative count of insts written-back -system.cpu.iew.wb_producers 238446717 # num instructions producing a value -system.cpu.iew.wb_consumers 344411432 # num instructions consuming a value -system.cpu.iew.wb_rate 2.384133 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692331 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68273083 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 134824639 # number of memory reference insts executed +system.cpu.iew.exec_branches 32104448 # Number of branches executed +system.cpu.iew.exec_stores 34306603 # Number of stores executed +system.cpu.iew.exec_rate 2.405762 # Inst execution rate +system.cpu.iew.wb_sent 314286106 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 313652879 # cumulative count of insts written-back +system.cpu.iew.wb_producers 237682188 # num instructions producing a value +system.cpu.iew.wb_consumers 343423954 # num instructions consuming a value +system.cpu.iew.wb_rate 2.392328 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 65797430 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1477187 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122118176 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.278059 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.046851 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1399141 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 121633848 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.287130 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.051606 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 56957157 46.64% 46.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16546673 13.55% 60.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11180219 9.16% 69.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8765216 7.18% 76.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2116572 1.73% 78.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1764817 1.45% 79.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 934979 0.77% 80.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 730886 0.60% 81.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23121657 18.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 56556051 46.50% 46.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16464352 13.54% 60.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11233282 9.24% 69.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8748892 7.19% 76.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2045691 1.68% 78.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1756798 1.44% 79.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 927336 0.76% 80.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727466 0.60% 80.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23173980 19.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122118176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 121633848 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,337 +568,336 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23121657 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 445462066 # The number of ROB reads -system.cpu.rob.rob_writes 702797421 # The number of ROB writes -system.cpu.timesIdled 887 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64788 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23173980 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 442449762 # The number of ROB reads +system.cpu.rob.rob_writes 697455131 # The number of ROB writes +system.cpu.timesIdled 919 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 67515 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.835336 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.835336 # CPI: Total CPI of All Threads -system.cpu.ipc 1.197123 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.197123 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 504041942 # number of integer regfile reads -system.cpu.int_regfile_writes 248656420 # number of integer regfile writes -system.cpu.fp_regfile_reads 4180 # number of floating regfile reads -system.cpu.fp_regfile_writes 782 # number of floating regfile writes -system.cpu.cc_regfile_reads 109261684 # number of cc regfile reads -system.cpu.cc_regfile_writes 65602098 # number of cc regfile writes -system.cpu.misc_regfile_reads 202573497 # number of misc regfile reads +system.cpu.cpi 0.829856 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.829856 # CPI: Total CPI of All Threads +system.cpu.ipc 1.205028 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.205028 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 502814986 # number of integer regfile reads +system.cpu.int_regfile_writes 247784196 # number of integer regfile writes +system.cpu.fp_regfile_reads 4396 # number of floating regfile reads +system.cpu.fp_regfile_writes 732 # number of floating regfile writes +system.cpu.cc_regfile_reads 109093589 # number of cc regfile reads +system.cpu.cc_regfile_writes 65488596 # number of cc regfile writes +system.cpu.misc_regfile_reads 201890594 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2073508 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2077604 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.604569 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21372047500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.413497 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993265 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993265 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2073601 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.108072 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71473739 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077697 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.400463 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21041764500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.108072 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993190 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993190 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3404 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 507 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3433 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31346019 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71894591 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71894591 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71894591 # number of overall hits -system.cpu.dcache.overall_hits::total 71894591 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2693971 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2693971 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93733 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93733 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2787704 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2787704 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2787704 # number of overall misses -system.cpu.dcache.overall_misses::total 2787704 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32332975500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32332975500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2952822993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2952822993 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35285798493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35285798493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35285798493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35285798493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 43242543 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 43242543 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 150601371 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 150601371 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 40127755 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40127755 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345984 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345984 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71473739 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71473739 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71473739 # number of overall hits +system.cpu.dcache.overall_hits::total 71473739 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2694330 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2694330 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93768 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93768 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2788098 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2788098 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2788098 # number of overall misses +system.cpu.dcache.overall_misses::total 2788098 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32345718500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32345718500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2982305493 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2982305493 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35328023993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35328023993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35328023993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35328023993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42822085 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42822085 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74682295 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74682295 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74682295 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74682295 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062299 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062299 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037328 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037328 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037328 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12001.976079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12001.976079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31502.491044 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31502.491044 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12657.656083 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12657.656083 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 219202 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 497 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43207 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74261837 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74261837 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74261837 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74261837 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062919 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.062919 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002982 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002982 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037544 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037544 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037544 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037544 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12005.106464 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12005.106464 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31805.152003 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31805.152003 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12671.012279 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12671.012279 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12671.012279 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12671.012279 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 218790 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 393 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43059 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.073298 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 124.250000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2066969 # number of writebacks -system.cpu.dcache.writebacks::total 2066969 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698217 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 698217 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 710100 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 710100 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 710100 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 710100 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995754 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1995754 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81850 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81850 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077604 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077604 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077604 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077604 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24221413500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24221413500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2795777993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2795777993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27017191493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27017191493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27017191493 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27017191493 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046153 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046153 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002603 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002603 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027819 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.472481 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.472481 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 93 # number of replacements -system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1113 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26951.013477 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.081168 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.250000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2067196 # number of writebacks +system.cpu.dcache.writebacks::total 2067196 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698496 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 698496 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11905 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11905 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 710401 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 710401 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 710401 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 710401 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995834 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1995834 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81863 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81863 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2077697 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2077697 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2077697 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2077697 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24223051500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24223051500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2825101993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2825101993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27048153493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27048153493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27048153493 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27048153493 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046608 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046608 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002604 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002604 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027978 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027978 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027978 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027978 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.806718 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.806718 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34510.120482 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34510.120482 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13018.333998 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13018.333998 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13018.333998 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13018.333998 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 91 # number of replacements +system.cpu.icache.tags.tagsinuse 875.979350 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29741086 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1117 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26625.860340 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 870.928206 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.425258 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.425258 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1020 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 34 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59996959 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 29996478 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 29996478 # number of overall hits -system.cpu.icache.overall_hits::total 29996478 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1445 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1445 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1445 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1445 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1445 # number of overall misses -system.cpu.icache.overall_misses::total 1445 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 106088999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 106088999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 106088999 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29988 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 166 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29650 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.915161 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33250579 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33250579 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2067196 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2067196 # 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average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78090.073529 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75660.682226 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75660.682226 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78090.073529 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74072.277127 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74214.973559 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78090.073529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74072.277127 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74214.973559 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -908,122 +906,128 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.writebacks::writebacks 280 # number of writebacks system.cpu.l2cache.writebacks::total 280 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28982 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28982 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1085 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1085 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 555 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 555 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1085 # 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mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974843 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000278 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014731 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014731 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63047.391484 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63047.391484 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66228.110599 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66228.110599 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68210.810811 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68210.810811 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4152318 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073604 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28989 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28989 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1856506500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74082000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74082000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 36573000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 36573000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74082000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1893079500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1967161500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74082000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1893079500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1967161500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.354004 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.354004 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974038 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000279 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000279 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014736 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014736 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64041.757218 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64041.757218 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68090.073529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68090.073529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65660.682226 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65660.682226 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68090.073529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64072.277127 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64214.973559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68090.073529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64072.277127 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64214.973559 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4152506 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073696 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 331 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6909 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81888 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81888 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1113 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995716 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2319 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228716 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6231035 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265252672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265329856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 650 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1996925 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2067476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 91 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1117 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995808 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2325 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228995 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6231320 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265273152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265350464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 663 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 17920 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2079367 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2079477 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000168 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012972 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2079019 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 348 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2079127 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 350 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2079367 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4143221000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2079477 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4143540000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1670997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1675999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1640 # Transaction distribution +system.cpu.toL2Bus.respLayer1.occupancy 3116545500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 30966 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 332 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1645 # Transaction distribution system.membus.trans_dist::WritebackDirty 280 # Transaction distribution -system.membus.trans_dist::CleanEvict 45 # Transaction distribution -system.membus.trans_dist::ReadExReq 28982 # Transaction distribution -system.membus.trans_dist::ReadExResp 28982 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1640 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61569 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61569 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61569 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1977728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1977728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1977728 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::CleanEvict 52 # Transaction distribution +system.membus.trans_dist::ReadExReq 28989 # Transaction distribution +system.membus.trans_dist::ReadExResp 28989 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1645 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61600 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1978496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1978496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1978496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30947 # Request fanout histogram +system.membus.snoop_fanout::samples 30634 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30947 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30634 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30947 # Request fanout histogram -system.membus.reqLayer0.occupancy 43483000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30634 # Request fanout histogram +system.membus.reqLayer0.occupancy 43502500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 161384500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 161439750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 8197faf7d..683cfaa02 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366199 # Number of seconds simulated -sim_ticks 366199170500 # Number of ticks simulated -final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366229 # Number of seconds simulated +sim_ticks 366229314500 # Number of ticks simulated +final_tick 366229314500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 454673 # Simulator instruction rate (inst/s) -host_op_rate 800606 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1053878980 # Simulator tick rate (ticks/s) -host_mem_usage 406480 # Number of bytes of host memory used -host_seconds 347.48 # Real time elapsed on the host +host_inst_rate 561124 # Simulator instruction rate (inst/s) +host_op_rate 988050 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1300728257 # Simulator tick rate (ticks/s) +host_mem_usage 412916 # Number of bytes of host memory used +host_seconds 281.56 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory -system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1871552 # Number of bytes read from this memory +system.physmem.bytes_read::total 1922944 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6528 # Number of bytes written to this memory -system.physmem.bytes_written::total 6528 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory +system.physmem.bytes_written::total 6656 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29241 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory -system.physmem.num_writes::total 102 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 140339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5110399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5250738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 140339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 140339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17826 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17826 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 29243 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30046 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory +system.physmem.num_writes::total 104 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 140327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5110328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5250656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 140327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 140327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 18174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 18174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 18174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 140327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5110328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5268830 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 366199170500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 732398341 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 366229314500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 732458629 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -66,7 +66,7 @@ system.cpu.num_mem_refs 122219137 # nu system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 732398340.998000 # Number of busy cycles +system.cpu.num_busy_cycles 732458628.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29309705 # Number of branches fetched @@ -105,25 +105,25 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4076.272883 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126122344500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.299825 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995190 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 126128435500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.272883 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995184 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995184 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1779 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2195 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2198 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits @@ -140,14 +140,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25499993500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25499993500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2801625000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2801625000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28301618500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28301618500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28301618500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28301618500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25500310500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25500310500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2830649000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2830649000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28330959500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28330959500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28330959500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28330959500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) @@ -164,14 +164,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.423263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.423263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26403.273992 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26403.273992 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13693.255949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.584938 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.584938 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26676.804041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26676.804041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13707.452092 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13707.452092 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,14 +188,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539273500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539273500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2695516000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2695516000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26234789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26234789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26234789500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26234789500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539590500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539590500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2724540000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2724540000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26264130500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26264130500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26264130500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26264130500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses @@ -204,22 +204,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.584938 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.584938 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25676.804041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25676.804041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12707.452092 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12707.452092 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12707.452092 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12707.452092 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 24 # number of replacements -system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 665.626582 # Cycle average of tags in use system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 665.626582 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id @@ -229,7 +229,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 715 system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits @@ -242,12 +242,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 49857000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 49857000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 49857000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 49857000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 49857000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 49857000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50660000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50660000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50660000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50660000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50660000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50660000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses @@ -260,12 +260,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61704.207921 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61704.207921 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61704.207921 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62698.019802 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62698.019802 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62698.019802 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62698.019802 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -280,48 +280,48 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808 system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49049000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49049000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49852000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 49852000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49852000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 49852000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49852000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 49852000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 313 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61698.019802 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61698.019802 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61698.019802 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61698.019802 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61698.019802 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61698.019802 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 315 # number of replacements +system.cpu.l2cache.tags.tagsinuse 21080.806353 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4100347 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30047 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 136.464439 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 156.452862 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.589743 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016982 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.611500 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1692 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::writebacks 0.624695 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.051540 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20524.130118 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000019 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016969 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.626347 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.643335 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29732 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29568 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.907349 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33073199 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33073199 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits @@ -330,38 +330,38 @@ system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 5 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960503 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1960503 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960501 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1960501 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2037588 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2037593 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2037586 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2037591 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2037588 # number of overall hits -system.cpu.l2cache.overall_hits::total 2037593 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2037586 # number of overall hits +system.cpu.l2cache.overall_hits::total 2037591 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 803 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 217 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 217 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 219 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 219 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29241 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30044 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29243 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30046 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29241 # number of overall misses -system.cpu.l2cache.overall_misses::total 30044 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1726959000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1726959000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47782000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 47782000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12911500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 12911500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 47782000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1739870500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1787652500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 47782000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1739870500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1787652500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 29243 # number of overall misses +system.cpu.l2cache.overall_misses::total 30046 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1755983000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1755983000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48585000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 48585000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13249500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13249500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 48585000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1769232500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1817817500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 48585000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1769232500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1817817500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses) @@ -382,91 +382,91 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000111 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000111 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000112 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000112 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014148 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014531 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014149 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014532 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59504.358655 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59504.358655 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.148316 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014149 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014532 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.358655 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.358655 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.148239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.148239 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 102 # number of writebacks -system.cpu.l2cache.writebacks::total 102 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks +system.cpu.l2cache.writebacks::total 104 # number of writebacks system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 217 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 217 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 219 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 219 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29241 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30044 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29243 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30046 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1436719000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1436719000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39752000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39752000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10741500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10741500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39752000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1447460500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1487212500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39752000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1447460500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1487212500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 29243 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30046 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1465743000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1465743000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40555000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40555000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11059500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11059500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40555000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1476802500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1517357500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40555000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1476802500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1517357500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000111 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000112 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014532 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.068082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.068082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49504.358655 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49504.358655 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014532 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.358655 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.358655 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2062586 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution @@ -479,53 +479,59 @@ system.cpu.toL2Bus.pkt_count::total 6198031 # Pa system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 313 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6528 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2067950 # Request fanout histogram +system.cpu.toL2Bus.snoops 315 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6656 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2067952 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2067753 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2067755 99.99% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2067950 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2067952 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1020 # Transaction distribution -system.membus.trans_dist::WritebackDirty 102 # Transaction distribution +system.membus.snoop_filter.tot_requests 30164 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 118 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1022 # Transaction distribution +system.membus.trans_dist::WritebackDirty 104 # Transaction distribution system.membus.trans_dist::CleanEvict 14 # Transaction distribution system.membus.trans_dist::ReadExReq 29024 # Transaction distribution system.membus.trans_dist::ReadExResp 29024 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1020 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60204 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60204 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60204 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1022 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60210 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60210 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60210 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1929600 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30160 # Request fanout histogram +system.membus.snoop_fanout::samples 30046 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30160 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30046 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30160 # Request fanout histogram -system.membus.reqLayer0.occupancy 30602500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30046 # Request fanout histogram +system.membus.reqLayer0.occupancy 30614500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 150220000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 150230000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |