diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref')
22 files changed, 485 insertions, 160 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 3ea467c54..dcc46b583 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 97b90c338..60efd00ac 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:22:28 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:32:09 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 0a1029305..90f8077ba 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.025989 # Nu sim_ticks 25988864000 # Number of ticks simulated final_tick 25988864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71403 # Simulator instruction rate (inst/s) -host_op_rate 71915 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20482160 # Simulator tick rate (ticks/s) -host_mem_usage 364344 # Number of bytes of host memory used -host_seconds 1268.85 # Real time elapsed on the host +host_inst_rate 141606 # Simulator instruction rate (inst/s) +host_op_rate 142623 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40620332 # Simulator tick rate (ticks/s) +host_mem_usage 364696 # Number of bytes of host memory used +host_seconds 639.80 # Real time elapsed on the host sim_insts 90599356 # Number of instructions simulated sim_ops 91249910 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 999040 # Number of bytes read from this memory -system.physmem.bytes_inst_read 46144 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2048 # Number of bytes written to this memory -system.physmem.num_reads 15610 # Number of read requests responded to by this memory -system.physmem.num_writes 32 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 38441080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1775530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 78803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 38519883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 46144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 952896 # Number of bytes read from this memory +system.physmem.bytes_read::total 999040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 46144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 46144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory +system.physmem.bytes_written::total 2048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 721 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14889 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15610 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory +system.physmem.num_writes::total 32 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1775530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36665550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38441080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1775530 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1775530 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 78803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 78803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 78803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1775530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36665550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 38519883 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -369,11 +382,17 @@ system.cpu.icache.demand_accesses::total 14156722 # nu system.cpu.icache.overall_accesses::cpu.inst 14156722 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 14156722 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000069 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000069 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000069 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34868.827160 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34868.827160 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34868.827160 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34868.827160 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34868.827160 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,11 +420,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 25625000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25625000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 25625000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34212.283044 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34212.283044 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34212.283044 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34212.283044 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34212.283044 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 943602 # number of replacements system.cpu.dcache.tagsinuse 3646.405021 # Cycle average of tags in use @@ -461,15 +486,25 @@ system.cpu.dcache.demand_accesses::total 29605337 # nu system.cpu.dcache.overall_accesses::cpu.data 29605337 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 29605337 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040373 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040373 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037182 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037182 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001355 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001355 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.039863 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.039863 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.039863 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039863 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5760.542992 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 5760.542992 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26197.875726 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26197.875726 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16125 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16125 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8809.367484 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 8809.367484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8809.367484 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 23104055 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 8078 # number of cycles access was blocked @@ -507,13 +542,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 3479231630 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3479231630 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 3479231630 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036356 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036356 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009190 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009190 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032011 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032011 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2656.699127 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2656.699127 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24753.157217 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24753.157217 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 3671.245091 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3671.245091 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 3671.245091 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 770 # number of replacements system.cpu.l2cache.tagsinuse 10017.166349 # Cycle average of tags in use @@ -578,18 +621,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 947698 system.cpu.l2cache.overall_accesses::total 948447 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963952 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000403 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001202 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.325962 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.325962 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963952 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015720 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016469 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963952 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015720 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016469 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.396122 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34262.362637 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34279.005525 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34352.380625 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34352.380625 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34347.279129 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.396122 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34350.181232 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34347.279129 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -633,18 +684,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 463107000 system.cpu.l2cache.overall_mshr_miss_latency::total 485521000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000393 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001190 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.325962 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.325962 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016458 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962617 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015711 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016458 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.378641 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31195.774648 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31123.141264 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31101.726985 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31101.726985 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31103.203075 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.378641 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31103.969373 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31103.203075 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 0dc5ea994..394878465 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout index 863d389ca..6025dc422 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:24:24 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:36:14 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 6150ebd1b..cb9066ccb 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.054241 # Nu sim_ticks 54240666000 # Number of ticks simulated final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1203852 # Simulator instruction rate (inst/s) -host_op_rate 1212496 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 720706000 # Simulator tick rate (ticks/s) -host_mem_usage 353596 # Number of bytes of host memory used -host_seconds 75.26 # Real time elapsed on the host +host_inst_rate 2223712 # Simulator instruction rate (inst/s) +host_op_rate 2239678 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1331261387 # Simulator tick rate (ticks/s) +host_mem_usage 354056 # Number of bytes of host memory used +host_seconds 40.74 # Real time elapsed on the host sim_insts 90602415 # Number of instructions simulated sim_ops 91252969 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 521339715 # Number of bytes read from this memory -system.physmem.bytes_inst_read 431323116 # Number of instructions bytes read from this memory -system.physmem.bytes_written 18908138 # Number of bytes written to this memory -system.physmem.num_reads 130384074 # Number of read requests responded to by this memory -system.physmem.num_writes 4738868 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9611602391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7952024704 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 348597084 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9960199475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 431323116 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 90016599 # Number of bytes read from this memory +system.physmem.bytes_read::total 521339715 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 431323116 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 431323116 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory +system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 107830779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 22553295 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130384074 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory +system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7952024704 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1659577687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9611602391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7952024704 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7952024704 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 348597084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 348597084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7952024704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2008174771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9960199475 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index 98847a36c..227acc83b 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout index 10d881c1d..b972e2aeb 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:24:48 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:37:05 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index d20615e1d..dd28872f6 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.148086 # Nu sim_ticks 148086239000 # Number of ticks simulated final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 549790 # Simulator instruction rate (inst/s) -host_op_rate 553732 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 898863423 # Simulator tick rate (ticks/s) -host_mem_usage 362780 # Number of bytes of host memory used -host_seconds 164.75 # Real time elapsed on the host +host_inst_rate 1056603 # Simulator instruction rate (inst/s) +host_op_rate 1064179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1727464138 # Simulator tick rate (ticks/s) +host_mem_usage 363220 # Number of bytes of host memory used +host_seconds 85.72 # Real time elapsed on the host sim_insts 90576869 # Number of instructions simulated sim_ops 91226321 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 986112 # Number of bytes read from this memory -system.physmem.bytes_inst_read 36992 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2048 # Number of bytes written to this memory -system.physmem.num_reads 15408 # Number of read requests responded to by this memory -system.physmem.num_writes 32 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 6659039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 249800 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 6672869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 949120 # Number of bytes read from this memory +system.physmem.bytes_read::total 986112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 36992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 36992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory +system.physmem.bytes_written::total 2048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14830 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15408 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory +system.physmem.num_writes::total 32 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 249800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6409238 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6659039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 249800 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 249800 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 13830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 13830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 249800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6409238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6672869 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 107830780 # nu system.cpu.icache.overall_accesses::cpu.inst 107830780 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 107830780 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54527.545910 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54527.545910 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54527.545910 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 30865000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 942702 # number of replacements system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use @@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 27284389 # nu system.cpu.dcache.overall_accesses::cpu.data 27284389 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 27284389 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14013.157237 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14013.157237 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27109.399472 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14657.859438 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14657.859438 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 11037638000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11037638000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 11037638000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11013.157237 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11013.157237 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11657.859438 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11657.859438 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 634 # number of replacements system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use @@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 946798 system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000313 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000955 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015663 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016264 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015663 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016264 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 593200000 system.cpu.l2cache.overall_mshr_miss_latency::total 616320000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000313 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000955 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini index addbca3ec..a0039b696 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout index 70118299e..c071d26fa 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:43:24 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:53:37 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index f04b9260d..804f585d6 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,23 +4,37 @@ sim_seconds 0.122216 # Nu sim_ticks 122215830000 # Number of ticks simulated final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1503519 # Simulator instruction rate (inst/s) -host_op_rate 1503581 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 753629165 # Simulator tick rate (ticks/s) -host_mem_usage 346024 # Number of bytes of host memory used -host_seconds 162.17 # Real time elapsed on the host +host_inst_rate 2951739 # Simulator instruction rate (inst/s) +host_op_rate 2951861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1479540198 # Simulator tick rate (ticks/s) +host_mem_usage 346528 # Number of bytes of host memory used +host_seconds 82.60 # Real time elapsed on the host sim_insts 243825163 # Number of instructions simulated sim_ops 243835278 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 1306360053 # Number of bytes read from this memory -system.physmem.bytes_inst_read 977686044 # Number of instructions bytes read from this memory -system.physmem.bytes_written 91606089 # Number of bytes written to this memory -system.physmem.num_reads 326641945 # Number of read requests responded to by this memory -system.physmem.num_writes 22901951 # Number of write requests responded to by this memory -system.physmem.num_other 3886 # Number of other requests responded to by this memory -system.physmem.bw_read 10688959466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7999667834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 749543566 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11438503032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 977686044 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 328674009 # Number of bytes read from this memory +system.physmem.bytes_read::total 1306360053 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 977686044 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977686044 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory +system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 244421511 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 82220434 # Number of read requests responded to by this memory +system.physmem.num_reads::total 326641945 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory +system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory +system.physmem.num_other::total 3886 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2689291633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10688959466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 749543566 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 749543566 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3438835198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11438503032 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.numCycles 244431661 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini index 861290241..e29268380 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout index 4ee289cc3..2436d9105 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:44:07 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:55:10 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 300c74bea..9186661e0 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.362431 # Nu sim_ticks 362430887000 # Number of ticks simulated final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 628265 # Simulator instruction rate (inst/s) -host_op_rate 628291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 933876298 # Simulator tick rate (ticks/s) -host_mem_usage 354916 # Number of bytes of host memory used -host_seconds 388.09 # Real time elapsed on the host +host_inst_rate 1267775 # Simulator instruction rate (inst/s) +host_op_rate 1267827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1884467398 # Simulator tick rate (ticks/s) +host_mem_usage 355400 # Number of bytes of host memory used +host_seconds 192.33 # Real time elapsed on the host sim_insts 243825163 # Number of instructions simulated sim_ops 243835278 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 1001472 # Number of bytes read from this memory -system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2560 # Number of bytes written to this memory -system.physmem.num_reads 15648 # Number of read requests responded to by this memory -system.physmem.num_writes 40 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2763208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 155219 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 7063 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 2770272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 945216 # Number of bytes read from this memory +system.physmem.bytes_read::total 1001472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 2560 # Number of bytes written to this memory +system.physmem.bytes_written::total 2560 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14769 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15648 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 40 # Number of write requests responded to by this memory +system.physmem.num_writes::total 40 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2607990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2763208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7063 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7063 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2607990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2770272 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.numCycles 724861774 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 244421512 # nu system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55857.142857 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55857.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 46620000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 935475 # number of replacements system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use @@ -160,15 +185,25 @@ system.cpu.dcache.demand_accesses::total 105122385 # nu system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.502082 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14660.150899 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14660.150899 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,15 +235,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.502082 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 865 # number of replacements system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use @@ -273,18 +318,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 939571 system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001210 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016639 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016639 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,18 +372,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001210 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016639 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016639 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 7dd036543..5c8d95ce9 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:14:48 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 2d4c91c54..a6e1946c5 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.067388 # Nu sim_ticks 67388458000 # Number of ticks simulated final_tick 67388458000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74550 # Simulator instruction rate (inst/s) -host_op_rate 131270 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31798513 # Simulator tick rate (ticks/s) -host_mem_usage 385908 # Number of bytes of host memory used -host_seconds 2119.23 # Real time elapsed on the host +host_inst_rate 84988 # Simulator instruction rate (inst/s) +host_op_rate 149650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36250631 # Simulator tick rate (ticks/s) +host_mem_usage 363056 # Number of bytes of host memory used +host_seconds 1858.96 # Real time elapsed on the host sim_insts 157988582 # Number of instructions simulated sim_ops 278192519 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 3907520 # Number of bytes read from this memory -system.physmem.bytes_inst_read 69248 # Number of instructions bytes read from this memory -system.physmem.bytes_written 897536 # Number of bytes written to this memory -system.physmem.num_reads 61055 # Number of read requests responded to by this memory -system.physmem.num_writes 14024 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 57985004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1027594 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 13318839 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 71303843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 69248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3838272 # Number of bytes read from this memory +system.physmem.bytes_read::total 3907520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 69248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 69248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 897536 # Number of bytes written to this memory +system.physmem.bytes_written::total 897536 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 59973 # Number of read requests responded to by this memory +system.physmem.num_reads::total 61055 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 14024 # Number of write requests responded to by this memory +system.physmem.num_writes::total 14024 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1027594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 56957410 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 57985004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1027594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1027594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 13318839 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13318839 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 13318839 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1027594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 56957410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 71303843 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 134776917 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -323,11 +336,17 @@ system.cpu.icache.demand_accesses::total 27278821 # nu system.cpu.icache.overall_accesses::cpu.inst 27278821 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 27278821 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35528.308563 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35528.308563 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 35528.308563 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35528.308563 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 35528.308563 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35528.308563 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -355,11 +374,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 38330500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38330500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 38330500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34909.380692 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34909.380692 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34909.380692 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34909.380692 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34909.380692 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34909.380692 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2072128 # number of replacements system.cpu.dcache.tagsinuse 4072.706371 # Cycle average of tags in use @@ -403,13 +428,21 @@ system.cpu.dcache.demand_accesses::total 78000448 # nu system.cpu.dcache.overall_accesses::cpu.data 78000448 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 78000448 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049205 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049205 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002736 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002736 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.030475 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.030475 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.030475 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.030475 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6031.763813 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 6031.763813 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17468.488873 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17468.488873 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 6445.578990 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 6445.578990 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 6445.578990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 6445.578990 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -445,13 +478,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 6755035291 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6755035291 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6755035291 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.042829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026618 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026618 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2806.348172 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2806.348172 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14114.884540 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14114.884540 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3253.508541 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 3253.508541 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3253.508541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 3253.508541 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 33429 # number of replacements system.cpu.l2cache.tagsinuse 18994.164700 # Cycle average of tags in use @@ -522,19 +563,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 2076226 system.cpu.l2cache.overall_accesses::total 2077320 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.989031 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.015273 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015807 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.800000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.800000 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358999 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.358999 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.989031 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.028886 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.029391 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.989031 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.028886 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.029391 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34274.491682 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34158.052865 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34162.047753 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.473271 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34085.473271 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34274.491682 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34122.330049 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34125.026615 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34274.491682 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34122.330049 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34125.026615 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,20 +623,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1859866500 system.cpu.l2cache.overall_mshr_miss_latency::total 1893481500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015273 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015807 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358999 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358999 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028886 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.029391 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028886 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.029391 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31067.467652 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.604170 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31022.212005 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.574700 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.574700 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31067.467652 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31011.730279 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31012.718041 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31067.467652 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31011.730279 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31012.718041 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout index 8772b21f0..9f1b85cdf 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:20:09 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 09f40044d..75d2c32b9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.168950 # Nu sim_ticks 168950072000 # Number of ticks simulated final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 563497 # Simulator instruction rate (inst/s) -host_op_rate 992227 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 602592819 # Simulator tick rate (ticks/s) -host_mem_usage 374808 # Number of bytes of host memory used -host_seconds 280.37 # Real time elapsed on the host +host_inst_rate 1244063 # Simulator instruction rate (inst/s) +host_op_rate 2190595 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1330377575 # Simulator tick rate (ticks/s) +host_mem_usage 351912 # Number of bytes of host memory used +host_seconds 126.99 # Real time elapsed on the host sim_insts 157988583 # Number of instructions simulated sim_ops 278192520 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 2458815679 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1741569664 # Number of instructions bytes read from this memory -system.physmem.bytes_written 243173115 # Number of bytes written to this memory -system.physmem.num_reads 308475658 # Number of read requests responded to by this memory -system.physmem.num_writes 31439751 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 14553504772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 10308191310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1439319393 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 15992824164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 1741569664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 717246015 # Number of bytes read from this memory +system.physmem.bytes_read::total 2458815679 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1741569664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1741569664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 243173115 # Number of bytes written to this memory +system.physmem.bytes_written::total 243173115 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 217696208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 90779450 # Number of read requests responded to by this memory +system.physmem.num_reads::total 308475658 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 31439751 # Number of write requests responded to by this memory +system.physmem.num_writes::total 31439751 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 10308191310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4245313462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14553504772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10308191310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10308191310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1439319393 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1439319393 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10308191310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5684632854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15992824164 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 337900145 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index 3e731c17d..d95343c19 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:22:27 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 093a41c03..bcdb996d9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.370011 # Nu sim_ticks 370010840000 # Number of ticks simulated final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 376379 # Simulator instruction rate (inst/s) -host_op_rate 662743 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 881483751 # Simulator tick rate (ticks/s) -host_mem_usage 383736 # Number of bytes of host memory used -host_seconds 419.76 # Real time elapsed on the host +host_inst_rate 564351 # Simulator instruction rate (inst/s) +host_op_rate 993732 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1321716509 # Simulator tick rate (ticks/s) +host_mem_usage 360832 # Number of bytes of host memory used +host_seconds 279.95 # Real time elapsed on the host sim_insts 157988583 # Number of instructions simulated sim_ops 278192520 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 4900800 # Number of bytes read from this memory -system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory -system.physmem.bytes_written 1885440 # Number of bytes written to this memory -system.physmem.num_reads 76575 # Number of read requests responded to by this memory -system.physmem.num_writes 29460 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 13245017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 139758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5095634 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 18340652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4849088 # Number of bytes read from this memory +system.physmem.bytes_read::total 4900800 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 51712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 51712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 1885440 # Number of bytes written to this memory +system.physmem.bytes_written::total 1885440 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 808 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 75767 # Number of read requests responded to by this memory +system.physmem.num_reads::total 76575 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 29460 # Number of write requests responded to by this memory +system.physmem.num_writes::total 29460 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 139758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13105259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13245017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 139758 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 139758 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5095634 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5095634 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5095634 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 139758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13105259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18340652 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 740021680 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 217696209 # nu system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 42824000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2062733 # number of replacements system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use @@ -152,13 +177,21 @@ system.cpu.dcache.demand_accesses::total 122219201 # nu system.cpu.dcache.overall_accesses::cpu.data 122219201 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 122219201 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14713.502183 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30805.991952 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15539.675029 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15539.675029 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,13 +219,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 25917362500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25917362500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 25917362500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11713.502183 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11713.502183 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27805.977815 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27805.977815 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 49212 # number of replacements system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use @@ -254,18 +295,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 2066829 system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.016988 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.017393 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.400136 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.400136 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.036659 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.037035 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.036659 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.037035 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.694804 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.694804 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.385243 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.385243 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -300,18 +349,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3030680000 system.cpu.l2cache.overall_mshr_miss_latency::total 3063000000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.016988 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017393 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.400136 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.400136 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.037035 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.037035 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |