diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref')
9 files changed, 610 insertions, 595 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index a0763b2c7..9dfc48f3b 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -157,8 +159,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -430,16 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -461,8 +465,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -471,16 +475,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=false -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=2097152 subblock_size=0 system=system @@ -507,14 +513,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -530,13 +536,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 48d145b85..62518a9bb 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:39:45 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 11:53:48 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 28553466500 because target called exit() +Exiting @ tick 28505597000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 757fbcd2c..1a08f1a5c 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.028553 # Number of seconds simulated -sim_ticks 28553466500 # Number of ticks simulated -final_tick 28553466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.028506 # Number of seconds simulated +sim_ticks 28505597000 # Number of ticks simulated +final_tick 28505597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181848 # Simulator instruction rate (inst/s) -host_op_rate 183154 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57311644 # Simulator tick rate (ticks/s) -host_mem_usage 367800 # Number of bytes of host memory used -host_seconds 498.21 # Real time elapsed on the host +host_inst_rate 145688 # Simulator instruction rate (inst/s) +host_op_rate 146734 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45838175 # Simulator tick rate (ticks/s) +host_mem_usage 362080 # Number of bytes of host memory used +host_seconds 621.87 # Real time elapsed on the host sim_insts 90599368 # Number of instructions simulated sim_ops 91249921 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory -system.physmem.bytes_read::total 992896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45312 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 708 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1586918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33186303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34773221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1586918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1586918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1586918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33186303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 34773221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 45568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory +system.physmem.bytes_read::total 993216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45568 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 712 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15519 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1598563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33244278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34842842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1598563 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1598563 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1598563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33244278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 34842842 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,320 +70,320 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 57106934 # number of cpu cycles simulated +system.cpu.numCycles 57011195 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 27012699 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22277532 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 889694 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11653286 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11426819 # Number of BTB hits +system.cpu.BPredUnit.lookups 27014403 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22277078 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 889929 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11548760 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11430884 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 72452 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 358 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14542606 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 129803697 # Number of instructions fetch has processed -system.cpu.fetch.Branches 27012699 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11499271 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24399920 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5015488 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 14039908 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 73122 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 372 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14508892 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 129672886 # Number of instructions fetch has processed +system.cpu.fetch.Branches 27014403 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11504006 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24367767 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4991272 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 14021743 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14144138 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 347071 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 57042317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.294103 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.179417 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 14122126 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 347107 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 56945823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.293943 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.179113 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 32680363 57.29% 57.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3435885 6.02% 63.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2022812 3.55% 66.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1588688 2.79% 69.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1698003 2.98% 72.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3014546 5.28% 77.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1479172 2.59% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1109191 1.94% 82.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10013657 17.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 32616008 57.28% 57.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3437208 6.04% 63.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2033940 3.57% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1577922 2.77% 69.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1684600 2.96% 72.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3016320 5.30% 77.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1478308 2.60% 80.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1110359 1.95% 82.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9991158 17.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 57042317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.473020 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.272994 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17762369 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 11471319 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22339470 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1418238 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4050921 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4486769 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 9087 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 127953392 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42856 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4050921 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19506799 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5508085 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 206847 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21544530 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6225135 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 124612804 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1000 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 540301 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4835980 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 10850 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 145164650 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 542855215 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 542847680 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7535 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 56945823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.473844 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.274516 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17727827 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11442534 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22314035 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1422886 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4038541 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4486849 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8989 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 127753929 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42812 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4038541 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19463622 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5507295 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 178125 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21532560 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6225680 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 124585344 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1117 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 540744 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4833961 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 11275 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 145162652 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 542774349 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 542766580 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7769 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107429498 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37735152 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18216 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18214 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 14341922 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29837938 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5556896 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2142306 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1236219 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 119143027 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22051 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105690693 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78779 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27699280 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68606056 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 11919 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 57042317 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.852847 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.854849 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 37733154 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6541 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6539 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 14204519 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29836795 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5560829 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2097523 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1243222 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 119152184 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 10385 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105702713 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79311 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27697349 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68611569 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 253 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 56945823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.856198 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.856170 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17381718 30.47% 30.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13049544 22.88% 53.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8518143 14.93% 68.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6991208 12.26% 80.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5292177 9.28% 89.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2744999 4.81% 94.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2144277 3.76% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 490134 0.86% 99.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 430117 0.75% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17311609 30.40% 30.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13029602 22.88% 53.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8527913 14.98% 68.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6948954 12.20% 80.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5271164 9.26% 89.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2793517 4.91% 94.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2152448 3.78% 98.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 481434 0.85% 99.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 429182 0.75% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 57042317 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 56945823 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 40944 6.13% 6.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 349072 52.27% 58.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 277751 41.59% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 40477 6.05% 6.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 349114 52.21% 58.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 279085 41.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74708862 70.69% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10518 0.01% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 221 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 275 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74715129 70.68% 70.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10969 0.01% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 226 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 287 0.00% 70.70% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 70.70% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25829491 24.44% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5141321 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25832645 24.44% 95.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5143450 4.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105690693 # Type of FU issued -system.cpu.iq.rate 1.850751 # Inst issue rate -system.cpu.iq.fu_busy_cnt 667794 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006318 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 269169203 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 146866507 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102954305 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1073 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1626 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 453 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106357959 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 528 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 425504 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105702713 # Type of FU issued +system.cpu.iq.rate 1.854069 # Inst issue rate +system.cpu.iq.fu_busy_cnt 668703 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006326 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 269098152 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 146861999 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102960296 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1111 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1652 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 475 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106370866 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 550 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 430808 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7262058 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7178 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4608 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 810138 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7260915 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7599 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4486 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 814071 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 165527 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 165011 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4050921 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 893670 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 117044 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 119201460 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 342636 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29837938 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5556896 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18147 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49262 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15777 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4608 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 477903 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 486113 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 964016 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104633146 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25499061 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1057547 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4038541 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 891747 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 116973 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 119175285 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 342275 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29836795 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5560829 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6480 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49074 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15714 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4486 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 478618 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 473981 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 952599 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104642381 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25500898 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1060332 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 36382 # number of nop insts executed -system.cpu.iew.exec_refs 30575453 # number of memory reference insts executed -system.cpu.iew.exec_branches 21352915 # Number of branches executed -system.cpu.iew.exec_stores 5076392 # Number of stores executed -system.cpu.iew.exec_rate 1.832232 # Inst execution rate -system.cpu.iew.wb_sent 103240911 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102954758 # cumulative count of insts written-back -system.cpu.iew.wb_producers 61949538 # num instructions producing a value -system.cpu.iew.wb_consumers 102898807 # num instructions consuming a value +system.cpu.iew.exec_nop 12716 # number of nop insts executed +system.cpu.iew.exec_refs 30579562 # number of memory reference insts executed +system.cpu.iew.exec_branches 21366362 # Number of branches executed +system.cpu.iew.exec_stores 5078664 # Number of stores executed +system.cpu.iew.exec_rate 1.835471 # Inst execution rate +system.cpu.iew.wb_sent 103249709 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102960771 # cumulative count of insts written-back +system.cpu.iew.wb_producers 61941288 # num instructions producing a value +system.cpu.iew.wb_consumers 102916553 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.802842 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.602043 # average fanout of values written-back +system.cpu.iew.wb_rate 1.805975 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.601859 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 27941572 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 27915285 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10132 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 892650 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 52991397 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.722214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.475842 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 881077 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 52907283 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.724952 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.476924 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23013346 43.43% 43.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13498664 25.47% 68.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4267920 8.05% 76.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3605539 6.80% 83.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1555941 2.94% 86.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 706178 1.33% 88.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 916105 1.73% 89.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 261507 0.49% 90.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5166197 9.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22917585 43.32% 43.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13525297 25.56% 68.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4253401 8.04% 76.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3602316 6.81% 83.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1554565 2.94% 86.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 724715 1.37% 88.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 894547 1.69% 89.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 264490 0.50% 90.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5170367 9.77% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 52991397 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 52907283 # Number of insts commited each cycle system.cpu.commit.committedInsts 90611977 # Number of instructions committed system.cpu.commit.committedOps 91262530 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 27322638 # Number of memory references committed system.cpu.commit.loads 22575880 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722474 # Number of branches committed +system.cpu.commit.branches 18734218 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72533330 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5166197 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5170367 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 167023568 # The number of ROB reads -system.cpu.rob.rob_writes 242480145 # The number of ROB writes -system.cpu.timesIdled 16985 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64617 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 166908997 # The number of ROB reads +system.cpu.rob.rob_writes 242415249 # The number of ROB writes +system.cpu.timesIdled 17140 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 65372 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90599368 # Number of Instructions Simulated system.cpu.committedOps 91249921 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90599368 # Number of Instructions Simulated -system.cpu.cpi 0.630324 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.630324 # CPI: Total CPI of All Threads -system.cpu.ipc 1.586486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.586486 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 497500268 # number of integer regfile reads -system.cpu.int_regfile_writes 120842597 # number of integer regfile writes -system.cpu.fp_regfile_reads 229 # number of floating regfile reads -system.cpu.fp_regfile_writes 593 # number of floating regfile writes -system.cpu.misc_regfile_reads 183620284 # number of misc regfile reads +system.cpu.cpi 0.629267 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.629267 # CPI: Total CPI of All Threads +system.cpu.ipc 1.589150 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.589150 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 497539806 # number of integer regfile reads +system.cpu.int_regfile_writes 120848373 # number of integer regfile writes +system.cpu.fp_regfile_reads 239 # number of floating regfile reads +system.cpu.fp_regfile_writes 624 # number of floating regfile writes +system.cpu.misc_regfile_reads 183493284 # number of misc regfile reads system.cpu.misc_regfile_writes 11612 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 638.455928 # Cycle average of tags in use -system.cpu.icache.total_refs 14143171 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 734 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19268.625341 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 636.231301 # Cycle average of tags in use +system.cpu.icache.total_refs 14121140 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 738 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 19134.336043 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 638.455928 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.311746 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.311746 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14143171 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14143171 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14143171 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14143171 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14143171 # number of overall hits -system.cpu.icache.overall_hits::total 14143171 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 967 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 967 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 967 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 967 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 967 # number of overall misses -system.cpu.icache.overall_misses::total 967 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 35020500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 35020500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 35020500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 35020500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 35020500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 35020500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14144138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14144138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14144138 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14144138 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14144138 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14144138 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000068 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000068 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000068 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000068 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000068 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000068 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36215.615305 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36215.615305 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36215.615305 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36215.615305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36215.615305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36215.615305 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 636.231301 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.310660 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.310660 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14121140 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14121140 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14121140 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14121140 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14121140 # number of overall hits +system.cpu.icache.overall_hits::total 14121140 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 986 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 986 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 986 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 986 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 986 # number of overall misses +system.cpu.icache.overall_misses::total 986 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 35670500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 35670500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 35670500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 35670500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 35670500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 35670500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14122126 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14122126 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14122126 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14122126 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14122126 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14122126 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36176.977688 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36176.977688 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36176.977688 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36176.977688 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36176.977688 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36176.977688 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,246 +392,246 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 233 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 233 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 233 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 233 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 233 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 233 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 734 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26444000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26444000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26444000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26444000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26444000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26444000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 738 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 738 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 738 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 738 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 738 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 738 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26658000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26658000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26658000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26658000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26658000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26658000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36027.247956 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36027.247956 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36027.247956 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36027.247956 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36027.247956 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36027.247956 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36121.951220 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36121.951220 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36121.951220 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36121.951220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36121.951220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36121.951220 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943512 # number of replacements -system.cpu.dcache.tagsinuse 3689.791275 # Cycle average of tags in use -system.cpu.dcache.total_refs 28381642 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947608 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.950826 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8154700000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3689.791275 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.900828 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.900828 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23801988 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23801988 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4567984 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4567984 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5869 # 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number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4568472 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5862 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5862 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5801 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5801 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28369972 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28369972 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28369972 # number of overall hits -system.cpu.dcache.overall_hits::total 28369972 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1060525 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1060525 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 166997 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 166997 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28366732 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28366732 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28366732 # number of overall hits +system.cpu.dcache.overall_hits::total 28366732 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1060889 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1060889 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 166509 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 166509 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1227522 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1227522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1227522 # number of overall misses -system.cpu.dcache.overall_misses::total 1227522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 21965060500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 21965060500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6217004264 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6217004264 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 153500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 153500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28182064764 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28182064764 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28182064764 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28182064764 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24862513 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24862513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1227398 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1227398 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1227398 # number of overall misses +system.cpu.dcache.overall_misses::total 1227398 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 21973475500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 21973475500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6211010261 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6211010261 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 161000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 161000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28184485761 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28184485761 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28184485761 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28184485761 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24859149 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24859149 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5877 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5877 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5870 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5870 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5801 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29597494 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29597494 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29597494 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29597494 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042656 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.042656 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.035269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.035269 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001361 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001361 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 29594130 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29594130 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29594130 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29594130 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042676 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.042676 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.035166 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.035166 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001363 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001363 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.041474 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.041474 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.041474 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.041474 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.497136 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.497136 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37228.239214 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37228.239214 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22958.500755 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22958.500755 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22958.500755 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22958.500755 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 78852438 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20712.322873 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20712.322873 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37301.348642 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37301.348642 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20125 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20125 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22962.792640 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22962.792640 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22962.792640 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22962.792640 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 78891432 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9147 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9153 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8620.579206 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8619.188463 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942869 # number of writebacks -system.cpu.dcache.writebacks::total 942869 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 148009 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 148009 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131905 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 131905 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942894 # number of writebacks +system.cpu.dcache.writebacks::total 942894 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 148366 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 148366 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131394 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 131394 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 279914 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 279914 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 279914 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 279914 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 912516 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 912516 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 35092 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 35092 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947608 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947608 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947608 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947608 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16755802500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16755802500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1751499399 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1751499399 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18507301899 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18507301899 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18507301899 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18507301899 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036702 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036702 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007411 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007411 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032016 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032016 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032016 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18362.201320 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18362.201320 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49911.643651 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49911.643651 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19530.546280 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19530.546280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19530.546280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19530.546280 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 279760 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 279760 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 279760 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 279760 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 912523 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 912523 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 35115 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 35115 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947638 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947638 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947638 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947638 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16758552000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16758552000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1752488893 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1752488893 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18511040893 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18511040893 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18511040893 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18511040893 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036708 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036708 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007416 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007416 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032021 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032021 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032021 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032021 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18365.073538 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18365.073538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49907.130656 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49907.130656 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.873581 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.873581 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.873581 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.873581 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 10958.956435 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1839863 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15497 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 118.723818 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 10969.237336 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1839897 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15502 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 118.687718 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10102.128367 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 622.173685 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 234.654384 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.308292 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.018987 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007161 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.334441 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 10112.492667 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 621.566782 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 235.177887 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.308609 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.018969 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.007177 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.334755 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 912088 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 912112 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942869 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942869 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 20704 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 20704 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 912096 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 912120 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942894 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942894 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 20725 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 20725 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932792 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932816 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932821 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932845 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932792 # number of overall hits -system.cpu.l2cache.overall_hits::total 932816 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 710 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 281 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 991 # number of ReadReq misses +system.cpu.l2cache.overall_hits::cpu.data 932821 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34385.173719 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35759.103641 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.890194 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34491.951581 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35759.103641 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.890194 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34491.951581 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,50 +649,50 @@ system.cpu.l2cache.demand_mshr_hits::total 12 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 12 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 708 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 979 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 712 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 984 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14535 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14535 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 708 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14806 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 712 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15519 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 712 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15519 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9198500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32438500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 453435000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 453435000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462633500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 485873500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23240000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462633500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 485873500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001078 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412223 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412223 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964578 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32607.344633 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33704.797048 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32911.133810 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31196.353629 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31196.353629 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32607.344633 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31242.266649 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31304.563620 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32607.344633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31242.266649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31304.563620 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016364 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32640.449438 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33818.014706 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32965.955285 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31196.078431 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31196.078431 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32640.449438 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31244.242588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31308.299504 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32640.449438 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31244.242588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31308.299504 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 0837df787..c70c9e062 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,8 +68,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -84,8 +84,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -95,14 +95,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -117,14 +117,15 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout index f567cacf4..fa062edc0 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:44:35 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 14:03:25 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 6111a0118..42f3c00f3 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu sim_ticks 54240661000 # Number of ticks simulated final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3184418 # Simulator instruction rate (inst/s) -host_op_rate 3207282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1906403630 # Simulator tick rate (ticks/s) -host_mem_usage 357244 # Number of bytes of host memory used -host_seconds 28.45 # Real time elapsed on the host +host_inst_rate 2374877 # Simulator instruction rate (inst/s) +host_op_rate 2391929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1421759359 # Simulator tick rate (ticks/s) +host_mem_usage 351688 # Number of bytes of host memory used +host_seconds 38.15 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91252960 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory @@ -84,7 +84,7 @@ system.cpu.committedOps 91252960 # Nu system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15548925 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls system.cpu.num_int_insts 72525674 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_int_register_reads 396912478 # number of times the integer registers were read diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index 172c79802..9c2aed7c6 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,16 +61,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -89,8 +91,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -99,16 +101,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -130,8 +134,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -140,16 +144,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=2097152 subblock_size=0 system=system @@ -176,14 +182,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -199,13 +205,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout index 092850ece..364027fbc 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:40:44 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:45:02 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 4b16c09c3..3cd60c7e5 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.148268 # Nu sim_ticks 148267705000 # Number of ticks simulated final_tick 148267705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1021914 # Simulator instruction rate (inst/s) -host_op_rate 1029241 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1672798092 # Simulator tick rate (ticks/s) -host_mem_usage 365748 # Number of bytes of host memory used -host_seconds 88.63 # Real time elapsed on the host +host_inst_rate 1153616 # Simulator instruction rate (inst/s) +host_op_rate 1161887 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1888384270 # Simulator tick rate (ticks/s) +host_mem_usage 360564 # Number of bytes of host memory used +host_seconds 78.52 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91226312 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory @@ -78,7 +78,7 @@ system.cpu.committedOps 91226312 # Nu system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15548925 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls system.cpu.num_int_insts 72525674 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_int_register_reads 464563355 # number of times the integer registers were read |