diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref')
5 files changed, 1132 insertions, 1102 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 8f24165d3..2f7887688 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.061241 # Number of seconds simulated -sim_ticks 61240850500 # Number of ticks simulated -final_tick 61240850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 61241011500 # Number of ticks simulated +final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182783 # Simulator instruction rate (inst/s) -host_op_rate 183693 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 123547949 # Simulator tick rate (ticks/s) -host_mem_usage 442472 # Number of bytes of host memory used -host_seconds 495.69 # Real time elapsed on the host +host_inst_rate 252391 # Simulator instruction rate (inst/s) +host_op_rate 253648 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 170598134 # Simulator tick rate (ticks/s) +host_mem_usage 450980 # Number of bytes of host memory used +host_seconds 358.98 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49536 # Nu system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 808872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15466800 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16275672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 808872 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 808872 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 808872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15466800 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16275672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 808870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15466760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16275629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 808870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 808870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 808870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15466760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16275629 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61240757000 # Total gap between requests +system.physmem.totGap 61240917000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 644.601036 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 438.502120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 402.393837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 247 16.00% 16.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 189 12.24% 28.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 92 5.96% 34.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 4.40% 38.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 69 4.47% 43.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 87 5.63% 48.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 40 2.59% 51.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 47 3.04% 54.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 705 45.66% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation -system.physmem.totQLat 73458500 # Total ticks spent queuing -system.physmem.totMemAccLat 365471000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1543 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 644.935839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 438.870546 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 402.302511 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 247 16.01% 16.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 187 12.12% 28.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 93 6.03% 34.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 68 4.41% 38.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 69 4.47% 43.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 87 5.64% 48.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 40 2.59% 51.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 47 3.05% 54.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 705 45.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1543 # Bytes accessed per row activation +system.physmem.totQLat 73241750 # Total ticks spent queuing +system.physmem.totMemAccLat 365254250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4716.74 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4702.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23466.74 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23452.82 # Average memory access latency per DRAM burst system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s @@ -220,35 +220,35 @@ system.physmem.readRowHits 14026 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.06 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3932243.29 # Average gap between requests +system.physmem.avgGap 3932253.56 # Average gap between requests system.physmem.pageHitRate 90.06 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 6305040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3440250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63780600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2494978920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34554891750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41123220960 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.518851 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57475186750 # Time in different power states +system.physmem_0.actBackEnergy 2491477695 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34557963000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41122783185 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.511702 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57480391250 # Time in different power states system.physmem_0.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1719043250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1713925750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5367600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2928750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57517200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5360040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2924625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2555622360 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34501695750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41122956060 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.514525 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57387265750 # Time in different power states +system.physmem_1.actBackEnergy 2555146980 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34502112750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41122878195 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.513254 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57387655250 # Time in different power states system.physmem_1.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1807269750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1806574750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 20752188 # Number of BP lookups system.cpu.branchPred.condPredicted 17062075 # Number of conditional branches predicted @@ -377,29 +377,29 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 122481701 # number of cpu cycles simulated +system.cpu.numCycles 122482023 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2176622 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2176623 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.351853 # CPI: cycles per instruction -system.cpu.ipc 0.739726 # IPC: instructions per cycle -system.cpu.tickCycles 109255125 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13226576 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.351856 # CPI: cycles per instruction +system.cpu.ipc 0.739724 # IPC: instructions per cycle +system.cpu.tickCycles 109255164 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13226859 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 946097 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.871508 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3616.872758 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26263183 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.639841 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 20511562500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.871508 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.883025 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.883025 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.872758 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.883026 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.883026 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2246 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 55455001 # Number of tag accesses @@ -428,14 +428,14 @@ system.cpu.dcache.demand_misses::cpu.data 989217 # n system.cpu.dcache.demand_misses::total 989217 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 989221 # number of overall misses system.cpu.dcache.overall_misses::total 989221 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918942500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11918942500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542548000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2542548000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14461490500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14461490500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14461490500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14461490500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919048000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11919048000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542627500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2542627500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14461675500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14461675500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14461675500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14461675500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22509137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22509137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -460,14 +460,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.036309 system.cpu.dcache.demand_miss_rate::total 0.036309 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.220234 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.220234 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34224.172511 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34224.172511 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.128563 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14619.128563 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.069450 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14619.069450 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.335544 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.335544 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.242627 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.242627 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.315580 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14619.315580 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.256465 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14619.256465 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -496,16 +496,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950190 system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865257500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865257500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481584500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481584500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865351000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865351000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481616500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481616500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346842000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12346842000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346998500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12346998500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346967500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12346967500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347124000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12347124000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040136 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040136 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -516,69 +516,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034877 system.cpu.dcache.demand_mshr_miss_rate::total 0.034877 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034876 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.739906 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.739906 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31681.481877 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31681.481877 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.843401 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.843401 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.166150 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.166150 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.076974 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.076974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.200652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.200652 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.209053 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.209053 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.332730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.332730 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 689.439690 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27770466 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 689.439811 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27770468 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34626.516209 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34626.518703 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 689.439690 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.336640 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.336640 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 689.439811 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.336641 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.336641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55543338 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55543338 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27770466 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27770466 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27770466 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27770466 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27770466 # number of overall hits -system.cpu.icache.overall_hits::total 27770466 # number of overall hits +system.cpu.icache.tags.tag_accesses 55543342 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55543342 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27770468 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27770468 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27770468 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27770468 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27770468 # number of overall hits +system.cpu.icache.overall_hits::total 27770468 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60107000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60107000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60107000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60107000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60107000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60107000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27771268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27771268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27771268 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27771268 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27771268 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27771268 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 59898000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 59898000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 59898000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 59898000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 59898000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 59898000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27771270 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27771270 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27771270 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27771270 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27771270 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27771270 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74946.384040 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74946.384040 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74946.384040 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74946.384040 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74685.785536 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74685.785536 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74685.785536 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74685.785536 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,38 +593,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59305000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59305000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59305000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59305000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59305000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59305000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59096000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59096000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59096000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59096000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59096000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59096000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73946.384040 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73946.384040 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73685.785536 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73685.785536 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10245.543243 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 10245.556298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1833992 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 117.888539 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9355.642515 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444420 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456307 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655412 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444539 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456347 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.285512 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020582 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312669 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312670 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id @@ -660,18 +660,18 @@ system.cpu.l2cache.demand_misses::total 15582 # nu system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses system.cpu.l2cache.overall_misses::total 15582 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067640500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1067640500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57828000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 57828000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21914500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 21914500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 57828000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1089555000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1147383000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 57828000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1089555000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1147383000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067673500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1067673500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57597000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 57597000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21897000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21897000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 57597000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1089570500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1147167500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 57597000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1089570500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1147167500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 943278 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 943278 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46765 # number of ReadExReq accesses(hits+misses) @@ -698,18 +698,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016385 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.625138 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.625138 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74520.618557 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74520.618557 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83643.129771 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83643.129771 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73635.155949 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73635.155949 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.894114 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.894114 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73621.325889 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73621.325889 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,18 +740,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922200500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922200500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49941000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49941000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18963500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18963500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49941000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941164000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 991105000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49941000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941164000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 991105000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49710000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49710000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18946000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18946000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49710000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941179500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 990889500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49710000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941179500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 990889500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311002 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311002 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses @@ -764,19 +764,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63407.625138 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63407.625138 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64523.255814 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64523.255814 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74076.171875 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74076.171875 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.894114 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.894114 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1897097 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 943278 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2674 # Transaction distribution @@ -792,14 +798,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 121233472 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1897097 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012905 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1897097 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1896781 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 316 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1897097 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1891826500 # Layer occupancy (ticks) @@ -827,9 +833,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21739500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21741000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82130500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82130750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 6f66b7dfa..6db072c1c 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,113 +1,113 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058182 # Number of seconds simulated -sim_ticks 58182114500 # Number of ticks simulated -final_tick 58182114500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058181 # Number of seconds simulated +sim_ticks 58181475500 # Number of ticks simulated +final_tick 58181475500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128679 # Simulator instruction rate (inst/s) -host_op_rate 129320 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 82645168 # Simulator tick rate (ticks/s) -host_mem_usage 446228 # Number of bytes of host memory used -host_seconds 704.00 # Real time elapsed on the host +host_inst_rate 122946 # Simulator instruction rate (inst/s) +host_op_rate 123559 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78962453 # Simulator tick rate (ticks/s) +host_mem_usage 448784 # Number of bytes of host memory used +host_seconds 736.82 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 51456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 933184 # Number of bytes read from this memory -system.physmem.bytes_read::total 1028928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44288 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 27456 # Number of bytes written to this memory -system.physmem.bytes_written::total 27456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 692 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14581 # Number of read requests responded to by this memory -system.physmem.num_reads::total 16077 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 429 # Number of write requests responded to by this memory -system.physmem.num_writes::total 429 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 761196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 884395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 16039018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17684610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 761196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 761196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 471898 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 471898 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 471898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 761196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 884395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 16039018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18156508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 16077 # Number of read requests accepted -system.physmem.writeReqs 429 # Number of write requests accepted -system.physmem.readBursts 16077 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 429 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1014080 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 14848 # Total number of bytes read from write queue -system.physmem.bytesWritten 26048 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1028928 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 27456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 232 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 50176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 933312 # Number of bytes read from this memory +system.physmem.bytes_read::total 1027904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 28672 # Number of bytes written to this memory +system.physmem.bytes_written::total 28672 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14583 # Number of read requests responded to by this memory +system.physmem.num_reads::total 16061 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 448 # Number of write requests responded to by this memory +system.physmem.num_writes::total 448 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 763404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 862405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 16041394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17667204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 763404 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 763404 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 492803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 492803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 492803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 763404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 862405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 16041394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18160007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 16061 # Number of read requests accepted +system.physmem.writeReqs 448 # Number of write requests accepted +system.physmem.readBursts 16061 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 448 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1014144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 13760 # Total number of bytes read from write queue +system.physmem.bytesWritten 26688 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1027904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 28672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 215 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1011 # Per bank write bursts +system.physmem.perBankRdBursts::0 1015 # Per bank write bursts system.physmem.perBankRdBursts::1 876 # Per bank write bursts -system.physmem.perBankRdBursts::2 957 # Per bank write bursts -system.physmem.perBankRdBursts::3 1029 # Per bank write bursts -system.physmem.perBankRdBursts::4 1060 # Per bank write bursts -system.physmem.perBankRdBursts::5 1137 # Per bank write bursts -system.physmem.perBankRdBursts::6 1146 # Per bank write bursts -system.physmem.perBankRdBursts::7 1099 # Per bank write bursts -system.physmem.perBankRdBursts::8 1049 # Per bank write bursts +system.physmem.perBankRdBursts::2 960 # Per bank write bursts +system.physmem.perBankRdBursts::3 1024 # Per bank write bursts +system.physmem.perBankRdBursts::4 1064 # Per bank write bursts +system.physmem.perBankRdBursts::5 1138 # Per bank write bursts +system.physmem.perBankRdBursts::6 1126 # Per bank write bursts +system.physmem.perBankRdBursts::7 1116 # Per bank write bursts +system.physmem.perBankRdBursts::8 1048 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 940 # Per bank write bursts -system.physmem.perBankRdBursts::11 901 # Per bank write bursts -system.physmem.perBankRdBursts::12 907 # Per bank write bursts -system.physmem.perBankRdBursts::13 888 # Per bank write bursts -system.physmem.perBankRdBursts::14 960 # Per bank write bursts -system.physmem.perBankRdBursts::15 923 # Per bank write bursts -system.physmem.perBankWrBursts::0 29 # Per bank write bursts +system.physmem.perBankRdBursts::10 947 # Per bank write bursts +system.physmem.perBankRdBursts::11 899 # Per bank write bursts +system.physmem.perBankRdBursts::12 909 # Per bank write bursts +system.physmem.perBankRdBursts::13 891 # Per bank write bursts +system.physmem.perBankRdBursts::14 939 # Per bank write bursts +system.physmem.perBankRdBursts::15 932 # Per bank write bursts +system.physmem.perBankWrBursts::0 39 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 8 # Per bank write bursts -system.physmem.perBankWrBursts::3 7 # Per bank write bursts -system.physmem.perBankWrBursts::4 4 # Per bank write bursts -system.physmem.perBankWrBursts::5 30 # Per bank write bursts -system.physmem.perBankWrBursts::6 102 # Per bank write bursts -system.physmem.perBankWrBursts::7 27 # Per bank write bursts -system.physmem.perBankWrBursts::8 34 # Per bank write bursts +system.physmem.perBankWrBursts::2 11 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 10 # Per bank write bursts +system.physmem.perBankWrBursts::5 33 # Per bank write bursts +system.physmem.perBankWrBursts::6 78 # Per bank write bursts +system.physmem.perBankWrBursts::7 51 # Per bank write bursts +system.physmem.perBankWrBursts::8 44 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 11 # Per bank write bursts -system.physmem.perBankWrBursts::11 5 # Per bank write bursts -system.physmem.perBankWrBursts::12 6 # Per bank write bursts -system.physmem.perBankWrBursts::13 38 # Per bank write bursts -system.physmem.perBankWrBursts::14 82 # Per bank write bursts -system.physmem.perBankWrBursts::15 24 # Per bank write bursts +system.physmem.perBankWrBursts::10 13 # Per bank write bursts +system.physmem.perBankWrBursts::11 2 # Per bank write bursts +system.physmem.perBankWrBursts::12 8 # Per bank write bursts +system.physmem.perBankWrBursts::13 25 # Per bank write bursts +system.physmem.perBankWrBursts::14 64 # Per bank write bursts +system.physmem.perBankWrBursts::15 39 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58181957500 # Total gap between requests +system.physmem.totGap 58181318500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 16077 # Read request sizes (log2) +system.physmem.readPktSize::6 16061 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 429 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10965 # What read queue length does an incoming req see +system.physmem.writePktSize::6 448 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10962 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 2513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 299 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 275 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 295 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see @@ -148,26 +148,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -197,93 +197,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1937 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 535.822406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 300.454496 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 434.844935 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 623 32.16% 32.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 199 10.27% 42.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 99 5.11% 47.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 70 3.61% 51.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 49 2.53% 53.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 51 2.63% 56.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 51 2.63% 58.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 47 2.43% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 748 38.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1937 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1956 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.533742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 297.285521 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 435.040107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 621 31.75% 31.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 232 11.86% 43.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 86 4.40% 48.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 69 3.53% 51.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 49 2.51% 54.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 52 2.66% 56.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 53 2.71% 59.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 46 2.35% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 748 38.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1956 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 23 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 687.695652 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 31.373989 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3139.186163 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 686.869565 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 31.250235 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3138.483903 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-511 22 95.65% 95.65% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 4.35% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 23 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 23 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.695652 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.676543 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.822125 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4 17.39% 17.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18 78.26% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 4.35% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.130435 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.125203 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.457697 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 21 91.30% 91.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 4.35% 95.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 4.35% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 23 # Writes before turning the bus around for reads -system.physmem.totQLat 162696744 # Total ticks spent queuing -system.physmem.totMemAccLat 459790494 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 79225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10268.02 # Average queueing delay per DRAM burst +system.physmem.totQLat 162337192 # Total ticks spent queuing +system.physmem.totMemAccLat 459449692 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 79230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10244.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29018.02 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28994.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.45 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 17.68 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.47 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 0.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.67 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.49 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.47 # Average read queue length when enqueuing -system.physmem.avgWrQLen 18.75 # Average write queue length when enqueuing -system.physmem.readRowHits 14165 # Number of row buffer hits during reads -system.physmem.writeRowHits 138 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.72 # Average write queue length when enqueuing +system.physmem.readRowHits 14167 # Number of row buffer hits during reads +system.physmem.writeRowHits 131 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.47 # Row buffer hit rate for writes -system.physmem.avgGap 3524897.46 # Average gap between requests -system.physmem.pageHitRate 87.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7749000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 4228125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 64591800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1302480 # Energy for write commands per rank (pJ) +system.physmem.writeRowHitRate 29.57 # Row buffer hit rate for writes +system.physmem.avgGap 3524218.21 # Average gap between requests +system.physmem.pageHitRate 87.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7983360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4356000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 64662000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1438560 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2489657400 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32723562000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39091051125 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.908601 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54427806081 # Time in different power states +system.physmem_0.actBackEnergy 2503358775 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32711543250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39093302265 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.947294 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54407827569 # Time in different power states system.physmem_0.memoryStateTime::REF 1942720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1808607669 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1828586181 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6811560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3716625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 58687200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1211760 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 6788880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3704250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58663800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1263600 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2472306885 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32738773500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39081467850 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.744040 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54453180249 # Time in different power states +system.physmem_1.actBackEnergy 2462347845 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32747517750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39080246445 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.722887 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54468275483 # Time in different power states system.physmem_1.memoryStateTime::REF 1942720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1783438751 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1768727017 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 28257673 # Number of BP lookups -system.cpu.branchPred.condPredicted 23279792 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837861 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11842586 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11784928 # Number of BTB hits +system.cpu.branchPred.lookups 28257355 # Number of BP lookups +system.cpu.branchPred.condPredicted 23279453 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837859 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11842476 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11784812 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.513130 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75759 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.513075 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75760 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -403,83 +403,83 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 116364230 # number of cpu cycles simulated +system.cpu.numCycles 116362952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 748840 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134987137 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28257673 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11860687 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 114722877 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 748921 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134986415 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28257355 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11860572 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114720736 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1679131 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 833 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32301983 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116313064 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.165803 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.319035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 953 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 835 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32301690 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 580 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116311010 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.165818 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.319039 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58742008 50.50% 50.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13941997 11.99% 62.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9231022 7.94% 70.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34398037 29.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58740461 50.50% 50.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13941673 11.99% 62.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9230825 7.94% 70.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34398051 29.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116313064 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 116311010 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.242838 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.160040 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8839881 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64052748 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33035096 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9558012 # Number of cycles decode is unblocking +system.cpu.fetch.rate 1.160046 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8839998 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64050748 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33034874 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9558063 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 827327 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101304 # Number of times decode resolved a branch +system.cpu.decode.BranchResolved 4101313 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 12342 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114430189 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1996961 # Number of squashed instructions handled by decode +system.cpu.decode.DecodedInsts 114429656 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1996969 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 827327 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15280915 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49896712 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109420 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35425336 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14773354 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110898724 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1415582 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11131047 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1144428 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1527040 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 487812 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129956476 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483272365 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119474128 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 430 # Number of floating rename lookups +system.cpu.rename.IdleCycles 15281198 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49893829 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109582 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35425015 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14774059 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110898152 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1415674 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11131476 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1144261 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1527056 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 488175 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129955893 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483270095 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119473614 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 428 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22643557 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22642974 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21506605 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26812984 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5349507 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 517744 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 254125 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109690412 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21507084 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26812785 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5349554 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 517855 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 254082 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109689870 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101387626 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074735 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18657629 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41690294 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101387714 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074676 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18657087 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41688114 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116313064 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.871679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.989298 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 116311010 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989305 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54672209 47.00% 47.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31362113 26.96% 73.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008866 18.92% 92.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7072036 6.08% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197527 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54670243 47.00% 47.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31362294 26.96% 73.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22008143 18.92% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7072499 6.08% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197518 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -487,9 +487,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116313064 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116311010 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9793385 48.69% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9794091 48.69% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 50 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.69% # attempts to use FU when none available @@ -512,19 +512,19 @@ system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.69% # at system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 14 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9616432 47.81% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 703828 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9615955 47.81% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 703739 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71984128 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10709 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71984145 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued @@ -546,90 +546,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 53 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 52 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24343025 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5049584 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24343095 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049585 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101387626 # Type of FU issued -system.cpu.iq.rate 0.871295 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20113709 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198384 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340276307 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128356979 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99625202 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 453 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 112 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121501099 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 290480 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101387714 # Type of FU issued +system.cpu.iq.rate 0.871306 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20113848 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198385 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340274513 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128355901 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99625297 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 449 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 614 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 111 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121501328 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 234 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 290500 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4337073 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 4336874 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1516 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1343 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604663 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1345 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604710 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7562 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130598 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7564 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130574 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 827327 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8118752 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684481 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109711326 # Number of instructions dispatched to IQ +system.cpu.iew.iewBlockCycles 8118136 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684680 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109710785 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26812984 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5349507 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26812785 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5349554 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 179113 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 342349 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1343 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436660 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412872 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849532 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100126680 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23806374 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1260946 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 179049 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 342646 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1345 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436655 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412870 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849525 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100126849 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23806470 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1260865 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12667 # number of nop insts executed -system.cpu.iew.exec_refs 28724279 # number of memory reference insts executed -system.cpu.iew.exec_branches 20624229 # Number of branches executed -system.cpu.iew.exec_stores 4917905 # Number of stores executed -system.cpu.iew.exec_rate 0.860459 # Inst execution rate -system.cpu.iew.wb_sent 99709898 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99625314 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59703303 # num instructions producing a value -system.cpu.iew.wb_consumers 95544285 # num instructions consuming a value +system.cpu.iew.exec_nop 12668 # number of nop insts executed +system.cpu.iew.exec_refs 28724380 # number of memory reference insts executed +system.cpu.iew.exec_branches 20624234 # Number of branches executed +system.cpu.iew.exec_stores 4917910 # Number of stores executed +system.cpu.iew.exec_rate 0.860470 # Inst execution rate +system.cpu.iew.wb_sent 99710000 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99625408 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59703416 # num instructions producing a value +system.cpu.iew.wb_consumers 95544446 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.856151 # insts written-back per cycle +system.cpu.iew.wb_rate 0.856161 # insts written-back per cycle system.cpu.iew.wb_fanout 0.624876 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17385621 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17385130 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825623 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113620717 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.801382 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.737978 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825621 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113618734 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801396 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.737990 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77197638 67.94% 67.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18614899 16.38% 84.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7150727 6.29% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3466583 3.05% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1641577 1.44% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 544810 0.48% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 704355 0.62% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 179975 0.16% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4120153 3.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77195687 67.94% 67.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18614563 16.38% 84.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7151371 6.29% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3466253 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1641564 1.44% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 544784 0.48% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 704352 0.62% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 179993 0.16% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4120167 3.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113620717 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113618734 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -675,78 +675,78 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4120153 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 217934090 # The number of ROB reads -system.cpu.rob.rob_writes 219571457 # The number of ROB writes -system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 51166 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4120167 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 217931602 # The number of ROB reads +system.cpu.rob.rob_writes 219570402 # The number of ROB writes +system.cpu.timesIdled 589 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 51942 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.284518 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.284518 # CPI: Total CPI of All Threads -system.cpu.ipc 0.778502 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.778502 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108111423 # number of integer regfile reads -system.cpu.int_regfile_writes 58700979 # number of integer regfile writes -system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.cpi 1.284504 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284504 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778511 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778511 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108111563 # number of integer regfile reads +system.cpu.int_regfile_writes 58701013 # number of integer regfile writes +system.cpu.fp_regfile_reads 59 # number of floating regfile reads system.cpu.fp_regfile_writes 92 # number of floating regfile writes -system.cpu.cc_regfile_reads 369063033 # number of cc regfile reads -system.cpu.cc_regfile_writes 58693305 # number of cc regfile writes -system.cpu.misc_regfile_reads 28414934 # number of misc regfile reads +system.cpu.cc_regfile_reads 369063684 # number of cc regfile reads +system.cpu.cc_regfile_writes 58693489 # number of cc regfile writes +system.cpu.misc_regfile_reads 28414952 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.replacements 5470204 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.787652 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18251843 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5470716 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.336280 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 5470194 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.787648 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18251935 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5470706 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.336303 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 35373500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.787652 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.787648 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999585 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999585 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 357 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61908596 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61908596 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13889769 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13889769 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353793 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353793 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61908668 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61908668 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13889868 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13889868 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353786 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353786 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18243562 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18243562 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18244084 # number of overall hits -system.cpu.dcache.overall_hits::total 18244084 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9585887 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9585887 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381188 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381188 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18243654 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18243654 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18244176 # number of overall hits +system.cpu.dcache.overall_hits::total 18244176 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9585829 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9585829 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381195 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381195 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9967075 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9967075 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9967082 # number of overall misses -system.cpu.dcache.overall_misses::total 9967082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88721516500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88721516500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4007000296 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4007000296 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9967024 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9967024 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9967031 # number of overall misses +system.cpu.dcache.overall_misses::total 9967031 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88721011000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88721011000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4006916840 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4006916840 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92728516796 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92728516796 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92728516796 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92728516796 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23475656 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23475656 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 92727927840 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92727927840 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92727927840 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92727927840 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23475697 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23475697 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -755,100 +755,100 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28210637 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28210637 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28211166 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28211166 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408333 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408333 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080505 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080505 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28210678 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28210678 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28211207 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28211207 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408330 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408330 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080506 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080506 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353309 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353309 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353303 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353303 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9255.431083 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9255.431083 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10511.874183 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10511.874183 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.353307 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353307 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353300 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353300 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9255.434350 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9255.434350 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10511.462218 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10511.462218 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9303.483399 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9303.483399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9303.476865 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9303.476865 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 329940 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 111027 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121461 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.716427 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.648310 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9303.471913 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9303.471913 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9303.465379 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9303.465379 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 329844 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 111014 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121439 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12836 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.716129 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.648644 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5432438 # number of writebacks -system.cpu.dcache.writebacks::total 5432438 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337660 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4337660 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158703 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158703 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 5433212 # number of writebacks +system.cpu.dcache.writebacks::total 5433212 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337614 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4337614 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158708 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158708 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4496363 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4496363 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4496363 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4496363 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248227 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248227 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222485 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222485 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4496322 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4496322 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4496322 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4496322 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248215 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248215 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5470712 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5470712 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5470716 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5470716 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43248007500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43248007500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2284927222 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2284927222 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5470702 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5470702 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5470706 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5470706 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43247632500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43247632500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285123725 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285123725 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45532934722 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45532934722 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45533149222 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45533149222 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223560 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223560 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45532756225 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45532756225 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45532970725 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45532970725 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223559 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223559 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193924 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193924 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193923 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193920 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.193920 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.498648 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8240.498648 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.028191 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.028191 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.446037 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8240.446037 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.819082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.819082 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8323.036329 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8323.036329 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8323.069452 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8323.069452 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8323.018915 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8323.018915 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8323.052038 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8323.052038 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 451 # number of replacements -system.cpu.icache.tags.tagsinuse 428.507566 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32300812 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 428.507470 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32300517 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35495.397802 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 35495.073626 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 428.507566 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 428.507470 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.836929 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.836929 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id @@ -857,196 +857,196 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 51 system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64604850 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64604850 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32300812 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32300812 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32300812 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32300812 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32300812 # number of overall hits -system.cpu.icache.overall_hits::total 32300812 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses -system.cpu.icache.overall_misses::total 1158 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 61588984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 61588984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 61588984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 61588984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 61588984 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62258984 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62258984 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32301676 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32301676 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32301676 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32301676 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32301676 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32301676 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53185.651123 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53185.651123 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53185.651123 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53185.651123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53185.651123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53185.651123 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 19024 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 135 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53717.846419 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53717.846419 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53717.846419 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53717.846419 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53717.846419 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53717.846419 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 18998 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 136 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 221 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 84.551111 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 85.963801 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 27.200000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 249 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54796.140659 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54796.140659 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55268.118681 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55268.118681 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55268.118681 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55268.118681 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55268.118681 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55268.118681 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 4982376 # 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Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 16082 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 664.657257 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14074518 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 620 # number of replacements +system.cpu.l2cache.tags.tagsinuse 12071.188165 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 10691146 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 16060 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 665.700249 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11058.580214 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 574.634156 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 222.368326 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 10 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 238 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 22 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 224 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 966 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1062 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 971 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.762637 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000270 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.004056 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41019.803691 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41019.803691 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96347.507331 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96347.507331 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62579.479769 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62579.479769 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 56055.075594 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 56055.075594 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62579.479769 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73144.278607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68257.352941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62579.479769 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73144.278607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41019.803691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42855.849908 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.004061 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 40925.493009 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 40925.493009 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95749.271137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95749.271137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62990.634006 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62990.634006 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 56670.068027 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 56670.068027 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62990.634006 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73767.219388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68707.036536 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62990.634006 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73767.219388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 40925.493009 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42773.594608 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 5245116 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 5432867 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 35515 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 22583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226510 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 10942261 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470659 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 6201 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 6201 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 5245097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 5433660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 34692 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 22620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 910 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244187 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2259 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408733 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16410992 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408705 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16410964 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697801856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 697860096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 23225 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10965506 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.002118 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045973 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697850752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 697908992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 23240 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10965501 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001098 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.033119 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10942281 99.79% 99.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 23225 0.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10953460 99.89% 99.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12041 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10965506 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10903578500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10965501 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10904342500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1366996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1367495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206077992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206062992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 15736 # Transaction distribution -system.membus.trans_dist::Writeback 429 # Transaction distribution -system.membus.trans_dist::CleanEvict 169 # Transaction distribution -system.membus.trans_dist::ReadExReq 341 # Transaction distribution -system.membus.trans_dist::ReadExResp 341 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 15736 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32752 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32752 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1056384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1056384 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 15718 # Transaction distribution +system.membus.trans_dist::Writeback 448 # Transaction distribution +system.membus.trans_dist::CleanEvict 139 # Transaction distribution +system.membus.trans_dist::ReadExReq 343 # Transaction distribution +system.membus.trans_dist::ReadExResp 343 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 15718 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32709 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1056576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1056576 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 16675 # Request fanout histogram +system.membus.snoop_fanout::samples 16648 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16675 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 16648 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16675 # Request fanout histogram -system.membus.reqLayer0.occupancy 28309413 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 16648 # Request fanout histogram +system.membus.reqLayer0.occupancy 28374711 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 84107303 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 84025804 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 86fbc3533..8cbe9f760 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.361489 # Number of seconds simulated -sim_ticks 361488535500 # Number of ticks simulated -final_tick 361488535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 361488536500 # Number of ticks simulated +final_tick 361488536500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1224088 # Simulator instruction rate (inst/s) -host_op_rate 1224138 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1814798992 # Simulator tick rate (ticks/s) -host_mem_usage 426288 # Number of bytes of host memory used -host_seconds 199.19 # Real time elapsed on the host +host_inst_rate 1117046 # Simulator instruction rate (inst/s) +host_op_rate 1117092 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1656101101 # Simulator tick rate (ticks/s) +host_mem_usage 428664 # Number of bytes of host memory used +host_seconds 218.28 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -31,7 +31,7 @@ system.physmem.bw_total::cpu.data 2606821 # To system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 722977071 # number of cpu cycles simulated +system.cpu.numCycles 722977073 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 722977070.998000 # Number of busy cycles +system.cpu.num_busy_cycles 722977072.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.469039 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3562.469029 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134366268500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469039 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 134366269500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469029 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -126,16 +126,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613736000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11613736000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12832738000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12832738000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12832738000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12832738000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) @@ -156,16 +156,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.386401 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.386401 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13658.140399 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13658.140399 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,16 +186,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720878000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720878000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720879000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720879000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1172292000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1172292000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 90000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 90000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893170000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11893170000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893170000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11893170000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893171000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11893171000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893171000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11893171000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses @@ -206,24 +206,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.385281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.385281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.386401 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.386401 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22500 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.412974 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 725.412972 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.412974 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 725.412972 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id @@ -304,13 +304,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685 system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9730.625133 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9730.625106 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670093 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635586 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670068 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635584 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319455 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy @@ -458,6 +458,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 233 # Transaction distribution @@ -473,14 +479,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1875953 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.001033 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1875953 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1875951 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1875953 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1873242500 # Layer occupancy (ticks) diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 40c2eacfb..9774ca6b0 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061602 # Nu sim_ticks 61602395500 # Number of ticks simulated final_tick 61602395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83209 # Simulator instruction rate (inst/s) -host_op_rate 146518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32444685 # Simulator tick rate (ticks/s) -host_mem_usage 451056 # Number of bytes of host memory used -host_seconds 1898.69 # Real time elapsed on the host +host_inst_rate 109389 # Simulator instruction rate (inst/s) +host_op_rate 192617 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42652748 # Simulator tick rate (ticks/s) +host_mem_usage 458300 # Number of bytes of host memory used +host_seconds 1444.28 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,12 +222,12 @@ system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Wr system.physmem.wrPerTurnAround::18 7 77.78% 88.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 1 11.11% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads -system.physmem.totQLat 132992250 # Total ticks spent queuing -system.physmem.totMemAccLat 701923500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 132940250 # Total ticks spent queuing +system.physmem.totMemAccLat 701871500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 151715000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4382.96 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4381.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23132.96 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23131.25 # Average memory access latency per DRAM burst system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s @@ -249,28 +249,28 @@ system.physmem_0.preEnergy 5960625 # En system.physmem_0.readEnergy 122031000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 991440 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2832651765 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34473588000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41469365190 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.233667 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57335439750 # Time in different power states +system.physmem_0.actBackEnergy 2832436305 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34473777000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41469338730 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.233237 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57335755750 # Time in different power states system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2206407250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2206091250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 114207600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3020113080 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34309140000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41481582315 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.432156 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57061058750 # Time in different power states +system.physmem_1.actBackEnergy 3020027580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34309215000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41481571815 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.431985 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57061184750 # Time in different power states system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2480990750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2480864750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 36908902 # Number of BP lookups system.cpu.branchPred.condPredicted 36908902 # Number of conditional branches predicted @@ -325,24 +325,24 @@ system.cpu.decode.SquashCycles 776598 # Nu system.cpu.decode.DecodedInsts 331225454 # Number of instructions handled by decode system.cpu.rename.SquashCycles 776598 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 18253440 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8529181 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 8529193 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 16791 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 40202739 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55361222 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 325142962 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 55361210 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 325142958 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1786 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 778279 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48626761 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4947640 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 327068193 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 863737847 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 532004044 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 48626800 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4947589 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 327068190 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 863737834 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 532004035 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47855446 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 47855443 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 492 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 490 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66412230 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 66412234 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 36169393 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 49402360 # Number of conflicting loads. @@ -358,13 +358,13 @@ system.cpu.iq.issued_per_cycle::samples 123139971 # Nu system.cpu.iq.issued_per_cycle::mean 2.485814 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.139103 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30260082 24.57% 24.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19566754 15.89% 40.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16687046 13.55% 54.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17331207 14.07% 68.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 14759369 11.99% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12567445 10.21% 90.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6273255 5.09% 95.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30260078 24.57% 24.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19566758 15.89% 40.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16687037 13.55% 54.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17331221 14.07% 68.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 14759373 11.99% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12567435 10.21% 90.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6273256 5.09% 95.38% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 3904180 3.17% 98.55% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1790633 1.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle @@ -401,7 +401,7 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.53% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3433516 86.49% 95.02% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 197609 4.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available @@ -441,15 +441,15 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 306103022 # Type of FU issued system.cpu.iq.rate 2.484506 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3969923 # FU busy when requested +system.cpu.iq.fu_busy_cnt 3969922 # FU busy when requested system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 739361487 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 739361486 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 366454631 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 304282654 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 310039424 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 310039423 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 58196276 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -464,14 +464,14 @@ system.cpu.iew.lsq.thread0.cacheBlocked 141546 # Nu system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 776598 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 5329301 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3100547 # Number of cycles IEW is unblocking +system.cpu.iew.iewUnblockCycles 3100559 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 322303730 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 36169393 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3102570 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3102582 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 371679 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 414777 # Number of branches that were predicted not taken incorrectly @@ -485,7 +485,7 @@ system.cpu.iew.exec_refs 131430383 # nu system.cpu.iew.exec_branches 31401847 # Number of branches executed system.cpu.iew.exec_stores 33679798 # Number of stores executed system.cpu.iew.exec_rate 2.476825 # Inst execution rate -system.cpu.iew.wb_sent 304565841 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent 304565840 # cumulative count of insts sent to commit system.cpu.iew.wb_count 304282787 # cumulative count of insts written-back system.cpu.iew.wb_producers 230213925 # num instructions producing a value system.cpu.iew.wb_consumers 333861001 # num instructions consuming a value @@ -500,14 +500,14 @@ system.cpu.commit.committed_per_cycle::samples 117119203 system.cpu.commit.committed_per_cycle::mean 2.375293 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 3.092758 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52926109 45.19% 45.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15815586 13.50% 58.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52926112 45.19% 45.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15815584 13.50% 58.69% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 10978620 9.37% 68.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8749339 7.47% 75.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1860123 1.59% 77.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1720770 1.47% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 865930 0.74% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 690109 0.59% 79.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8749335 7.47% 75.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1860124 1.59% 77.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1720771 1.47% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 865932 0.74% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 690108 0.59% 79.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 23512617 20.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle @@ -570,7 +570,7 @@ system.cpu.cpi_total 0.779834 # CP system.cpu.ipc 1.282325 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.282325 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 491477122 # number of integer regfile reads -system.cpu.int_regfile_writes 239432261 # number of integer regfile writes +system.cpu.int_regfile_writes 239432260 # number of integer regfile writes system.cpu.fp_regfile_reads 110 # number of floating regfile reads system.cpu.fp_regfile_writes 84 # number of floating regfile writes system.cpu.cc_regfile_reads 107533023 # number of cc regfile reads @@ -609,14 +609,14 @@ system.cpu.dcache.demand_misses::cpu.data 2785082 # n system.cpu.dcache.demand_misses::total 2785082 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2785082 # number of overall misses system.cpu.dcache.overall_misses::total 2785082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304422000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32304422000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956618494 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2956618494 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35261040494 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35261040494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35261040494 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35261040494 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304507500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32304507500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956593494 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2956593494 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35261100994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35261100994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35261100994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35261100994 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 39416377 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 39416377 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) @@ -633,19 +633,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.929169 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.929169 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.498659 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.498659 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12660.683059 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12660.683059 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 221512 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.960940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.960940 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.232497 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.232497 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12660.704781 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12660.704781 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 221514 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 43222 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124983 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.125029 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -667,14 +667,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2076410 system.cpu.dcache.demand_mshr_misses::total 2076410 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2076410 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2076410 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196094000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196094000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995490995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26995490995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995490995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26995490995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196144500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196144500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799371995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799371995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995516495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26995516495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995516495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26995516495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses @@ -683,22 +683,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.223474 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.223474 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.248795 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.248795 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.374372 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.374372 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 53 # number of replacements -system.cpu.icache.tags.tagsinuse 825.040012 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 825.039934 # Cycle average of tags in use system.cpu.icache.tags.total_refs 27442569 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 27090.393880 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 825.040012 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 825.039934 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.402852 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.402852 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id @@ -721,12 +721,12 @@ system.cpu.icache.demand_misses::cpu.inst 1323 # n system.cpu.icache.demand_misses::total 1323 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1323 # number of overall misses system.cpu.icache.overall_misses::total 1323 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 97269000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 97269000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 97269000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 97269000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 97269000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 97269000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 97144000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 97144000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 97144000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 97144000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 97144000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 97144000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 27443892 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 27443892 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 27443892 # number of demand (read+write) accesses @@ -739,12 +739,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73521.541950 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73521.541950 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73521.541950 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73521.541950 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73521.541950 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73521.541950 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73427.059713 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73427.059713 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73427.059713 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73427.059713 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -765,34 +765,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1014 system.cpu.icache.demand_mshr_misses::total 1014 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1014 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77416000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 77416000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77416000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 77416000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77416000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 77416000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77391000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 77391000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77391000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 77391000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77391000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 77391000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76347.140039 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76347.140039 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76347.140039 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76347.140039 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76347.140039 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76347.140039 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76322.485207 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76322.485207 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 487 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20712.335895 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 20712.335726 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4035103 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 30405 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 132.711824 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576431 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841934 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917530 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576352 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841852 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917522 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.603991 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020595 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.007505 # Average percentage of cache occupancy @@ -834,18 +834,18 @@ system.cpu.l2cache.demand_misses::total 30422 # nu system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29424 # number of overall misses system.cpu.l2cache.overall_misses::total 30422 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118154500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2118154500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75720000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 75720000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32849000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 32849000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 75720000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2151003500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2226723500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 75720000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2151003500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2226723500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118128500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2118128500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75694000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 75694000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32848500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 32848500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 75694000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2150977000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2226671000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 75694000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2150977000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2226671000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 2066601 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 2066601 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) @@ -874,18 +874,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.014644 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984221 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014171 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.847921 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.847921 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75871.743487 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75871.743487 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77110.328638 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77110.328638 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75871.743487 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73103.707858 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73194.513839 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75871.743487 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73103.707858 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73194.513839 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73043.951307 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73043.951307 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75845.691383 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75845.691383 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77109.154930 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77109.154930 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73192.788114 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73192.788114 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -910,18 +910,18 @@ system.cpu.l2cache.demand_mshr_misses::total 30422 system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29424 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30422 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828174500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828174500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65740000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65740000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28589000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28589000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65740000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856763500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1922503500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65740000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856763500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1922503500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828148500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828148500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65714000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65714000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28588500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28588500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65714000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856737000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1922451000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65714000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856737000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1922451000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses @@ -936,19 +936,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.847921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.847921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.743487 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.743487 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67110.328638 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67110.328638 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63043.951307 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63043.951307 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65845.691383 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65845.691383 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67109.154930 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67109.154930 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4149790 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072370 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2066785 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6027 # Transaction distribution @@ -966,15 +972,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 265217536 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 487 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4150277 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.000117 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010832 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.009390 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4149790 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 487 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4149911 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 366 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4150277 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4141496000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) @@ -1005,7 +1011,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 30636 # Request fanout histogram -system.membus.reqLayer0.occupancy 42746500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 42746000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 160323750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index d40f8a71c..d05ee6d96 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu sim_ticks 365988859500 # Number of ticks simulated final_tick 365988859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 643347 # Simulator instruction rate (inst/s) -host_op_rate 1132831 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1490347920 # Simulator tick rate (ticks/s) -host_mem_usage 451472 # Number of bytes of host memory used -host_seconds 245.57 # Real time elapsed on the host +host_inst_rate 563395 # Simulator instruction rate (inst/s) +host_op_rate 992048 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1305133674 # Simulator tick rate (ticks/s) +host_mem_usage 455224 # Number of bytes of host memory used +host_seconds 280.42 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -449,6 +449,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.490660 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2062584 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 486 # Transaction distribution @@ -464,15 +470,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 264327616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 313 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4130707 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.000076 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.008704 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000048 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.006906 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4130394 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 313 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4130510 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 197 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4130707 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4127679000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) |