diff options
Diffstat (limited to 'tests/long/se/10.mcf/ref')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt | 879 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1214 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt | 520 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt | 1013 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt | 515 |
5 files changed, 4141 insertions, 0 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index e69de29bb..be7e45565 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,879 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.061235 # Number of seconds simulated +sim_ticks 61234797500 # Number of ticks simulated +final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 196562 # Simulator instruction rate (inst/s) +host_op_rate 197541 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132848546 # Simulator tick rate (ticks/s) +host_mem_usage 399976 # Number of bytes of host memory used +host_seconds 460.94 # Real time elapsed on the host +sim_insts 90602850 # Number of instructions simulated +sim_ops 91054081 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory +system.physmem.bytes_read::total 996672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15573 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 807907 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15468329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16276236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 807907 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 807907 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 807907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15468329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16276236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15573 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 15573 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 996672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 996672 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 993 # Per bank write bursts +system.physmem.perBankRdBursts::1 890 # Per bank write bursts +system.physmem.perBankRdBursts::2 949 # Per bank write bursts +system.physmem.perBankRdBursts::3 1027 # Per bank write bursts +system.physmem.perBankRdBursts::4 1050 # Per bank write bursts +system.physmem.perBankRdBursts::5 1113 # Per bank write bursts +system.physmem.perBankRdBursts::6 1087 # Per bank write bursts +system.physmem.perBankRdBursts::7 1088 # Per bank write bursts +system.physmem.perBankRdBursts::8 1024 # Per bank write bursts +system.physmem.perBankRdBursts::9 962 # Per bank write bursts +system.physmem.perBankRdBursts::10 938 # Per bank write bursts +system.physmem.perBankRdBursts::11 899 # Per bank write bursts +system.physmem.perBankRdBursts::12 904 # Per bank write bursts +system.physmem.perBankRdBursts::13 867 # Per bank write bursts +system.physmem.perBankRdBursts::14 876 # Per bank write bursts +system.physmem.perBankRdBursts::15 906 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 61234703000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 15573 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1535 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 648.213681 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 443.714701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 401.012846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 241 15.70% 15.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 186 12.12% 27.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 88 5.73% 33.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 73 4.76% 38.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 4.63% 42.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 84 5.47% 48.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 2.35% 50.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 51 3.32% 54.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 705 45.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1535 # Bytes accessed per row activation +system.physmem.totQLat 72594750 # Total ticks spent queuing +system.physmem.totMemAccLat 364588500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77865000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4661.58 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 23411.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 14028 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 3932107.04 # Average gap between requests +system.physmem.pageHitRate 90.08 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6282360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3427875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63679200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3999315840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2519893620 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34528365000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41120963895 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.567381 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57430990750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2044640000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1755713000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3999315840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2548962765 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34502857500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41116813260 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.499745 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57389143250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2044640000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 20750031 # Number of BP lookups +system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8954908 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8830467 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.610360 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 61988 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26205 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.numCycles 122469595 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 90602850 # Number of instructions committed +system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2175024 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.351719 # CPI: cycles per instruction +system.cpu.ipc 0.739799 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction +system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction +system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 91054081 # Class of committed instruction +system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 946097 # number of replacements +system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.639317 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20511782500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.804007 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.883009 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.883009 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2253 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660692 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 26254404 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26254404 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26254912 # number of overall hits +system.cpu.dcache.overall_hits::total 26254912 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 914926 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 914926 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74289 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74289 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 989215 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 989215 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 989219 # number of overall misses +system.cpu.dcache.overall_misses::total 989219 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919140000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11919140000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2539899500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2539899500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14459039500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14459039500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14459039500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14459039500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22508638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22508638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 27243619 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27243619 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27244131 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27244131 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040648 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040648 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015689 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015689 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036310 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036310 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.436099 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.436099 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34189.442582 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34189.442582 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14616.680398 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14616.680398 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14616.621294 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14616.621294 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 943278 # number of writebacks +system.cpu.dcache.writebacks::total 943278 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11500 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11500 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27525 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27525 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39025 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39025 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39025 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39025 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903426 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903426 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 950190 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1480423500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1480423500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345929500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12345929500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346086000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12346086000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034878 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034878 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034877 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12027.001658 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12027.001658 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency +system.cpu.icache.tags.replacements 5 # number of replacements +system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 34665.279650 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 990185500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50052500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 940133000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 990185500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000283 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016375 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016375 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63327.867162 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63327.867162 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64750.970246 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64750.970246 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74580.078125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74580.078125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 903429 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846483 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2848090 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 950994 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 950828 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 950994 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1891831000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1202498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1029 # Transaction distribution +system.membus.trans_dist::ReadExReq 14544 # Transaction distribution +system.membus.trans_dist::ReadExResp 14544 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1029 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31146 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31146 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 996672 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15573 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15573 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15573 # Request fanout histogram +system.membus.reqLayer0.occupancy 21737000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 82128750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index e69de29bb..5fa1b74da 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -0,0 +1,1214 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.058199 # Number of seconds simulated +sim_ticks 58199030500 # Number of ticks simulated +final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 101249 # Simulator instruction rate (inst/s) +host_op_rate 101754 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65047265 # Simulator tick rate (ticks/s) +host_mem_usage 487144 # Number of bytes of host memory used +host_seconds 894.72 # Real time elapsed on the host +sim_insts 90589799 # Number of instructions simulated +sim_ops 91041030 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory +system.physmem.bytes_read::total 1057024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory +system.physmem.bytes_written::total 11200 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 693 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1369 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14454 # Number of read requests responded to by this memory +system.physmem.num_reads::total 16516 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 175 # Number of write requests responded to by this memory +system.physmem.num_writes::total 175 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 762075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1505455 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15894698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 18162227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 762075 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 762075 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 192443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 192443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 192443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 762075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1505455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15894698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18354670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 16517 # Number of read requests accepted +system.physmem.writeReqs 175 # Number of write requests accepted +system.physmem.readBursts 16517 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 175 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1048320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1057088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11200 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 1166 # Per bank write bursts +system.physmem.perBankRdBursts::1 920 # Per bank write bursts +system.physmem.perBankRdBursts::2 953 # Per bank write bursts +system.physmem.perBankRdBursts::3 1031 # Per bank write bursts +system.physmem.perBankRdBursts::4 1061 # Per bank write bursts +system.physmem.perBankRdBursts::5 1122 # Per bank write bursts +system.physmem.perBankRdBursts::6 1094 # Per bank write bursts +system.physmem.perBankRdBursts::7 1089 # Per bank write bursts +system.physmem.perBankRdBursts::8 1025 # Per bank write bursts +system.physmem.perBankRdBursts::9 962 # Per bank write bursts +system.physmem.perBankRdBursts::10 933 # Per bank write bursts +system.physmem.perBankRdBursts::11 900 # Per bank write bursts +system.physmem.perBankRdBursts::12 903 # Per bank write bursts +system.physmem.perBankRdBursts::13 900 # Per bank write bursts +system.physmem.perBankRdBursts::14 1411 # Per bank write bursts +system.physmem.perBankRdBursts::15 910 # Per bank write bursts +system.physmem.perBankWrBursts::0 2 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 6 # Per bank write bursts +system.physmem.perBankWrBursts::3 1 # Per bank write bursts +system.physmem.perBankWrBursts::4 3 # Per bank write bursts +system.physmem.perBankWrBursts::5 16 # Per bank write bursts +system.physmem.perBankWrBursts::6 40 # Per bank write bursts +system.physmem.perBankWrBursts::7 7 # Per bank write bursts +system.physmem.perBankWrBursts::8 2 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 2 # Per bank write bursts +system.physmem.perBankWrBursts::11 2 # Per bank write bursts +system.physmem.perBankWrBursts::12 2 # Per bank write bursts +system.physmem.perBankWrBursts::13 17 # Per bank write bursts +system.physmem.perBankWrBursts::14 37 # Per bank write bursts +system.physmem.perBankWrBursts::15 7 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 58199022000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 16517 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 175 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 11454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1812 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 582.746137 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 353.648277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 424.722034 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 448 24.72% 24.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 213 11.75% 36.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96 5.30% 41.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 72 3.97% 45.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 3.09% 48.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 67 3.70% 52.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 61 3.37% 55.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 48 2.65% 58.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 751 41.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1812 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2016.250000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 98.342741 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 5441.040729 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 7 87.50% 87.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 12.50% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads +system.physmem.totQLat 175730624 # Total ticks spent queuing +system.physmem.totMemAccLat 482855624 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 81900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10728.37 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29478.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 18.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 18.16 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing +system.physmem.readRowHits 14651 # Number of row buffer hits during reads +system.physmem.writeRowHits 51 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.82 # Row buffer hit rate for writes +system.physmem.avgGap 3486641.62 # Average gap between requests +system.physmem.pageHitRate 88.83 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 65512200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 486000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2714701095 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32535498750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39129012390 # Total energy per rank (pJ) +system.physmem_0.averagePower 672.381118 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54114607553 # Time in different power states +system.physmem_0.memoryStateTime::REF 1943240000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2137743447 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6017760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3283500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 61916400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 447120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2480426820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32741002500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39094071540 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.780705 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54458056984 # Time in different power states +system.physmem_1.memoryStateTime::REF 1943240000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 28233538 # Number of BP lookups +system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11829354 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11747655 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.309354 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 74541 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 92 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 27216 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25478 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.numCycles 116398062 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 746143 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134906479 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28233538 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11847674 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114760827 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1674187 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 805 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32275055 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 562 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116345779 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.164712 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.318875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58810972 50.55% 50.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13933527 11.98% 62.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9228064 7.93% 70.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34373216 29.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 116345779 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242560 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.159010 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8834252 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64111694 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33013656 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9560800 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 825377 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4097950 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114395383 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1985420 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 825377 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15270485 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49952350 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109536 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35410349 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14777682 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110872417 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1412237 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11132933 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1144918 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1526969 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 486977 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129945519 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483153288 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119447216 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 22632600 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21510749 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26805153 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5347343 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 519410 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 254099 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109667150 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101366848 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074801 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18634403 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41667299 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116345779 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871255 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989200 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54714850 47.03% 47.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31358235 26.95% 73.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22007860 18.92% 92.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7066756 6.07% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197765 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116345779 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9784213 48.67% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9614548 47.83% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 702998 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71970791 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10698 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24337715 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5047462 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 101366848 # Type of FU issued +system.cpu.iq.rate 0.870864 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20101822 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198308 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340255638 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128310520 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99608490 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 624 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121468430 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 288068 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 4329242 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1500 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1342 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 602499 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 7579 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130663 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 825377 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8119454 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 685980 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109688255 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26805153 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5347343 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 180270 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 342292 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1342 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 435059 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412404 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 847463 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100109842 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23803071 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1257006 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 12822 # number of nop insts executed +system.cpu.iew.exec_refs 28718921 # number of memory reference insts executed +system.cpu.iew.exec_branches 20621209 # Number of branches executed +system.cpu.iew.exec_stores 4915850 # Number of stores executed +system.cpu.iew.exec_rate 0.860065 # Inst execution rate +system.cpu.iew.wb_sent 99693752 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99608605 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59691637 # num instructions producing a value +system.cpu.iew.wb_consumers 95527463 # num instructions consuming a value +system.cpu.iew.wb_rate 0.855758 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624864 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17362842 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 823674 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113658017 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801119 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.737711 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77235221 67.95% 67.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18611593 16.38% 84.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7151823 6.29% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3469408 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644636 1.45% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541902 0.48% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 703188 0.62% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178974 0.16% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4121272 3.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113658017 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90602408 # Number of instructions committed +system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 27220755 # Number of memory references committed +system.cpu.commit.loads 22475911 # Number of loads committed +system.cpu.commit.membars 3888 # Number of memory barriers committed +system.cpu.commit.branches 18732305 # Number of branches committed +system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. +system.cpu.commit.int_insts 72326352 # Number of committed integer instructions. +system.cpu.commit.function_calls 56148 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction +system.cpu.commit.bw_lim_events 4121272 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 217947492 # The number of ROB reads +system.cpu.rob.rob_writes 219521309 # The number of ROB writes +system.cpu.timesIdled 570 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 52283 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90589799 # Number of Instructions Simulated +system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.284891 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284891 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778276 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778276 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108097873 # number of integer regfile reads +system.cpu.int_regfile_writes 58692304 # number of integer regfile writes +system.cpu.fp_regfile_reads 59 # number of floating regfile reads +system.cpu.fp_regfile_writes 96 # number of floating regfile writes +system.cpu.cc_regfile_reads 369004699 # number of cc regfile reads +system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes +system.cpu.misc_regfile_reads 28410220 # number of misc regfile reads +system.cpu.misc_regfile_writes 7784 # number of misc regfile writes +system.cpu.dcache.tags.replacements 5470634 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5471146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.335565 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 35796500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.784091 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999578 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353747 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 18241078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18241078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18241600 # number of overall hits +system.cpu.dcache.overall_hits::total 18241600 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9587264 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9587264 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381234 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381234 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9968498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9968498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9968505 # number of overall misses +system.cpu.dcache.overall_misses::total 9968505 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88773272500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88773272500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000795875 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4000795875 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 291000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 291000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92774068375 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92774068375 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92774068375 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92774068375 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23474595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23474595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 884 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 17033 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 226019 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 226019 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 210 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 159948000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 5451171 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 5451171 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 17033 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 17033 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 226519 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 226519 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 905 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 905 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244627 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 5244627 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 905 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 5471146 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 5472051 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 905 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 5471146 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 5472051 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # 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miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.000413 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19833.333333 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19833.333333 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82519 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82519 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68221.582734 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68221.582734 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66924.413146 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66924.413146 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70773.451327 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70773.451327 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.unused_prefetches 7 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 175 # number of writebacks +system.cpu.l2cache.writebacks::total 175 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 37 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 37 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 195 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 196 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 195 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 196 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316084 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 316084 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 342 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 342 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 694 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 694 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1028 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1028 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 694 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1370 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2064 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 694 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1370 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316084 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 318148 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 852614747 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 41500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 41500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32745000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32745000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43196500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43196500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63614500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63614500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43196500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96359500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 139556000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43196500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96359500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 992170747 # number of overall MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.766851 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000196 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000196 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000377 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058141 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2697.430895 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13833.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13833.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95745.614035 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95745.614035 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62242.795389 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62242.795389 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61881.809339 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1794 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 317966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244627 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2256 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16415192 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700360640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 319939 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5791989 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.053010 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.224658 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485738 94.71% 94.71% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305466 5.27% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 785 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5791989 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10942648515 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1357497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 16175 # Transaction distribution +system.membus.trans_dist::WritebackDirty 175 # Transaction distribution +system.membus.trans_dist::CleanEvict 63 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 341 # Transaction distribution +system.membus.trans_dist::ReadExResp 341 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 16176 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 33275 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 33275 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1068224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1068224 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 16759 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 16759 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 16759 # Request fanout histogram +system.membus.reqLayer0.occupancy 27529285 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 86434816 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index e69de29bb..95463debe 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,520 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.361598 # Number of seconds simulated +sim_ticks 361597758500 # Number of ticks simulated +final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 779266 # Simulator instruction rate (inst/s) +host_op_rate 779298 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1155667536 # Simulator tick rate (ticks/s) +host_mem_usage 379236 # Number of bytes of host memory used +host_seconds 312.89 # Real time elapsed on the host +sim_insts 243825150 # Number of instructions simulated +sim_ops 243835265 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory +system.physmem.bytes_read::total 998592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 443 # Number of system calls +system.cpu.numCycles 723195517 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 243825150 # Number of instructions committed +system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses +system.cpu.num_func_calls 4252956 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls +system.cpu.num_int_insts 194726494 # number of integer instructions +system.cpu.num_fp_insts 11630 # number of float instructions +system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read +system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written +system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read +system.cpu.num_fp_register_writes 90 # number of times the floating registers were written +system.cpu.num_mem_refs 105711441 # number of memory refs +system.cpu.num_load_insts 82803521 # Number of load instructions +system.cpu.num_store_insts 22907920 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 29302884 # Number of branches fetched +system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction +system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction +system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 244431613 # Class of executed instruction +system.cpu.dcache.tags.replacements 935475 # number of replacements +system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits +system.cpu.dcache.overall_hits::total 104182817 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses +system.cpu.dcache.overall_misses::total 939567 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks +system.cpu.dcache.writebacks::total 935266 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency +system.cpu.icache.tags.replacements 25 # number of replacements +system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses +system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits +system.cpu.icache.overall_hits::total 244420617 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses +system.cpu.icache.overall_misses::total 882 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # 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average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 25 # number of writebacks +system.cpu.icache.writebacks::total 25 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 882 # 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number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1036 # Transaction distribution +system.membus.trans_dist::ReadExReq 14567 # Transaction distribution +system.membus.trans_dist::ReadExResp 14567 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15603 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15603 # Request fanout histogram +system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index e69de29bb..7579adace 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -0,0 +1,1013 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.065987 # Number of seconds simulated +sim_ticks 65986743500 # Number of ticks simulated +final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 84238 # Simulator instruction rate (inst/s) +host_op_rate 148330 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35183666 # Simulator tick rate (ticks/s) +host_mem_usage 410392 # Number of bytes of host memory used +host_seconds 1875.49 # Real time elapsed on the host +sim_insts 157988547 # Number of instructions simulated +sim_ops 278192464 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory +system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 69440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 69440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 17920 # Number of bytes written to this memory +system.physmem.bytes_written::total 17920 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29537 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30622 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 280 # Number of write requests responded to by this memory +system.physmem.num_writes::total 280 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1052333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28647693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29700026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1052333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1052333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 271570 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 271570 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 271570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1052333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28647693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29971596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30622 # Number of read requests accepted +system.physmem.writeReqs 280 # Number of write requests accepted +system.physmem.readBursts 30622 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 280 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1952768 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue +system.physmem.bytesWritten 16064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1959808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 17920 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 1932 # Per bank write bursts +system.physmem.perBankRdBursts::1 2084 # Per bank write bursts +system.physmem.perBankRdBursts::2 2041 # Per bank write bursts +system.physmem.perBankRdBursts::3 1935 # Per bank write bursts +system.physmem.perBankRdBursts::4 2086 # Per bank write bursts +system.physmem.perBankRdBursts::5 1909 # Per bank write bursts +system.physmem.perBankRdBursts::6 1974 # Per bank write bursts +system.physmem.perBankRdBursts::7 1865 # Per bank write bursts +system.physmem.perBankRdBursts::8 1948 # Per bank write bursts +system.physmem.perBankRdBursts::9 1940 # Per bank write bursts +system.physmem.perBankRdBursts::10 1806 # Per bank write bursts +system.physmem.perBankRdBursts::11 1794 # Per bank write bursts +system.physmem.perBankRdBursts::12 1792 # Per bank write bursts +system.physmem.perBankRdBursts::13 1799 # Per bank write bursts +system.physmem.perBankRdBursts::14 1828 # Per bank write bursts +system.physmem.perBankRdBursts::15 1779 # Per bank write bursts +system.physmem.perBankWrBursts::0 10 # Per bank write bursts +system.physmem.perBankWrBursts::1 107 # Per bank write bursts +system.physmem.perBankWrBursts::2 30 # Per bank write bursts +system.physmem.perBankWrBursts::3 12 # Per bank write bursts +system.physmem.perBankWrBursts::4 60 # Per bank write bursts +system.physmem.perBankWrBursts::5 8 # Per bank write bursts +system.physmem.perBankWrBursts::6 16 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 5 # Per bank write bursts +system.physmem.perBankWrBursts::10 3 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 65986546500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 30622 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 280 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 2831 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 694.731190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 483.360902 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 396.952113 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 443 15.65% 15.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 258 9.11% 24.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 108 3.81% 28.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 115 4.06% 32.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 113 3.99% 36.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 115 4.06% 40.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 137 4.84% 45.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 80 2.83% 48.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1462 51.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2831 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2175.285714 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 28.380874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 8064.070078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 13 92.86% 92.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 7.14% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 14 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.928571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.918266 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.615728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 7.14% 7.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 12 85.71% 92.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 7.14% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 14 # Writes before turning the bus around for reads +system.physmem.totQLat 136557750 # Total ticks spent queuing +system.physmem.totMemAccLat 708657750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152560000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4475.54 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 23225.54 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.59 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.27 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.23 # Data bus utilization in percentage +system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.53 # Average write queue length when enqueuing +system.physmem.readRowHits 27745 # Number of row buffer hits during reads +system.physmem.writeRowHits 178 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 63.57 # Row buffer hit rate for writes +system.physmem.avgGap 2135348.73 # Average gap between requests +system.physmem.pageHitRate 90.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11551680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 6303000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 123130800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1574640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3035388510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36925944000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 44413430070 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.125124 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 61414409250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2203240000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2364289750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 9805320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5350125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114441600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3171429270 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36806601750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 44417217345 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.182663 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 61216839000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2203240000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 40828848 # Number of BP lookups +system.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26813424 # Number of BTB lookups +system.cpu.branchPred.BTBHits 0 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6079027 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 92484 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26813424 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 21202389 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.numCycles 131973488 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 30825655 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 222121094 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40828848 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27281416 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 99433771 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3060135 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 329 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 6280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 112427 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29997924 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 374431 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 131908700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.964131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.412100 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65727022 49.83% 49.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4068693 3.08% 52.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3626407 2.75% 55.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6133247 4.65% 60.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7782444 5.90% 66.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5574161 4.23% 70.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3387073 2.57% 73.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2926863 2.22% 75.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32682790 24.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 131908700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309372 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.683074 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15512553 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64273138 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40712149 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9880793 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1530067 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 365468602 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1530067 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 21068463 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11448631 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17559 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44736331 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53107649 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355543189 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 24245 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 799476 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46595900 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4792588 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 358065930 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 942303414 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 580264608 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 22491 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 78853183 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 501 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 500 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64461317 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 113156478 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38725561 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51813945 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9109294 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 346336448 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4423 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 319025181 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 175223 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 68148407 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 106206343 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3978 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131908700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.418530 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.165753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 35712645 27.07% 27.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20185531 15.30% 42.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17171104 13.02% 55.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17670057 13.40% 68.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15380757 11.66% 80.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12917935 9.79% 90.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6743014 5.11% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4104772 3.11% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2022885 1.53% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131908700 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 364922 8.93% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3529438 86.37% 95.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 191983 4.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 182585704 57.23% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11686 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 478 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 321 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101596397 31.85% 89.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34797255 10.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 319025181 # Type of FU issued +system.cpu.iq.rate 2.417343 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4086343 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012809 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 774202119 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 414517759 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 314637932 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 18509 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 33754 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4413 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 323069884 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8300 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57418928 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 22377093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67905 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 65034 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7285809 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 4034 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 140997 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 1530067 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8343953 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3020633 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 346340871 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 136261 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 113156478 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38725561 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1825 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2944 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3026950 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 65034 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 548248 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1104057 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1652305 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 316487526 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100816589 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2537655 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 135188403 # number of memory reference insts executed +system.cpu.iew.exec_branches 32185799 # Number of branches executed +system.cpu.iew.exec_stores 34371814 # Number of stores executed +system.cpu.iew.exec_rate 2.398114 # Inst execution rate +system.cpu.iew.wb_sent 315304152 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 314642345 # cumulative count of insts written-back +system.cpu.iew.wb_producers 238446717 # num instructions producing a value +system.cpu.iew.wb_consumers 344411432 # num instructions consuming a value +system.cpu.iew.wb_rate 2.384133 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692331 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68273083 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1477187 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 122118176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.278059 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.046851 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 56957157 46.64% 46.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16546673 13.55% 60.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11180219 9.16% 69.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8765216 7.18% 76.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2116572 1.73% 78.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1764817 1.45% 79.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 934979 0.77% 80.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 730886 0.60% 81.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23121657 18.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 122118176 # Number of insts commited each cycle +system.cpu.commit.committedInsts 157988547 # Number of instructions committed +system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 122219137 # Number of memory references committed +system.cpu.commit.loads 90779385 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 29309705 # Number of branches committed +system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. +system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. +system.cpu.commit.function_calls 4237596 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction +system.cpu.commit.bw_lim_events 23121657 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 445462066 # The number of ROB reads +system.cpu.rob.rob_writes 702797421 # The number of ROB writes +system.cpu.timesIdled 887 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64788 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 157988547 # Number of Instructions Simulated +system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.835336 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.835336 # CPI: Total CPI of All Threads +system.cpu.ipc 1.197123 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.197123 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 504041942 # number of integer regfile reads +system.cpu.int_regfile_writes 248656420 # number of integer regfile writes +system.cpu.fp_regfile_reads 4180 # number of floating regfile reads +system.cpu.fp_regfile_writes 782 # number of floating regfile writes +system.cpu.cc_regfile_reads 109261684 # number of cc regfile reads +system.cpu.cc_regfile_writes 65602098 # number of cc regfile writes +system.cpu.misc_regfile_reads 202573497 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.replacements 2073508 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077604 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.604569 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21372047500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.413497 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993265 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993265 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3404 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31346019 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71894591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71894591 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71894591 # number of overall hits +system.cpu.dcache.overall_hits::total 71894591 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2693971 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2693971 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93733 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93733 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2787704 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2787704 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2787704 # number of overall misses +system.cpu.dcache.overall_misses::total 2787704 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32332975500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32332975500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2952822993 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2952822993 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35285798493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35285798493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35285798493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35285798493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 43242543 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 43242543 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 74682295 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74682295 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74682295 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74682295 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062299 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.062299 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037328 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037328 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037328 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037328 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12001.976079 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12001.976079 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31502.491044 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31502.491044 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12657.656083 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12657.656083 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 219202 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 497 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43207 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.073298 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 124.250000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2066969 # number of writebacks +system.cpu.dcache.writebacks::total 2066969 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698217 # 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number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2077604 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2077604 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2077604 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24221413500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24221413500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2795777993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2795777993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27017191493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27017191493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27017191493 # 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average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency +system.cpu.icache.tags.replacements 93 # number of replacements +system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1113 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26951.013477 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 870.928206 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.425258 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.425258 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1020 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 34 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses +system.cpu.icache.tags.data_accesses 59996959 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 29996478 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 29996478 # number of overall hits +system.cpu.icache.overall_hits::total 29996478 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1445 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1445 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1445 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1445 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1445 # number of overall misses +system.cpu.icache.overall_misses::total 1445 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 106088999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 106088999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 106088999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 106088999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 106088999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 106088999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 29997923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 29997923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 29997923 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 29997923 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 29997923 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 29997923 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73417.992388 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73417.992388 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73417.992388 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73417.992388 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73417.992388 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73417.992388 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 515 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 46.818182 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 93 # number of writebacks +system.cpu.icache.writebacks::total 93 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 332 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 332 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 84684499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 84684499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 84684499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 84684499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76086.701707 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76086.701707 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 650 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30622 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 131.854680 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 19620.454834 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 710.830105 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 275.118635 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.598769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021693 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.008396 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.628858 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29972 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 833 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1405 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27613 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.914673 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33330894 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33330894 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2066969 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2066969 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 93 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 93 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 52906 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 52906 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 28 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 28 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1995161 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1995161 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2048067 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2048095 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2048067 # number of overall hits +system.cpu.l2cache.overall_hits::total 2048095 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 28982 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 28982 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1085 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1085 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 555 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 555 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1085 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29537 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30622 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1085 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29537 # number of overall misses +system.cpu.l2cache.overall_misses::total 30622 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2117059500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2117059500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 82707500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 82707500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43407000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 43407000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 82707500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2160466500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2243174000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 82707500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2160466500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2243174000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066969 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2066969 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 93 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 93 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 81888 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 81888 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1113 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1113 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995716 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1995716 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1113 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2077604 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2078717 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1113 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2077604 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2078717 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353922 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.353922 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.974843 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.974843 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000278 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000278 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.974843 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014217 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014731 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.974843 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014217 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014731 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73047.391484 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73047.391484 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76228.110599 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76228.110599 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78210.810811 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78210.810811 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76228.110599 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73144.412093 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73253.673829 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76228.110599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73144.412093 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73253.673829 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 280 # number of writebacks +system.cpu.l2cache.writebacks::total 280 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28982 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28982 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1085 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1085 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 555 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 555 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1085 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29537 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30622 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1085 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29537 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30622 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827239500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827239500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 71857500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 71857500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 37857000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 37857000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71857500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1865096500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1936954000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71857500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1865096500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1936954000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353922 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353922 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974843 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000278 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014731 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014731 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63047.391484 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63047.391484 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66228.110599 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66228.110599 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68210.810811 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68210.810811 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4152318 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073604 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6909 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1113 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995716 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2319 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228716 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6231035 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265252672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265329856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 650 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2079367 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2079019 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 348 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2079367 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4143221000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1670997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1640 # Transaction distribution +system.membus.trans_dist::WritebackDirty 280 # Transaction distribution +system.membus.trans_dist::CleanEvict 45 # Transaction distribution +system.membus.trans_dist::ReadExReq 28982 # Transaction distribution +system.membus.trans_dist::ReadExResp 28982 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1640 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61569 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1977728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1977728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1977728 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 30947 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 30947 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 30947 # Request fanout histogram +system.membus.reqLayer0.occupancy 43483000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 161384500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index e69de29bb..be41a6e0b 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,515 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.366199 # Number of seconds simulated +sim_ticks 366199170500 # Number of ticks simulated +final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 433838 # Simulator instruction rate (inst/s) +host_op_rate 763918 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1005585249 # Simulator tick rate (ticks/s) +host_mem_usage 405532 # Number of bytes of host memory used +host_seconds 364.17 # Real time elapsed on the host +sim_insts 157988548 # Number of instructions simulated +sim_ops 278192465 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory +system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6528 # Number of bytes written to this memory +system.physmem.bytes_written::total 6528 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29241 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory +system.physmem.num_writes::total 102 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 140339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5110399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5250738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 140339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 140339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17826 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17826 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.numCycles 732398341 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 157988548 # Number of instructions committed +system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses +system.cpu.num_func_calls 8475189 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls +system.cpu.num_int_insts 278169482 # number of integer instructions +system.cpu.num_fp_insts 40 # number of float instructions +system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read +system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written +system.cpu.num_fp_register_reads 40 # number of times the floating registers were read +system.cpu.num_fp_register_writes 26 # number of times the floating registers were written +system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read +system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written +system.cpu.num_mem_refs 122219137 # number of memory refs +system.cpu.num_load_insts 90779385 # Number of load instructions +system.cpu.num_store_insts 31439752 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 732398340.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 29309705 # Number of branches fetched +system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction +system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction +system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 278192465 # Class of executed instruction +system.cpu.dcache.tags.replacements 2062733 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 126122344500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.299825 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995190 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1779 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2195 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits +system.cpu.dcache.overall_hits::total 120152370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses +system.cpu.dcache.overall_misses::total 2066829 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25499993500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25499993500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2801625000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2801625000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28301618500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28301618500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28301618500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28301618500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.423263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.423263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26403.273992 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26403.273992 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13693.255949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks +system.cpu.dcache.writebacks::total 2062482 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539273500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539273500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2695516000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2695516000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26234789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26234789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26234789500 # 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average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency +system.cpu.icache.tags.replacements 24 # number of replacements +system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses +system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # 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number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49857000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49857000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49857000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49857000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61704.207921 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61704.207921 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61704.207921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 24 # number of writebacks +system.cpu.icache.writebacks::total 24 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 808 # 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mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 313 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 156.452862 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.589743 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016982 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.611500 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1692 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 24 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 5 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960503 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1960503 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2037588 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2037593 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2037588 # number of overall hits +system.cpu.l2cache.overall_hits::total 2037593 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 803 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 217 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 217 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29241 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30044 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29241 # number of overall misses +system.cpu.l2cache.overall_misses::total 30044 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1726959000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1726959000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47782000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 47782000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12911500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 12911500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 47782000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1739870500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1787652500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 47782000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1739870500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1787652500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 24 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 808 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1960720 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1960720 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000111 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000111 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014148 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014531 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59504.358655 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59504.358655 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.148316 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 102 # number of writebacks +system.cpu.l2cache.writebacks::total 102 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 217 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 217 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29241 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30044 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1436719000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1436719000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39752000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39752000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10741500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10741500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39752000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1447460500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1487212500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39752000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1447460500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1487212500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000111 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49504.358655 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49504.358655 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 313 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2067950 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2067753 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2067950 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1020 # Transaction distribution +system.membus.trans_dist::WritebackDirty 102 # Transaction distribution +system.membus.trans_dist::CleanEvict 14 # Transaction distribution +system.membus.trans_dist::ReadExReq 29024 # Transaction distribution +system.membus.trans_dist::ReadExResp 29024 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1020 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 30160 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 30160 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 30160 # Request fanout histogram +system.membus.reqLayer0.occupancy 30602500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 150220000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |