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-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr1
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/o3-timing/simout10
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt1137
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout6
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt62
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini45
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-timing/simout6
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt78
12 files changed, 684 insertions, 685 deletions
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index b0792be17..4d1a87896 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -78,7 +78,6 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
-isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -465,9 +464,6 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
-[system.cpu.isa]
-type=X86ISA
-
[system.cpu.itb]
type=X86TLB
children=walker
@@ -528,9 +524,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
index ac4ad20a5..f5691fd64 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index d71b96b19..0aa3d6ea9 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:14:29
-gem5 started Oct 30 2012 16:29:18
-gem5 executing on u200540-lin
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:35:30
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -23,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 66000220500 because target called exit()
+Exiting @ tick 65982862500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 80c10d75b..1e22e4596 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.066000 # Number of seconds simulated
-sim_ticks 66000220500 # Number of ticks simulated
-final_tick 66000220500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.065983 # Number of seconds simulated
+sim_ticks 65982862500 # Number of ticks simulated
+final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 92408 # Simulator instruction rate (inst/s)
-host_op_rate 162716 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38603772 # Simulator tick rate (ticks/s)
-host_mem_usage 361664 # Number of bytes of host memory used
-host_seconds 1709.68 # Real time elapsed on the host
+host_inst_rate 71115 # Simulator instruction rate (inst/s)
+host_op_rate 125222 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 29700736 # Simulator tick rate (ticks/s)
+host_mem_usage 413360 # Number of bytes of host memory used
+host_seconds 2221.59 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
-sim_ops 278192462 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1881344 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1946176 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9344 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 29396 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 30409 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 146 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 146 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 982300 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 28505117 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 29487417 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 982300 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 982300 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 141575 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 141575 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 141575 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 982300 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 28505117 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 29628992 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 30411 # Total number of read requests seen
-system.physmem.writeReqs 146 # Total number of write requests seen
-system.physmem.cpureqs 30558 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1946176 # Total number of bytes read from memory
-system.physmem.bytesWritten 9344 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1946176 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 9344 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 46 # Number of read reqs serviced by write Q
+sim_ops 278192463 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1948288 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 11136 # Number of bytes written to this memory
+system.physmem.bytes_written::total 11136 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 29423 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 30442 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 174 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 174 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 988378 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 28538804 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 29527182 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 988378 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 988378 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 168771 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 168771 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 168771 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 988378 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 28538804 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 29695953 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 30444 # Total number of read requests seen
+system.physmem.writeReqs 174 # Total number of write requests seen
+system.physmem.cpureqs 30619 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1948288 # Total number of bytes read from memory
+system.physmem.bytesWritten 11136 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1948288 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 11136 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 1914 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 2026 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1920 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 2031 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1924 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1999 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1961 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1964 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 1870 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1865 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1866 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 1859 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1922 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1899 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1824 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1923 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1903 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1827 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 1881 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 1910 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1876 # Track reads on a per bank basis
@@ -61,15 +61,15 @@ system.physmem.perBankRdReqs::14 1869 # Tr
system.physmem.perBankRdReqs::15 1770 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 93 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 6 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 5 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 4 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 11 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 6 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 14 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 14 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 1 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 11 # Track writes on a per bank basis
@@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 66000206500 # Total gap between requests
+system.physmem.totGap 65982842000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 30411 # Categorize read packet sizes
+system.physmem.readPktSize::6 30444 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 146 # categorize write packet sizes
+system.physmem.writePktSize::6 174 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 1 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 29839 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 401 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 29860 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 399 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -138,29 +138,29 @@ system.physmem.rdQLenPdf::29 0 # Wh
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
@@ -171,125 +171,126 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 10043842 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 570319842 # Sum of mem lat for all requests
-system.physmem.totBusLat 121460000 # Total cycles spent in databus access
-system.physmem.totBankLat 438816000 # Total cycles spent in bank access
-system.physmem.avgQLat 330.77 # Average queueing delay per request
-system.physmem.avgBankLat 14451.37 # Average bank access latency per request
+system.physmem.totQLat 10444357 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 571602357 # Sum of mem lat for all requests
+system.physmem.totBusLat 121544000 # Total cycles spent in databus access
+system.physmem.totBankLat 439614000 # Total cycles spent in bank access
+system.physmem.avgQLat 343.72 # Average queueing delay per request
+system.physmem.avgBankLat 14467.65 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 18782.15 # Average memory access latency
-system.physmem.avgRdBW 29.49 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 0.14 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 29.49 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 0.14 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 18811.37 # Average memory access latency
+system.physmem.avgRdBW 29.53 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 29.53 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.17 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.19 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 11.23 # Average write queue length over time
-system.physmem.readRowHits 29628 # Number of row buffer hits during reads
-system.physmem.writeRowHits 33 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 97.57 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 22.60 # Row buffer hit rate for writes
-system.physmem.avgGap 2159904.65 # Average gap between requests
+system.physmem.avgWrQLen 11.24 # Average write queue length over time
+system.physmem.readRowHits 29640 # Number of row buffer hits during reads
+system.physmem.writeRowHits 45 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 97.54 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes
+system.physmem.avgGap 2155034.36 # Average gap between requests
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 132000442 # number of cpu cycles simulated
+system.cpu.numCycles 131965726 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 34554509 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 34554509 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 911394 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 24765022 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 24662055 # Number of BTB hits
+system.cpu.BPredUnit.lookups 34537566 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 34537566 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 909846 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 24744786 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 24642661 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 26596332 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 185596643 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 34554509 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 24662055 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 56507097 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6124499 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 43643381 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 161 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 25948459 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 189220 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 131924094 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.485407 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.326719 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 26601820 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 185569905 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 34537566 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 24642661 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 56492855 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6109576 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 43628030 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 25952050 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 188970 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 131886743 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.485312 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.326723 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 77963907 59.10% 59.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1995685 1.51% 60.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2954745 2.24% 62.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 3921734 2.97% 65.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 7794021 5.91% 71.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4758298 3.61% 75.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2730030 2.07% 77.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1578417 1.20% 78.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 28227257 21.40% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 77942049 59.10% 59.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1996023 1.51% 60.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2954192 2.24% 62.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 3924230 2.98% 65.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 7791327 5.91% 71.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4757391 3.61% 75.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2730462 2.07% 77.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1561040 1.18% 78.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 28230029 21.40% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 131924094 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.261776 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.406030 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 37436709 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 35891345 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 44770440 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 8648508 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 5177092 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 324637130 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 5177092 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 43002137 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 8530644 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 9064 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 47590207 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 27614950 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 320247590 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 230 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 56685 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 25740543 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 371 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 322254877 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 849337194 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 849335025 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2169 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 279212744 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 43042133 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 470 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 464 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 62360742 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 102568175 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 35245114 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 39579817 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 6021711 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 315893152 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1659 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 302191539 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 115107 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 37070468 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 54283440 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1213 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 131924094 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.290647 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.699813 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 131886743 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.261716 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.406198 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 37433496 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 35884188 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 44759605 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 8645670 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 5163784 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 324546222 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 5163784 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 42999384 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 8526748 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 9161 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 47575820 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 27611846 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 320149985 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 225 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 53569 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 25749083 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 361 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 322162823 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 849088667 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 849086832 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1835 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 279212745 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 42950078 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 468 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 462 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 62353215 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 102529083 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 35255084 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 39579305 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5971941 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 315806334 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1679 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 302165189 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 115128 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 36987116 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 54145851 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1234 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 131886743 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.291096 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.700528 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 24546585 18.61% 18.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 23206107 17.59% 36.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 25921610 19.65% 55.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 25807341 19.56% 75.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 18909357 14.33% 89.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 8337371 6.32% 96.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 4135132 3.13% 99.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 899614 0.68% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 160977 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 24537309 18.60% 18.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 23216690 17.60% 36.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 25879367 19.62% 55.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 25801755 19.56% 75.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 18920728 14.35% 89.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 8321327 6.31% 96.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 4137839 3.14% 99.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 905905 0.69% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 165823 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 131924094 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 131886743 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 38482 1.96% 1.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 38358 1.96% 1.96% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available
@@ -318,12 +319,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # at
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1831710 93.52% 95.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 88409 4.51% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1830721 93.50% 95.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 88976 4.54% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 31296 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 171161443 56.64% 56.65% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 31295 0.01% 0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 171151869 56.64% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.65% # Type of FU issued
@@ -352,285 +353,393 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 97760077 32.35% 89.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 33238688 11.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 97747173 32.35% 89.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 33234817 11.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 302191539 # Type of FU issued
-system.cpu.iq.rate 2.289322 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1958601 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006481 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 738380204 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 352997189 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 299552936 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1019 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 193 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 304118533 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 311 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 53992044 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 302165189 # Type of FU issued
+system.cpu.iq.rate 2.289725 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1958055 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006480 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 738289800 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 352827074 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 299525455 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 504 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 863 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 304091716 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 233 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 54002404 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 11788791 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 25892 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 34061 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 3805363 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 11749699 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 26201 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 33919 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 3815332 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 3223 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 8493 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3226 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 8521 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 5177092 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1727451 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 159578 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 315894811 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 195834 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 102568175 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 35245114 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 3211 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 73329 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 34061 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 522882 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 446154 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 969036 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 300573249 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 97290254 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1618290 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 5163784 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1727826 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 159628 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 315808013 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewLSQFullEvents 73485 # Number of times the LSQ has become full, causing a stall
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+system.cpu.iew.predictedNotTakenIncorrect 445155 # Number of branches that were predicted not taken incorrectly
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+system.cpu.iew.iewExecutedInsts 300546126 # Number of executed instructions
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system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 130308372 # number of memory reference insts executed
-system.cpu.iew.exec_branches 30889144 # Number of branches executed
-system.cpu.iew.exec_stores 33018118 # Number of stores executed
-system.cpu.iew.exec_rate 2.277062 # Inst execution rate
-system.cpu.iew.wb_sent 299980860 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 299553129 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 219502976 # num instructions producing a value
-system.cpu.iew.wb_consumers 298002309 # num instructions consuming a value
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+system.cpu.iew.exec_rate 2.277456 # Inst execution rate
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.269334 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.736581 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.269723 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.736636 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 37715212 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 911415 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 126747002 # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::0 58171175 45.90% 45.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 19282988 15.21% 61.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 11825828 9.33% 70.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 9598483 7.57% 78.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1735999 1.37% 79.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 2077835 1.64% 81.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1295284 1.02% 82.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 717786 0.57% 82.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 22041624 17.39% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 58163271 45.90% 45.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 19278050 15.21% 61.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 11813019 9.32% 70.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 9592484 7.57% 78.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1741744 1.37% 79.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 2072615 1.64% 81.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1297671 1.02% 82.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 717994 0.57% 82.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 22046111 17.40% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 126747002 # Number of insts commited each cycle
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system.cpu.commit.committedInsts 157988547 # Number of instructions committed
-system.cpu.commit.committedOps 278192462 # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps 278192463 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 122219135 # Number of memory references committed
+system.cpu.commit.refs 122219136 # Number of memory references committed
system.cpu.commit.loads 90779384 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 29309705 # Number of branches committed
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 278186170 # Number of committed integer instructions.
+system.cpu.commit.int_insts 278186172 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 22041624 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 22046111 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 420613052 # The number of ROB reads
-system.cpu.rob.rob_writes 636997439 # The number of ROB writes
-system.cpu.timesIdled 13642 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 76348 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 420497824 # The number of ROB reads
+system.cpu.rob.rob_writes 636810847 # The number of ROB writes
+system.cpu.timesIdled 13700 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 78983 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
-system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps 278192463 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated
-system.cpu.cpi 0.835506 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.835506 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.196879 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.196879 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 592880828 # number of integer regfile reads
-system.cpu.int_regfile_writes 300217894 # number of integer regfile writes
-system.cpu.fp_regfile_reads 180 # number of floating regfile reads
-system.cpu.fp_regfile_writes 79 # number of floating regfile writes
-system.cpu.misc_regfile_reads 192706911 # number of misc regfile reads
-system.cpu.icache.replacements 61 # number of replacements
-system.cpu.icache.tagsinuse 834.549611 # Cycle average of tags in use
-system.cpu.icache.total_refs 25947121 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1029 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 25215.861030 # Average number of references to valid blocks.
+system.cpu.cpi 0.835287 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.835287 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.197194 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.197194 # IPC: Total IPC of All Threads
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+system.cpu.misc_regfile_reads 192690356 # number of misc regfile reads
+system.cpu.icache.replacements 68 # number of replacements
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+system.cpu.icache.total_refs 25950700 # Total number of references to valid blocks.
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+system.cpu.icache.avg_refs 24976.612127 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 834.549611 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.407495 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.407495 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 25947121 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 25947121 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 25947121 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 25947121 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 25947121 # number of overall hits
-system.cpu.icache.overall_hits::total 25947121 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1338 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1338 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1338 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1338 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1338 # number of overall misses
-system.cpu.icache.overall_misses::total 1338 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 65589000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 65589000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 65589000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 65589000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 65589000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 65589000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 25948459 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 25948459 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 25948459 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 25948459 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 25948459 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 25948459 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 836.141366 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.408272 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.408272 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 25950700 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 25950700 # number of ReadReq hits
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+system.cpu.icache.demand_hits::total 25950700 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 25950700 # number of overall hits
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+system.cpu.icache.overall_misses::total 1350 # number of overall misses
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+system.cpu.icache.ReadReq_miss_latency::total 65277000 # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::total 65277000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 65277000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 65277000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 25952050 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 25952050 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::total 25952050 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49020.179372 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49020.179372 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49020.179372 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49020.179372 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49020.179372 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49020.179372 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 78 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48353.333333 # average ReadReq miss latency
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+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 48353.333333 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48353.333333 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 48353.333333 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 243 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 19.500000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 48.600000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 308 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 308 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 308 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 308 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 308 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 308 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1030 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1030 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1030 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1030 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 51699000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51699000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 51699000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51699000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 51699000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 310 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 310 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 310 # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::cpu.inst 310 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 310 # number of overall MSHR hits
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+system.cpu.icache.overall_mshr_misses::total 1040 # number of overall MSHR misses
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+system.cpu.icache.demand_mshr_miss_latency::total 52080000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50193.203883 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50193.203883 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50193.203883 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 50193.203883 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50193.203883 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 50193.203883 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50076.923077 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50076.923077 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50076.923077 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 50076.923077 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50076.923077 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 50076.923077 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 454 # number of replacements
-system.cpu.l2cache.tagsinuse 20802.546521 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 4028808 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 30388 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 132.578913 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 2072071 # number of replacements
+system.cpu.dcache.tagsinuse 4072.565348 # Cycle average of tags in use
+system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks.
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41347.539740 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41347.539740 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49884.690873 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41472.982158 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 41754.532913 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49884.690873 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41472.982158 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 41754.532913 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -639,168 +748,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 146 # number of writebacks
-system.cpu.l2cache.writebacks::total 146 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1013 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 400 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 1413 # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks 174 # number of writebacks
+system.cpu.l2cache.writebacks::total 174 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 424 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1443 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 1013 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 29398 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 30411 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 1013 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 29398 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 30411 # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14639611 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52385190 # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_misses::total 29001 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53879732 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 824070390 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 824070390 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37745579 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 838710001 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 876455580 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37745579 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 838710001 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 876455580 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000201 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000708 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 824195395 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 824195395 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37999583 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840075544 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 878075127 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37999583 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 840075544 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 878075127 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000213 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000723 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352585 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352585 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014160 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.014640 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984451 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014160 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.014640 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37261.183613 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36599.027500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37073.736730 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352690 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352690 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014173 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.014656 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014173 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.014656 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.052993 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37453.181604 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37338.691615 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28418.180219 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28418.180219 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37261.183613 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28529.491836 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28820.347243 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37261.183613 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28529.491836 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28820.347243 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28419.550878 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28419.550878 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.052993 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.721121 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.304789 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2072087 # number of replacements
-system.cpu.dcache.tagsinuse 4072.565599 # Cycle average of tags in use
-system.cpu.dcache.total_refs 71969114 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2076183 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 34.664148 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 21167717000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4072.565599 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 40627633 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 40627633 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 31341474 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 31341474 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 71969107 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 71969107 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 71969107 # number of overall hits
-system.cpu.dcache.overall_hits::total 71969107 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2625254 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2625254 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 98277 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 98277 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2723531 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2723531 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2723531 # number of overall misses
-system.cpu.dcache.overall_misses::total 2723531 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 31319760000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 31319760000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 2088062998 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 2088062998 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 33407822998 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 33407822998 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 33407822998 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 33407822998 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 43252887 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 43252887 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 74692638 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 74692638 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 74692638 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 74692638 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060695 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.060695 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.036463 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.036463 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.036463 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.036463 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.182756 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.182756 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21246.710807 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 21246.710807 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12266.364142 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12266.364142 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12266.364142 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12266.364142 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 32155 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 9466 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.396894 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2066445 # number of writebacks
-system.cpu.dcache.writebacks::total 2066445 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631206 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 631206 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16138 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 16138 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 647344 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 647344 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 647344 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 647344 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994048 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1994048 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82139 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 82139 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2076187 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2076187 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2076187 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2076187 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21982292500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 21982292500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812892498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812892498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23795184998 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 23795184998 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23795184998 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 23795184998 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046102 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046102 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027796 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.027796 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027796 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.027796 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11023.953536 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.953536 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22071.032007 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22071.032007 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.002789 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.002789 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.002789 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.002789 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
index 21c7d0296..93f7366bc 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -68,13 +68,13 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -91,7 +91,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.membus.slave[3]
@@ -129,9 +129,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
index ac4ad20a5..f5691fd64 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
index 809429d83..20b1e73d6 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:54:55
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:45:38
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@@ -25,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 168950039000 because target called exit()
+Exiting @ tick 168950039500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index 0a05e5832..e854ab47f 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.168950 # Number of seconds simulated
-sim_ticks 168950039000 # Number of ticks simulated
-final_tick 168950039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 168950039500 # Number of ticks simulated
+final_tick 168950039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 917389 # Simulator instruction rate (inst/s)
-host_op_rate 1615374 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 981038557 # Simulator tick rate (ticks/s)
-host_mem_usage 400492 # Number of bytes of host memory used
-host_seconds 172.22 # Real time elapsed on the host
+host_inst_rate 911205 # Simulator instruction rate (inst/s)
+host_op_rate 1604486 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 974425819 # Simulator tick rate (ticks/s)
+host_mem_usage 402856 # Number of bytes of host memory used
+host_seconds 173.38 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
-sim_ops 278192463 # Number of ops (including micro ops) simulated
+sim_ops 278192464 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 717246011 # Number of bytes read from this memory
system.physmem.bytes_read::total 2458815323 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 243173115 # Number of bytes written to this memory
-system.physmem.bytes_written::total 243173115 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 243173117 # Number of bytes written to this memory
+system.physmem.bytes_written::total 243173117 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 90779446 # Number of read requests responded to by this memory
system.physmem.num_reads::total 308475610 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 31439751 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 31439751 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 10308191240 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 4245314267 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14553505507 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 10308191240 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 10308191240 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1439319674 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1439319674 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 10308191240 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5684633941 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 15992825181 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::cpu.data 31439752 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 31439752 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 10308191209 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 4245314255 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14553505464 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 10308191209 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 10308191209 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1439319681 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1439319681 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 10308191209 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 5684633936 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 15992825145 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 337900079 # number of cpu cycles simulated
+system.cpu.numCycles 337900080 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988548 # Number of instructions committed
-system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses
+system.cpu.committedOps 278192464 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 278186173 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
-system.cpu.num_int_insts 278186171 # number of integer instructions
+system.cpu.num_int_insts 278186173 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
-system.cpu.num_int_register_reads 739519993 # number of times the integer registers were read
-system.cpu.num_int_register_writes 279212718 # number of times the integer registers were written
+system.cpu.num_int_register_reads 739519998 # number of times the integer registers were read
+system.cpu.num_int_register_writes 279212719 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
-system.cpu.num_mem_refs 122219135 # number of memory refs
+system.cpu.num_mem_refs 122219136 # number of memory refs
system.cpu.num_load_insts 90779384 # Number of load instructions
-system.cpu.num_store_insts 31439751 # Number of store instructions
+system.cpu.num_store_insts 31439752 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 337900079 # Number of busy cycles
+system.cpu.num_busy_cycles 337900080 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index 519e44990..046ac1011 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -61,21 +61,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=262144
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -90,7 +91,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[3]
@@ -99,21 +100,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=2
size=131072
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -122,7 +124,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -139,30 +141,31 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -172,10 +175,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -213,9 +216,9 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
[system.physmem]
type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
index ac4ad20a5..f5691fd64 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
@@ -1,4 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index 0ff981af8..d9a250bb1 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 23:03:49
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:35:30
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
@@ -25,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 368209206000 because target called exit()
+Exiting @ tick 365989064000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index c24d579f7..2cdeaff80 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.365989 # Number of seconds simulated
-sim_ticks 365989063000 # Number of ticks simulated
-final_tick 365989063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 365989064000 # Number of ticks simulated
+final_tick 365989064000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 621192 # Simulator instruction rate (inst/s)
-host_op_rate 1093819 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1439024491 # Simulator tick rate (ticks/s)
-host_mem_usage 361884 # Number of bytes of host memory used
-host_seconds 254.33 # Real time elapsed on the host
+host_inst_rate 426513 # Simulator instruction rate (inst/s)
+host_op_rate 751021 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 988040650 # Simulator tick rate (ticks/s)
+host_mem_usage 411308 # Number of bytes of host memory used
+host_seconds 370.42 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
-sim_ops 278192463 # Number of ops (including micro ops) simulated
+sim_ops 278192464 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory
system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory
@@ -35,35 +35,35 @@ system.physmem.bw_total::cpu.inst 140419 # To
system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 731978126 # number of cpu cycles simulated
+system.cpu.numCycles 731978128 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988548 # Number of instructions committed
-system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses
+system.cpu.committedOps 278192464 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 278186173 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
-system.cpu.num_int_insts 278186171 # number of integer instructions
+system.cpu.num_int_insts 278186173 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
-system.cpu.num_int_register_reads 739519993 # number of times the integer registers were read
-system.cpu.num_int_register_writes 279212718 # number of times the integer registers were written
+system.cpu.num_int_register_reads 739519998 # number of times the integer registers were read
+system.cpu.num_int_register_writes 279212719 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
-system.cpu.num_mem_refs 122219135 # number of memory refs
+system.cpu.num_mem_refs 122219136 # number of memory refs
system.cpu.num_load_insts 90779384 # Number of load instructions
-system.cpu.num_store_insts 31439751 # Number of store instructions
+system.cpu.num_store_insts 31439752 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 731978126 # Number of busy cycles
+system.cpu.num_busy_cycles 731978128 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements
-system.cpu.icache.tagsinuse 665.632511 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 665.632509 # Cycle average of tags in use
system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 665.632511 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 665.632509 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
@@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010
system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2062733 # number of replacements
-system.cpu.dcache.tagsinuse 4076.488641 # Cycle average of tags in use
-system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4076.488630 # Cycle average of tags in use
+system.cpu.dcache.total_refs 120152369 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 126079699000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4076.488641 # Average occupied blocks per requestor
+system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 126079700000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4076.488630 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 120152368 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 120152368 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 120152368 # number of overall hits
-system.cpu.dcache.overall_hits::total 120152368 # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 120152369 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 120152369 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 120152369 # number of overall hits
+system.cpu.dcache.overall_hits::total 120152369 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
@@ -170,12 +170,12 @@ system.cpu.dcache.overall_miss_latency::cpu.data 28097140000
system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 122219197 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 122219197 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 122219197 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 122219197 # number of overall (read+write) accesses
+system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 122219198 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 122219198 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 122219198 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 122219198 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
@@ -236,13 +236,13 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 318 # number of replacements
-system.cpu.l2cache.tagsinuse 20041.899874 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 20041.899820 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 19330.353270 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 557.646384 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 19330.353217 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 557.646383 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 153.900220 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy