diff options
Diffstat (limited to 'tests/long/se/10.mcf')
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini | 79 | ||||
| -rw-r--r-- | tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini | 22 |
2 files changed, 51 insertions, 50 deletions
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 80f56aa0a..399eedece 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -165,7 +165,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -176,7 +176,6 @@ size=262144 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -222,9 +221,9 @@ opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList1] type=FUDesc @@ -236,16 +235,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=19 opClass=IntDiv -opLat=20 +opLat=1 +pipelined=false [system.cpu.fuPool.FUList2] type=FUDesc @@ -257,23 +256,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste [system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=2 +pipelined=true [system.cpu.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=2 +pipelined=true [system.cpu.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=2 +pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc @@ -285,23 +284,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste [system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=FloatDiv opLat=12 +pipelined=false [system.cpu.fuPool.FUList3.opList2] type=OpDesc eventq_index=0 -issueLat=24 opClass=FloatSqrt opLat=24 +pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc @@ -313,9 +312,9 @@ opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu.fuPool.FUList5] type=FUDesc @@ -327,142 +326,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys [system.cpu.fuPool.FUList5.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList5.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=1 +pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc @@ -474,9 +473,9 @@ opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu.fuPool.FUList7] type=FUDesc @@ -488,16 +487,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu.fuPool.FUList8] type=FUDesc @@ -509,9 +508,9 @@ opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc eventq_index=0 -issueLat=3 opClass=IprAccess opLat=3 +pipelined=false [system.cpu.icache] type=BaseCache @@ -523,7 +522,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -534,7 +533,6 @@ size=131072 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -590,7 +588,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -601,7 +599,6 @@ size=2097152 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index 3b3cbc058..fecf9a5e9 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -92,7 +93,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -103,7 +104,6 @@ size=262144 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -143,7 +143,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -154,7 +154,6 @@ size=131072 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -210,7 +209,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -221,7 +220,6 @@ size=2097152 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -240,8 +238,11 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 @@ -295,11 +296,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master |