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-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm4
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini535
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out999
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr2
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/o3-timing/simout26
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt536
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm4
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini102
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out999
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr2
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout26
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt87
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm4
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini205
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out999
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr2
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/simple-timing/simout26
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt280
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini102
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out999
-rwxr-xr-xtests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr2
-rwxr-xr-xtests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout26
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt45
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini205
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out999
-rwxr-xr-xtests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr2
-rwxr-xr-xtests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout26
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt244
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini536
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out999
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr4
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/o3-timing/simout28
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt486
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini102
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out999
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr4
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout26
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt45
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini205
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out999
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr4
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-timing/simout26
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt234
-rw-r--r--tests/long/se/10.mcf/test.py34
44 files changed, 12219 insertions, 0 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
new file mode 100644
index 000000000..9ac19076f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
@@ -0,0 +1,4 @@
+P6
+15 15
+255
+   !!!  !!!$$$&&&'''&&&%%% !!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))''' """%%%&&&'''&&&%%%%%%  !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW \ No newline at end of file
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
new file mode 100644
index 000000000..bec9490f3
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out
@@ -0,0 +1,999 @@
+()
+500
+()
+499
+()
+498
+()
+496
+()
+495
+()
+494
+()
+493
+()
+492
+()
+491
+()
+490
+()
+489
+()
+488
+()
+487
+()
+486
+()
+484
+()
+482
+()
+481
+()
+480
+()
+479
+()
+478
+()
+477
+()
+476
+()
+475
+()
+474
+()
+473
+()
+472
+()
+471
+()
+469
+()
+468
+()
+467
+()
+466
+()
+465
+()
+464
+()
+463
+()
+462
+()
+461
+()
+460
+()
+459
+()
+458
+()
+457
+()
+455
+()
+454
+()
+452
+()
+451
+()
+450
+()
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diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
new file mode 100755
index 000000000..db74d3d24
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:43:41
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 33080569000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..190781128
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -0,0 +1,536 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.033081 # Number of seconds simulated
+sim_ticks 33080569000 # Number of ticks simulated
+final_tick 33080569000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 140676 # Simulator instruction rate (inst/s)
+host_tick_rate 50998874 # Simulator tick rate (ticks/s)
+host_mem_usage 353196 # Number of bytes of host memory used
+host_seconds 648.65 # Real time elapsed on the host
+sim_insts 91249885 # Number of instructions simulated
+system.physmem.bytes_read 997440 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 44864 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 2048 # Number of bytes written to this memory
+system.physmem.num_reads 15585 # Number of read requests responded to by this memory
+system.physmem.num_writes 32 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 30151839 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1356204 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 61909 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 30213749 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 442 # Number of system calls
+system.cpu.numCycles 66161139 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.BPredUnit.lookups 27503856 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 21975755 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1408867 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 24498145 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 23511296 # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS 109835 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 10070 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 15373276 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 131330352 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 27503856 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 23621131 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 32575580 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5466802 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 14146451 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 14 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 14744728 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 369535 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 66131343 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.004854 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.741973 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 33609066 50.82% 50.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 6636464 10.04% 60.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 5762437 8.71% 69.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 4857984 7.35% 76.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2814891 4.26% 81.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1640731 2.48% 83.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1559267 2.36% 86.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 2974436 4.50% 90.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 6276067 9.49% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 66131343 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.415710 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.985007 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 17946396 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 12652276 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 30529024 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 996648 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4006999 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4433202 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 29411 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 129091755 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 32642 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4006999 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 19654600 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1107804 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 8424491 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 29777332 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 3160117 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 124853414 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 254616 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 1879605 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 145685583 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 543523067 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 543516086 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 6981 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 107429439 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 38256144 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 662187 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 664355 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 7619533 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29336350 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 5741000 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1194254 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 692979 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 117270516 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 648807 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 106162042 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 30561 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 26211084 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 62748223 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 93963 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 66131343 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.605321 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.761707 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 24322507 36.78% 36.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14238727 21.53% 58.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 9857796 14.91% 73.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 8080873 12.22% 85.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4216462 6.38% 91.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2267133 3.43% 95.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2478028 3.75% 98.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 463113 0.70% 99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 206704 0.31% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 66131343 # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 52363 10.31% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 27 0.01% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 192834 37.95% 48.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 262907 51.74% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 74696384 70.36% 70.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 11141 0.01% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 159 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 260 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 26155378 24.64% 95.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 5298717 4.99% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total 106162042 # Type of FU issued
+system.cpu.iq.rate 1.604598 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 508131 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.004786 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 278993219 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 144129610 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 102521129 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 900 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1354 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 412 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 106669721 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 452 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 366276 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads 6760478 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 42465 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 731 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 994251 # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 30282 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles 4006999 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 182542 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 28701 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 117958129 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 810273 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 29336350 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 5741000 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 643936 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 9429 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 1050 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 731 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1288873 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 210071 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1498944 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 104530426 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25743276 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1631616 # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp 0 # number of swp insts executed
+system.cpu.iew.exec_nop 38806 # number of nop insts executed
+system.cpu.iew.exec_refs 30946109 # number of memory reference insts executed
+system.cpu.iew.exec_branches 21214083 # Number of branches executed
+system.cpu.iew.exec_stores 5202833 # Number of stores executed
+system.cpu.iew.exec_rate 1.579937 # Inst execution rate
+system.cpu.iew.wb_sent 102941811 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 102521541 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 60312663 # num instructions producing a value
+system.cpu.iew.wb_consumers 96996327 # num instructions consuming a value
+system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate 1.549573 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.621804 # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts 91262494 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 26696986 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 554844 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 1392644 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 62124345 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.469029 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.224973 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 28387912 45.70% 45.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 16565318 26.66% 72.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 5280655 8.50% 80.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 3908699 6.29% 87.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2045216 3.29% 90.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 660602 1.06% 91.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 536847 0.86% 92.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 207955 0.33% 92.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 4531141 7.29% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 62124345 # Number of insts commited each cycle
+system.cpu.commit.count 91262494 # Number of instructions committed
+system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.refs 27322621 # Number of memory references committed
+system.cpu.commit.loads 22575872 # Number of loads committed
+system.cpu.commit.membars 3888 # Number of memory barriers committed
+system.cpu.commit.branches 18722466 # Number of branches committed
+system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 72533302 # Number of committed integer instructions.
+system.cpu.commit.function_calls 56148 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 4531141 # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads 175546950 # The number of ROB reads
+system.cpu.rob.rob_writes 239939834 # The number of ROB writes
+system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 29796 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 91249885 # Number of Instructions Simulated
+system.cpu.committedInsts_total 91249885 # Number of Instructions Simulated
+system.cpu.cpi 0.725054 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.725054 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.379207 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.379207 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 496902731 # number of integer regfile reads
+system.cpu.int_regfile_writes 120936097 # number of integer regfile writes
+system.cpu.fp_regfile_reads 197 # number of floating regfile reads
+system.cpu.fp_regfile_writes 534 # number of floating regfile writes
+system.cpu.misc_regfile_reads 184886725 # number of misc regfile reads
+system.cpu.misc_regfile_writes 11594 # number of misc regfile writes
+system.cpu.icache.replacements 2 # number of replacements
+system.cpu.icache.tagsinuse 611.587678 # Cycle average of tags in use
+system.cpu.icache.total_refs 14743812 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 20420.792244 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 611.587678 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.298627 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 14743812 # number of ReadReq hits
+system.cpu.icache.demand_hits 14743812 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 14743812 # number of overall hits
+system.cpu.icache.ReadReq_misses 916 # number of ReadReq misses
+system.cpu.icache.demand_misses 916 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 916 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 32376000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 32376000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 32376000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 14744728 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 14744728 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 14744728 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000062 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000062 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000062 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 35344.978166 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 35344.978166 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 35344.978166 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits 194 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits 194 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 194 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 24887000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 24887000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 24887000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000049 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000049 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000049 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34469.529086 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34469.529086 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34469.529086 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 943456 # number of replacements
+system.cpu.dcache.tagsinuse 3558.808717 # Cycle average of tags in use
+system.cpu.dcache.total_refs 28819274 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 947552 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 30.414451 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 12353041000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 3558.808717 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.868850 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 24247443 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 4559242 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits 6797 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits 5792 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits 28806685 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 28806685 # number of overall hits
+system.cpu.dcache.ReadReq_misses 989267 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 175739 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses 1165006 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 1165006 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 5475542500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 4498706928 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency 124500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency 9974249428 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 9974249428 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 25236710 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 6804 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses 5792 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 29971691 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 29971691 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.039200 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.037115 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate 0.001029 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate 0.038870 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.038870 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 5534.949109 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 25598.796670 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 8561.543398 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 8561.543398 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 23239503 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 8123 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.950757 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 942907 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits 86240 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits 131213 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits 217453 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 217453 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 903027 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 44526 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 947553 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 947553 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 2253075000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 1081062556 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 3334137556 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 3334137556 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.035782 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.009404 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.031615 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.031615 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2495.025066 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24279.354894 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 3518.681864 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 3518.681864 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 744 # number of replacements
+system.cpu.l2cache.tagsinuse 9229.669539 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1596774 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 15569 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 102.561115 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 392.792284 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 8836.877255 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.011987 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.269680 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 901413 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 942907 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 31267 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 932680 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 932680 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 1057 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 14538 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 15595 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 15595 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 36209000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 498763000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 534972000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 534972000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 902470 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 942907 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 45805 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 948275 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 948275 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.001171 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.317389 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.016446 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.016446 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34256.385998 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34307.538864 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34304.071818 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34304.071818 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 32 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 1047 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 14538 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 15585 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 15585 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 32560500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 451777500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 484338000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 484338000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001160 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317389 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.016435 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.016435 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.853868 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.629385 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
new file mode 100644
index 000000000..9ac19076f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
@@ -0,0 +1,4 @@
+P6
+15 15
+255
+   !!!  !!!$$$&&&'''&&&%%% !!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))''' """%%%&&&'''&&&%%%%%%  !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW \ No newline at end of file
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..67a5d19a5
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
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+()
+41
+***
+91
+()
+40
+***
+96
+()
+38
+***
+100
+()
+37
+***
+149
+()
+36
+***
+74
+()
+35
+***
+258
+()
+34
+***
+151
+()
+33
+***
+85
+()
+32
+()
+31
+***
+94
+()
+30
+***
+97
+()
+29
+***
+90
+()
+28
+***
+89
+()
+27
+***
+92
+()
+26
+***
+72
+***
+247
+()
+25
+***
+86
+()
+24
+***
+82
+()
+23
+***
+87
+***
+117
+()
+22
+***
+76
+***
+119
+()
+21
+***
+84
+()
+20
+***
+78
+()
+19
+***
+73
+()
+18
+***
+81
+()
+17
+***
+65
+()
+16
+***
+63
+***
+101
+()
+15
+***
+71
+()
+14
+***
+75
+()
+13
+***
+322
+()
+12
+***
+77
+()
+11
+***
+283
+()
+10
+***
+79
+()
+9
+***
+145
+***
+150
+()
+8
+***
+67
+()
+7
+***
+60
+***
+231
+()
+6
+***
+56
+***
+234
+()
+5
+***
+164
+***
+202
+()
+4
+***
+53
+()
+3
+***
+130
+***
+185
+***
+200
+()
+2
+***
+205
+()
+1
+***
+39
+***
+95
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..902784594
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:47:31
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 54240666000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..66ab48bd5
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,87 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.054241 # Number of seconds simulated
+sim_ticks 54240666000 # Number of ticks simulated
+final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2777644 # Simulator instruction rate (inst/s)
+host_tick_rate 1651027932 # Simulator tick rate (ticks/s)
+host_mem_usage 342980 # Number of bytes of host memory used
+host_seconds 32.85 # Real time elapsed on the host
+sim_insts 91252969 # Number of instructions simulated
+system.physmem.bytes_read 521339715 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 431323116 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 18908138 # Number of bytes written to this memory
+system.physmem.num_reads 130384074 # Number of read requests responded to by this memory
+system.physmem.num_writes 4738868 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 9611602391 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7952024704 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 348597084 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9960199475 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 442 # Number of system calls
+system.cpu.numCycles 108481333 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 91252969 # Number of instructions executed
+system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
+system.cpu.num_func_calls 96832 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls
+system.cpu.num_int_insts 72525682 # number of integer instructions
+system.cpu.num_fp_insts 48 # number of float instructions
+system.cpu.num_int_register_reads 396912516 # number of times the integer registers were read
+system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
+system.cpu.num_mem_refs 27318811 # number of memory refs
+system.cpu.num_load_insts 22573967 # Number of load instructions
+system.cpu.num_store_insts 4744844 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 108481333 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
new file mode 100644
index 000000000..9ac19076f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
@@ -0,0 +1,4 @@
+P6
+15 15
+255
+   !!!  !!!$$$&&&'''&&&%%% !!!%%%(((******)))(((!!!###'''***+++,,,+++)))"""###''')))++++++***)))!!!!!!%%%((()))))))))''' """%%%&&&'''&&&%%%%%%  !!!"""#########"""(((---222666&&&...///===;;;999555111,,,((($$$DDDKKKRRRXXXBBB†††‘‘‘jjjWWWZZZUUUNNNGGG???888[[[dddkkkrrr]]]CCC===eeeaaarrrkkkddd[[[SSSKKKiiipppvvvvvvEEEggg{{{uuunnnfff^^^VVVmmmsssxxx|||oooEEEDDD]]]vvvzzzuuuooohhhaaaZZZjjjooossswwwyyyzzzzzzyyywwwtttoookkkeee```ZZZeeeiiilllnnnpppppppppooonnnkkkhhhddd```\\\WWW \ No newline at end of file
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
new file mode 100644
index 000000000..2f73411a5
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
@@ -0,0 +1,999 @@
+()
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diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
new file mode 100755
index 000000000..959967602
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:48:15
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 148086239000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..d6f3be234
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -0,0 +1,280 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.148086 # Number of seconds simulated
+sim_ticks 148086239000 # Number of ticks simulated
+final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1300672 # Simulator instruction rate (inst/s)
+host_tick_rate 2111359212 # Simulator tick rate (ticks/s)
+host_mem_usage 351948 # Number of bytes of host memory used
+host_seconds 70.14 # Real time elapsed on the host
+sim_insts 91226321 # Number of instructions simulated
+system.physmem.bytes_read 986112 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 36992 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 2048 # Number of bytes written to this memory
+system.physmem.num_reads 15408 # Number of read requests responded to by this memory
+system.physmem.num_writes 32 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 6659039 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 249800 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 13830 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 6672869 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 442 # Number of system calls
+system.cpu.numCycles 296172478 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 91226321 # Number of instructions executed
+system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
+system.cpu.num_func_calls 96832 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls
+system.cpu.num_int_insts 72525682 # number of integer instructions
+system.cpu.num_fp_insts 48 # number of float instructions
+system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read
+system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
+system.cpu.num_mem_refs 27318811 # number of memory refs
+system.cpu.num_load_insts 22573967 # Number of load instructions
+system.cpu.num_store_insts 4744844 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 296172478 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 2 # number of replacements
+system.cpu.icache.tagsinuse 510.335448 # Cycle average of tags in use
+system.cpu.icache.total_refs 107830181 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 510.335448 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.249187 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 107830181 # number of ReadReq hits
+system.cpu.icache.demand_hits 107830181 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 107830181 # number of overall hits
+system.cpu.icache.ReadReq_misses 599 # number of ReadReq misses
+system.cpu.icache.demand_misses 599 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 599 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 32662000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 32662000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 32662000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 107830780 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 107830780 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 107830780 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 54527.545910 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 54527.545910 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 54527.545910 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 599 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 599 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 599 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 30865000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 30865000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 30865000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 942702 # number of replacements
+system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use
+system.cpu.dcache.total_refs 26345365 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 3568.549501 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.871228 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 21649219 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 4688372 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits 3887 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits 3887 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits 26337591 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 26337591 # number of overall hits
+system.cpu.dcache.ReadReq_misses 900189 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 46609 # number of WriteReq misses
+system.cpu.dcache.demand_misses 946798 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 946798 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 12614490000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 1263542000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 13878032000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 13878032000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 22549408 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 3887 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses 3887 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 27284389 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 27284389 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.039921 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.009844 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.034701 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.034701 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 14657.859438 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 14657.859438 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 942309 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses 900189 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 46609 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 946798 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 946798 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 9913923000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 1123715000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 11037638000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 11037638000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.039921 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.009844 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.034701 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.034701 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 634 # number of replacements
+system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1594542 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 103.595504 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 325.097811 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 8910.209882 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.009921 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.271918 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 899928 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 942309 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 32061 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 931989 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 931989 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 860 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 14548 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 15408 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 15408 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 44720000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 756496000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 801216000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 801216000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 900788 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 942309 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 46609 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 947397 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 947397 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.000955 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.312129 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.016264 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.016264 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 32 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 860 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 14548 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 15408 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 15408 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 34400000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 581920000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 616320000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 616320000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000955 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312129 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.016264 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.016264 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..77055bd16
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
@@ -0,0 +1,999 @@
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diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
new file mode 100755
index 000000000..18a19b6d7
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:20:13
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 122215830000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..e3ffceab4
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
@@ -0,0 +1,45 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.122216 # Number of seconds simulated
+sim_ticks 122215830000 # Number of ticks simulated
+final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 3409932 # Simulator instruction rate (inst/s)
+host_tick_rate 1709135687 # Simulator tick rate (ticks/s)
+host_mem_usage 338176 # Number of bytes of host memory used
+host_seconds 71.51 # Real time elapsed on the host
+sim_insts 243835278 # Number of instructions simulated
+system.physmem.bytes_read 1306360053 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 977686044 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 91606089 # Number of bytes written to this memory
+system.physmem.num_reads 326641945 # Number of read requests responded to by this memory
+system.physmem.num_writes 22901951 # Number of write requests responded to by this memory
+system.physmem.num_other 3886 # Number of other requests responded to by this memory
+system.physmem.bw_read 10688959466 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999667834 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 749543566 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 11438503032 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls 443 # Number of system calls
+system.cpu.numCycles 244431661 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 243835278 # Number of instructions executed
+system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
+system.cpu.num_func_calls 4252956 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls
+system.cpu.num_int_insts 194726506 # number of integer instructions
+system.cpu.num_fp_insts 11630 # number of float instructions
+system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read
+system.cpu.num_int_register_writes 215451567 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
+system.cpu.num_mem_refs 105711442 # number of memory refs
+system.cpu.num_load_insts 82803522 # Number of load instructions
+system.cpu.num_store_insts 22907920 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 244431661 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
new file mode 100644
index 000000000..acd41b2d5
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=SparcTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=SparcTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out
@@ -0,0 +1,999 @@
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diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
new file mode 100755
index 000000000..ca44a686d
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:21:35
+gem5 executing on zizzer
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 362430887000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..7dc591cfe
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -0,0 +1,244 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.362431 # Number of seconds simulated
+sim_ticks 362430887000 # Number of ticks simulated
+final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1587659 # Simulator instruction rate (inst/s)
+host_tick_rate 2359857170 # Simulator tick rate (ticks/s)
+host_mem_usage 346888 # Number of bytes of host memory used
+host_seconds 153.58 # Real time elapsed on the host
+sim_insts 243835278 # Number of instructions simulated
+system.physmem.bytes_read 1001472 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 2560 # Number of bytes written to this memory
+system.physmem.num_reads 15648 # Number of read requests responded to by this memory
+system.physmem.num_writes 40 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 2763208 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 155219 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 7063 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 2770272 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls 443 # Number of system calls
+system.cpu.numCycles 724861774 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 243835278 # Number of instructions executed
+system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
+system.cpu.num_func_calls 4252956 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls
+system.cpu.num_int_insts 194726506 # number of integer instructions
+system.cpu.num_fp_insts 11630 # number of float instructions
+system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read
+system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
+system.cpu.num_mem_refs 105711442 # number of memory refs
+system.cpu.num_load_insts 82803522 # Number of load instructions
+system.cpu.num_store_insts 22907920 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 724861774 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 25 # number of replacements
+system.cpu.icache.tagsinuse 725.567632 # Cycle average of tags in use
+system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 725.567632 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.354281 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 244420630 # number of ReadReq hits
+system.cpu.icache.demand_hits 244420630 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 244420630 # number of overall hits
+system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses
+system.cpu.icache.demand_misses 882 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 882 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 49266000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 49266000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 49266000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 55857.142857 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 55857.142857 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 55857.142857 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 46620000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 46620000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 46620000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52857.142857 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 935475 # number of replacements
+system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use
+system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 3563.824259 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.870074 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 22855241 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits 3882 # number of SwapReq hits
+system.cpu.dcache.demand_hits 104182818 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 104182818 # number of overall hits
+system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 46710 # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses 4 # number of SwapReq misses
+system.cpu.dcache.demand_misses 939567 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 939567 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 12508482000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 1265712000 # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency 98000 # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency 13774194000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 13774194000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.002040 # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate 0.001029 # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate 0.008938 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.008938 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 14009.502082 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 27097.238279 # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency 24500 # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 14660.150899 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 14660.150899 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 935237 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 46710 # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses 4 # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 939567 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 939567 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 9829911000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 1125582000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency 86000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 10955493000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 10955493000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.002040 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.001029 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.008938 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.008938 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.502082 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24097.238279 # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 21500 # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 865 # number of replacements
+system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1585884 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 375.506440 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 8861.245791 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.011460 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.270424 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 892658 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 935237 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 32147 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 924805 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 924805 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 1081 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 14567 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 15648 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 15648 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 56212000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 757484000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 813696000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 813696000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 935237 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.001210 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.311834 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.016639 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.016639 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 40 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 1081 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 14567 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 15648 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 15648 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 43240000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 582680000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 625920000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 625920000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001210 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.311834 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.016639 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.016639 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
new file mode 100644
index 000000000..c0a21768c
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -0,0 +1,536 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+needsTSO=true
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+store_set_clear_period=250000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
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+[system.cpu.itb]
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+[system.cpu.l2cache]
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+[system.cpu.tracer]
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+[system.cpu.workload]
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+max_stack_size=67108864
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+[system.membus]
+type=Bus
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+[system.physmem]
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+file=
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+range=0:268435455
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+port=system.membus.port[1]
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diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out
@@ -0,0 +1,999 @@
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diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
new file mode 100755
index 000000000..7ce56ed7f
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -0,0 +1,28 @@
+Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 28 2012 12:11:40
+gem5 started Jan 28 2012 12:12:43
+gem5 executing on ribera.cs.wisc.edu
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 70097938500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..741105f40
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -0,0 +1,486 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.070098 # Number of seconds simulated
+sim_ticks 70097938500 # Number of ticks simulated
+final_tick 70097938500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 110386 # Simulator instruction rate (inst/s)
+host_tick_rate 27814669 # Simulator tick rate (ticks/s)
+host_mem_usage 379416 # Number of bytes of host memory used
+host_seconds 2520.18 # Real time elapsed on the host
+sim_insts 278192519 # Number of instructions simulated
+system.physmem.bytes_read 3896128 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 65152 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 892416 # Number of bytes written to this memory
+system.physmem.num_reads 60877 # Number of read requests responded to by this memory
+system.physmem.num_writes 13944 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 55581207 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 929442 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 12730988 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 68312194 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls 444 # Number of system calls
+system.cpu.numCycles 140195878 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.BPredUnit.lookups 37928407 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 37928407 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1334678 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 33548417 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 33040245 # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 29060209 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 203598338 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 37928407 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 33040245 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 63274026 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 10249926 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 38189577 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 77 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 28245503 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 214193 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 139407654 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.577879 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.292775 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 78584615 56.37% 56.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3556242 2.55% 58.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2802198 2.01% 60.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 4529245 3.25% 64.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 6913485 4.96% 69.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 5169478 3.71% 72.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 7697084 5.52% 78.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 4298531 3.08% 81.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 25856776 18.55% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 139407654 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.270539 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.452242 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 41988791 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 28417024 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 52030953 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 8087139 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 8883747 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 355040007 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 8883747 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 48483810 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4810408 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 9079 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 52929871 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 24290739 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 350051728 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 20 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 103496 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 20366187 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 314282471 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 860902327 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 860897388 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 4939 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 65938279 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 478 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 472 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 57634584 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 112617334 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 37601195 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 47838969 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 8379867 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 343415839 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2328 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 316096096 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 78808 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 65029362 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 92942153 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1882 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 139407654 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.267423 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.745481 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 32098361 23.02% 23.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 17868067 12.82% 35.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 24417482 17.52% 53.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 32093883 23.02% 76.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 18421218 13.21% 89.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 9527374 6.83% 96.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 3128162 2.24% 98.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1804154 1.29% 99.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 48953 0.04% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 139407654 # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 25731 1.31% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1863505 95.00% 96.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 72393 3.69% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 180196286 57.01% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 342 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 101438567 32.09% 89.10% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 34444190 10.90% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total 316096096 # Type of FU issued
+system.cpu.iq.rate 2.254675 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1961629 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006206 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 773638738 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 408477370 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 312370165 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1545 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 3169 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 656 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 318040246 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 768 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 52318776 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads 21837946 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 139826 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 33737 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 6161444 # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads 3258 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 3821 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles 8883747 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 984872 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 88741 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 343418167 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 39651 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 112617334 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 37601195 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1341 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 42673 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 33737 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1237180 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 215729 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1452909 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 313907375 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 100815222 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2188721 # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp 0 # number of swp insts executed
+system.cpu.iew.exec_nop 0 # number of nop insts executed
+system.cpu.iew.exec_refs 134855811 # number of memory reference insts executed
+system.cpu.iew.exec_branches 31730666 # Number of branches executed
+system.cpu.iew.exec_stores 34040589 # Number of stores executed
+system.cpu.iew.exec_rate 2.239063 # Inst execution rate
+system.cpu.iew.wb_sent 313087219 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 312370821 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 231825034 # num instructions producing a value
+system.cpu.iew.wb_consumers 317282535 # num instructions consuming a value
+system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate 2.228103 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.730658 # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 65229233 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 1334689 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 130523907 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.131353 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.650695 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 49374885 37.83% 37.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 24990571 19.15% 56.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 17165469 13.15% 70.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 12454302 9.54% 79.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 3472302 2.66% 82.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 3453203 2.65% 84.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 2713996 2.08% 87.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1124527 0.86% 87.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 15774652 12.09% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 130523907 # Number of insts commited each cycle
+system.cpu.commit.count 278192519 # Number of instructions committed
+system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.refs 122219139 # Number of memory references committed
+system.cpu.commit.loads 90779388 # Number of loads committed
+system.cpu.commit.membars 0 # Number of memory barriers committed
+system.cpu.commit.branches 29309710 # Number of branches committed
+system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
+system.cpu.commit.function_calls 0 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 15774652 # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads 458171007 # The number of ROB reads
+system.cpu.rob.rob_writes 695745355 # The number of ROB writes
+system.cpu.timesIdled 23904 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 788224 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 278192519 # Number of Instructions Simulated
+system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
+system.cpu.cpi 0.503953 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.503953 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.984313 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.984313 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 554439426 # number of integer regfile reads
+system.cpu.int_regfile_writes 279882097 # number of integer regfile writes
+system.cpu.fp_regfile_reads 791 # number of floating regfile reads
+system.cpu.fp_regfile_writes 562 # number of floating regfile writes
+system.cpu.misc_regfile_reads 200975844 # number of misc regfile reads
+system.cpu.icache.replacements 62 # number of replacements
+system.cpu.icache.tagsinuse 823.089414 # Cycle average of tags in use
+system.cpu.icache.total_refs 28244206 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 1023 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 27609.194526 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 823.089414 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.401899 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 28244206 # number of ReadReq hits
+system.cpu.icache.demand_hits 28244206 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 28244206 # number of overall hits
+system.cpu.icache.ReadReq_misses 1297 # number of ReadReq misses
+system.cpu.icache.demand_misses 1297 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 1297 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 46884000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 46884000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 46884000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 28245503 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 28245503 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 28245503 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 36148.033924 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 36148.033924 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 36148.033924 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits 273 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits 273 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 273 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 1024 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 1024 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 1024 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 36044000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 36044000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 36044000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35199.218750 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35199.218750 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35199.218750 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 2072801 # number of replacements
+system.cpu.dcache.tagsinuse 4073.016957 # Cycle average of tags in use
+system.cpu.dcache.total_refs 77487718 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2076897 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 37.309370 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 23652058000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4073.016957 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.994389 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 46133976 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 31353733 # number of WriteReq hits
+system.cpu.dcache.demand_hits 77487709 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 77487709 # number of overall hits
+system.cpu.dcache.ReadReq_misses 2288597 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 86018 # number of WriteReq misses
+system.cpu.dcache.demand_misses 2374615 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 2374615 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 13760644500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 1501321288 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 15261965788 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 15261965788 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 48422573 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 79862324 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 79862324 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.047263 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.002736 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.029734 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.029734 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 6012.698828 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 17453.571206 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 6427.132730 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 6427.132730 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 1880524 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits 293812 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits 3902 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits 297714 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 297714 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 1994785 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 82116 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 2076901 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 2076901 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 5560782500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 1157739288 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 6718521788 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 6718521788 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.041195 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.002612 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.026006 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.026006 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2787.660074 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14098.827123 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 3234.878209 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 3234.878209 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 33248 # number of replacements
+system.cpu.l2cache.tagsinuse 18948.902283 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 3764067 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 61254 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 61.450142 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 6031.150094 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 12917.752189 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.184056 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.394219 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 1964318 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 1880524 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 52728 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 2017046 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 2017046 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 31362 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses 29515 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 60877 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 60877 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 1071112000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 1006258500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 2077370500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 2077370500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 1995680 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 1880524 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 82243 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 2077923 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 2077923 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.015715 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.358876 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.029297 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.029297 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34153.179006 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34093.122141 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34124.061632 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34124.061632 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 13944 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 31362 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 29515 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 60877 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 60877 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 972890000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 914988000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 1887878000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 1887878000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.015715 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.358876 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.029297 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.029297 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.299662 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.779265 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31011.350756 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31011.350756 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..96706c5cc
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
@@ -0,0 +1,999 @@
+()
+500
+()
+499
+()
+498
+()
+496
+()
+495
+()
+494
+()
+493
+()
+492
+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
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+()
+473
+()
+472
+()
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+()
+469
+()
+468
+()
+467
+()
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+()
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+()
+464
+()
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+()
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+()
+461
+()
+460
+()
+459
+()
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+()
+457
+()
+455
+()
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+()
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+()
+451
+()
+450
+()
+449
+()
+448
+()
+446
+()
+445
+()
+444
+()
+443
+()
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diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
new file mode 100755
index 000000000..eb189c10a
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:52:52
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 168950072000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..e99e16cd0
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
@@ -0,0 +1,45 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.168950 # Number of seconds simulated
+sim_ticks 168950072000 # Number of ticks simulated
+final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2042288 # Simulator instruction rate (inst/s)
+host_tick_rate 1240309006 # Simulator tick rate (ticks/s)
+host_mem_usage 339312 # Number of bytes of host memory used
+host_seconds 136.22 # Real time elapsed on the host
+sim_insts 278192520 # Number of instructions simulated
+system.physmem.bytes_read 2458815679 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 1741569664 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 243173115 # Number of bytes written to this memory
+system.physmem.num_reads 308475658 # Number of read requests responded to by this memory
+system.physmem.num_writes 31439751 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 14553504772 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 10308191310 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1439319393 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 15992824164 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls 444 # Number of system calls
+system.cpu.numCycles 337900145 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 278192520 # Number of instructions executed
+system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
+system.cpu.num_int_insts 278186228 # number of integer instructions
+system.cpu.num_fp_insts 40 # number of float instructions
+system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read
+system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
+system.cpu.num_mem_refs 122219139 # number of memory refs
+system.cpu.num_load_insts 90779388 # Number of load instructions
+system.cpu.num_store_insts 31439751 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 337900145 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
new file mode 100644
index 000000000..008adeebb
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=X86TLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=X86TLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+gid=100
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
new file mode 100644
index 000000000..095132477
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
@@ -0,0 +1,999 @@
+()
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diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
new file mode 100755
index 000000000..ac4ad20a5
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
@@ -0,0 +1,4 @@
+warn: Sockets disabled, not accepting gdb connections
+warn: instruction 'fnstcw_Mw' unimplemented
+warn: instruction 'fldcw_Mw' unimplemented
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
new file mode 100755
index 000000000..e89b51a20
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:55:19
+gem5 executing on zizzer
+command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 370010840000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..59ae818d2
--- /dev/null
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -0,0 +1,234 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.370011 # Number of seconds simulated
+sim_ticks 370010840000 # Number of ticks simulated
+final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1163147 # Simulator instruction rate (inst/s)
+host_tick_rate 1547047043 # Simulator tick rate (ticks/s)
+host_mem_usage 348152 # Number of bytes of host memory used
+host_seconds 239.17 # Real time elapsed on the host
+sim_insts 278192520 # Number of instructions simulated
+system.physmem.bytes_read 4900800 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 1885440 # Number of bytes written to this memory
+system.physmem.num_reads 76575 # Number of read requests responded to by this memory
+system.physmem.num_writes 29460 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 13245017 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 139758 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 5095634 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 18340652 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.workload.num_syscalls 444 # Number of system calls
+system.cpu.numCycles 740021680 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 278192520 # Number of instructions executed
+system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
+system.cpu.num_func_calls 0 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
+system.cpu.num_int_insts 278186228 # number of integer instructions
+system.cpu.num_fp_insts 40 # number of float instructions
+system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read
+system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
+system.cpu.num_mem_refs 122219139 # number of memory refs
+system.cpu.num_load_insts 90779388 # Number of load instructions
+system.cpu.num_store_insts 31439751 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 740021680 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 24 # number of replacements
+system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use
+system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits
+system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 217695401 # number of overall hits
+system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses
+system.cpu.icache.demand_misses 808 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 808 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 2062733 # number of replacements
+system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use
+system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits
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+system.cpu.dcache.overall_hits 120152372 # number of overall hits
+system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses
+system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 2066829 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 3268793000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses
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+system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.003375 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 1437080 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.016911 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 49212 # number of replacements
+system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits 63651 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 1991062 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses 42458 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 76575 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency 1774084000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses 1437080 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks 29460 # number of writebacks
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/test.py b/tests/long/se/10.mcf/test.py
new file mode 100644
index 000000000..9bd18a83f
--- /dev/null
+++ b/tests/long/se/10.mcf/test.py
@@ -0,0 +1,34 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Korey Sewell
+
+m5.util.addToPath('../configs/common')
+from cpu2000 import mcf
+
+workload = mcf(isa, opsys, 'smred')
+root.system.cpu.workload = workload.makeLiveProcess()
+root.system.physmem.range=AddrRange('256MB')