diff options
Diffstat (limited to 'tests/long/se/10.mcf')
3 files changed, 59 insertions, 57 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini index cdddacd16..3938653f4 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini @@ -111,7 +111,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.branchPred] -type=BranchPredictor +type=TournamentBP BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -125,7 +125,6 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament [system.cpu.dcache] type=BaseCache @@ -137,7 +136,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -148,7 +147,6 @@ size=262144 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -597,7 +595,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -608,7 +606,6 @@ size=131072 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -708,7 +705,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -719,7 +716,6 @@ size=2097152 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -763,9 +759,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false max_stack_size=67108864 output=cout diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 698e8108f..a092bf499 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -158,7 +158,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -169,7 +169,6 @@ size=32768 system=system tags=system.cpu.dcache.tags tgts_per_mshr=8 -two_queue=false write_buffers=16 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -241,9 +240,9 @@ opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList1] type=FUDesc @@ -255,23 +254,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste [system.cpu.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=IntDiv opLat=12 +pipelined=false [system.cpu.fuPool.FUList1.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=IprAccess opLat=3 +pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc @@ -283,9 +282,9 @@ opList=system.cpu.fuPool.FUList2.opList [system.cpu.fuPool.FUList2.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=2 +pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc @@ -297,9 +296,9 @@ opList=system.cpu.fuPool.FUList3.opList [system.cpu.fuPool.FUList3.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=2 +pipelined=true [system.cpu.fuPool.FUList4] type=FUDesc @@ -311,184 +310,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys [system.cpu.fuPool.FUList4.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=9 +pipelined=true [system.cpu.fuPool.FUList4.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList4.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=9 +pipelined=true [system.cpu.fuPool.FUList4.opList20] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList21] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList22] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList23] type=OpDesc eventq_index=0 -issueLat=9 opClass=FloatDiv opLat=9 +pipelined=false [system.cpu.fuPool.FUList4.opList24] type=OpDesc eventq_index=0 -issueLat=33 opClass=FloatSqrt opLat=33 +pipelined=false [system.cpu.fuPool.FUList4.opList25] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu.icache] type=BaseCache @@ -500,7 +499,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -511,7 +510,6 @@ size=32768 system=system tags=system.cpu.icache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -611,7 +609,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -622,7 +620,6 @@ size=1048576 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini index e9a50bebb..263d31358 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -23,6 +23,7 @@ load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem +mmap_using_noreserve=false num_work_ids=16 readfile= symbolfile= @@ -82,10 +83,11 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -96,7 +98,6 @@ size=262144 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -122,10 +123,11 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -136,7 +138,6 @@ size=131072 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -170,10 +171,11 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -184,7 +186,6 @@ size=2097152 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -203,8 +204,11 @@ size=2097152 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 @@ -219,6 +223,7 @@ eventq_index=0 type=LiveProcess cmd=mcf mcf.in cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing +drivers= egid=100 env= errout=cerr @@ -227,6 +232,7 @@ eventq_index=0 executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +kvmInSE=false max_stack_size=67108864 output=cout pid=100 @@ -256,11 +262,14 @@ transition_latency=100000000 type=CoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side |