diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index d4b67bdd9..aa609094f 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.412080 # Nu sim_ticks 412079966500 # Number of ticks simulated final_tick 412079966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240872 # Simulator instruction rate (inst/s) -host_op_rate 240872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162212982 # Simulator tick rate (ticks/s) -host_mem_usage 251076 # Number of bytes of host memory used -host_seconds 2540.36 # Real time elapsed on the host +host_inst_rate 523017 # Simulator instruction rate (inst/s) +host_op_rate 523017 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 352221098 # Simulator tick rate (ticks/s) +host_mem_usage 299640 # Number of bytes of host memory used +host_seconds 1169.95 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 156608 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24143296 # Number of bytes read from this memory system.physmem.bytes_read::total 24299904 # Number of bytes read from this memory @@ -282,6 +283,7 @@ system.physmem_1.memoryStateTime::REF 13760240000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 73580458750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 123917421 # Number of BP lookups system.cpu.branchPred.condPredicted 87658943 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 6214661 # Number of conditional branches incorrect @@ -329,6 +331,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 412079966500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 824159933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -375,6 +378,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 611901617 # Class of committed instruction system.cpu.tickCycles 739333991 # Number of cycles that the object actually ticked system.cpu.idleCycles 84825942 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2535268 # number of replacements system.cpu.dcache.tags.tagsinuse 4087.644038 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 202570428 # Total number of references to valid blocks. @@ -392,6 +396,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 414584966 # Number of tag accesses system.cpu.dcache.tags.data_accesses 414584966 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 146904269 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 146904269 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 55666159 # number of WriteReq hits @@ -488,6 +493,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.814661 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22270.814661 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3158 # number of replacements system.cpu.icache.tags.tagsinuse 1117.678366 # Cycle average of tags in use system.cpu.icache.tags.total_refs 226045682 # Total number of references to valid blocks. @@ -506,6 +512,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 452106322 # Number of tag accesses system.cpu.icache.tags.data_accesses 452106322 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 226045682 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 226045682 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 226045682 # number of demand (read+write) hits @@ -574,6 +581,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45856.899318 system.cpu.icache.demand_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45856.899318 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 347705 # number of replacements system.cpu.l2cache.tags.tagsinuse 29504.977164 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3908748 # Total number of references to valid blocks. @@ -596,6 +604,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18756 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989685 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 41820503 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 41820503 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2339413 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2339413 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3158 # number of WritebackClean hits @@ -742,6 +751,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 2394 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2394 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1766190 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2633020 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3158 # Transaction distribution @@ -774,6 +784,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 7479000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3809046000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 173378 # Transaction distribution system.membus.trans_dist::WritebackDirty 293607 # Transaction distribution system.membus.trans_dist::CleanEvict 51709 # Transaction distribution |