diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt | 946 |
1 files changed, 480 insertions, 466 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 63d0e7cc1..70e92b094 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.361826 # Number of seconds simulated -sim_ticks 361826015500 # Number of ticks simulated -final_tick 361826015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.361881 # Number of seconds simulated +sim_ticks 361880862500 # Number of ticks simulated +final_tick 361880862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 231274 # Simulator instruction rate (inst/s) -host_op_rate 250500 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 165186980 # Simulator tick rate (ticks/s) -host_mem_usage 321304 # Number of bytes of host memory used -host_seconds 2190.40 # Real time elapsed on the host +host_inst_rate 239591 # Simulator instruction rate (inst/s) +host_op_rate 259509 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171154005 # Simulator tick rate (ticks/s) +host_mem_usage 311472 # Number of bytes of host memory used +host_seconds 2114.36 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 9220736 # Number of bytes read from this memory -system.physmem.bytes_read::total 9220736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6177024 # Number of bytes written to this memory -system.physmem.bytes_written::total 6177024 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 144074 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144074 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96516 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96516 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25483894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25483894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 612007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 612007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17071807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17071807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17071807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25483894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42555702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144074 # Number of read requests accepted -system.physmem.writeReqs 96516 # Number of write requests accepted -system.physmem.readBursts 144074 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96516 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9213952 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue -system.physmem.bytesWritten 6175488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9220736 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6177024 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 9221824 # Number of bytes read from this memory +system.physmem.bytes_read::total 9221824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6177344 # Number of bytes written to this memory +system.physmem.bytes_written::total 6177344 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 144091 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144091 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96521 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96521 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25483039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25483039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 612622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 612622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17070104 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17070104 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17070104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25483039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42553143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144091 # Number of read requests accepted +system.physmem.writeReqs 96521 # Number of write requests accepted +system.physmem.readBursts 144091 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96521 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9215168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue +system.physmem.bytesWritten 6176128 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9221824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6177344 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9331 # Per bank write bursts -system.physmem.perBankRdBursts::1 8974 # Per bank write bursts -system.physmem.perBankRdBursts::2 8995 # Per bank write bursts -system.physmem.perBankRdBursts::3 8704 # Per bank write bursts +system.physmem.perBankRdBursts::0 9338 # Per bank write bursts +system.physmem.perBankRdBursts::1 8967 # Per bank write bursts +system.physmem.perBankRdBursts::2 9003 # Per bank write bursts +system.physmem.perBankRdBursts::3 8705 # Per bank write bursts system.physmem.perBankRdBursts::4 9445 # Per bank write bursts -system.physmem.perBankRdBursts::5 9338 # Per bank write bursts -system.physmem.perBankRdBursts::6 8941 # Per bank write bursts -system.physmem.perBankRdBursts::7 8096 # Per bank write bursts -system.physmem.perBankRdBursts::8 8562 # Per bank write bursts -system.physmem.perBankRdBursts::9 8674 # Per bank write bursts +system.physmem.perBankRdBursts::5 9343 # Per bank write bursts +system.physmem.perBankRdBursts::6 8943 # Per bank write bursts +system.physmem.perBankRdBursts::7 8100 # Per bank write bursts +system.physmem.perBankRdBursts::8 8560 # Per bank write bursts +system.physmem.perBankRdBursts::9 8672 # Per bank write bursts system.physmem.perBankRdBursts::10 8773 # Per bank write bursts -system.physmem.perBankRdBursts::11 9481 # Per bank write bursts -system.physmem.perBankRdBursts::12 9368 # Per bank write bursts -system.physmem.perBankRdBursts::13 9509 # Per bank write bursts -system.physmem.perBankRdBursts::14 8709 # Per bank write bursts -system.physmem.perBankRdBursts::15 9068 # Per bank write bursts -system.physmem.perBankWrBursts::0 6188 # Per bank write bursts -system.physmem.perBankWrBursts::1 6094 # Per bank write bursts -system.physmem.perBankWrBursts::2 6004 # Per bank write bursts -system.physmem.perBankWrBursts::3 5817 # Per bank write bursts -system.physmem.perBankWrBursts::4 6158 # Per bank write bursts -system.physmem.perBankWrBursts::5 6168 # Per bank write bursts -system.physmem.perBankWrBursts::6 6012 # Per bank write bursts -system.physmem.perBankWrBursts::7 5489 # Per bank write bursts -system.physmem.perBankWrBursts::8 5725 # Per bank write bursts -system.physmem.perBankWrBursts::9 5819 # Per bank write bursts +system.physmem.perBankRdBursts::11 9480 # Per bank write bursts +system.physmem.perBankRdBursts::12 9371 # Per bank write bursts +system.physmem.perBankRdBursts::13 9512 # Per bank write bursts +system.physmem.perBankRdBursts::14 8706 # Per bank write bursts +system.physmem.perBankRdBursts::15 9069 # Per bank write bursts +system.physmem.perBankWrBursts::0 6189 # Per bank write bursts +system.physmem.perBankWrBursts::1 6093 # Per bank write bursts +system.physmem.perBankWrBursts::2 6008 # Per bank write bursts +system.physmem.perBankWrBursts::3 5816 # Per bank write bursts +system.physmem.perBankWrBursts::4 6159 # Per bank write bursts +system.physmem.perBankWrBursts::5 6173 # Per bank write bursts +system.physmem.perBankWrBursts::6 6014 # Per bank write bursts +system.physmem.perBankWrBursts::7 5494 # Per bank write bursts +system.physmem.perBankWrBursts::8 5724 # Per bank write bursts +system.physmem.perBankWrBursts::9 5818 # Per bank write bursts system.physmem.perBankWrBursts::10 5961 # Per bank write bursts -system.physmem.perBankWrBursts::11 6448 # Per bank write bursts -system.physmem.perBankWrBursts::12 6304 # Per bank write bursts -system.physmem.perBankWrBursts::13 6266 # Per bank write bursts -system.physmem.perBankWrBursts::14 5996 # Per bank write bursts -system.physmem.perBankWrBursts::15 6043 # Per bank write bursts +system.physmem.perBankWrBursts::11 6447 # Per bank write bursts +system.physmem.perBankWrBursts::12 6306 # Per bank write bursts +system.physmem.perBankWrBursts::13 6267 # Per bank write bursts +system.physmem.perBankWrBursts::14 5992 # Per bank write bursts +system.physmem.perBankWrBursts::15 6041 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 361825986500 # Total gap between requests +system.physmem.totGap 361880833500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144074 # Read request sizes (log2) +system.physmem.readPktSize::6 144091 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96516 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96521 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 348 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,38 +140,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -189,59 +189,51 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64715 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.790435 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 157.392081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 243.201287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24444 37.77% 37.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18161 28.06% 65.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6768 10.46% 76.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7845 12.12% 88.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2212 3.42% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1114 1.72% 93.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 793 1.23% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 596 0.92% 95.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2782 4.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64715 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.855065 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.360630 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5564 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 64681 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.949073 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 157.463319 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 243.404639 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24397 37.72% 37.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18169 28.09% 65.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6808 10.53% 76.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7802 12.06% 88.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2168 3.35% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1166 1.80% 93.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 777 1.20% 94.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 613 0.95% 95.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2781 4.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64681 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5584 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.784921 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 381.788967 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5580 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.329741 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.226111 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.490816 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2624 47.13% 47.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2801 50.31% 97.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 48 0.86% 98.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 25 0.45% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 21 0.38% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 12 0.22% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 8 0.14% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 6 0.11% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 3 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 4 0.07% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 5 0.09% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-69 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-81 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads -system.physmem.totQLat 1536727500 # Total ticks spent queuing -system.physmem.totMemAccLat 4236127500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 719840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10674.09 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5584 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5584 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.281877 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.171400 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.885179 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5428 97.21% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 84 1.50% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 28 0.50% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 20 0.36% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 9 0.16% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 7 0.13% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 2 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5584 # Writes before turning the bus around for reads +system.physmem.totQLat 1580318000 # Total ticks spent queuing +system.physmem.totMemAccLat 4280074250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 719935000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10975.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29424.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29725.42 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.46 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 17.07 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 25.48 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 17.07 # Average system write bandwidth in MiByte/s @@ -250,44 +242,52 @@ system.physmem.busUtil 0.33 # Da system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing -system.physmem.readRowHits 111270 # Number of row buffer hits during reads -system.physmem.writeRowHits 64468 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes -system.physmem.avgGap 1503911.16 # Average gap between requests -system.physmem.pageHitRate 73.08 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 254085865250 # Time in different power states -system.physmem.memoryStateTime::REF 12081940000 # Time in different power states +system.physmem.avgWrQLen 20.42 # Average write queue length when enqueuing +system.physmem.readRowHits 111153 # Number of row buffer hits during reads +system.physmem.writeRowHits 64649 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.98 # Row buffer hit rate for writes +system.physmem.avgGap 1504001.60 # Average gap between requests +system.physmem.pageHitRate 73.10 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 254039828500 # Time in different power states +system.physmem.memoryStateTime::REF 12083760000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 95653103250 # Time in different power states +system.physmem.memoryStateTime::ACT 95752175500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 42555702 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 43212 # Transaction distribution -system.membus.trans_dist::ReadResp 43212 # Transaction distribution -system.membus.trans_dist::Writeback 96516 # Transaction distribution -system.membus.trans_dist::ReadExReq 100862 # Transaction distribution -system.membus.trans_dist::ReadExResp 100862 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 384664 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15397760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15397760 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15397760 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1075054000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 43225 # Transaction distribution +system.membus.trans_dist::ReadResp 43225 # Transaction distribution +system.membus.trans_dist::Writeback 96521 # Transaction distribution +system.membus.trans_dist::ReadExReq 100866 # Transaction distribution +system.membus.trans_dist::ReadExResp 100866 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384703 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384703 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15399168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15399168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 240612 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 240612 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 240612 # Request fanout histogram +system.membus.reqLayer0.occupancy 1075136000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1362559750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1362650250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 132256489 # Number of BP lookups -system.cpu.branchPred.condPredicted 98266035 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6550672 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68852239 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64692489 # Number of BTB hits +system.cpu.branchPred.lookups 132262855 # Number of BP lookups +system.cpu.branchPred.condPredicted 98270441 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6551317 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68771118 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64694090 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.958439 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9992276 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17882 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.071598 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9992883 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17801 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -373,71 +373,71 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 723652031 # number of cpu cycles simulated +system.cpu.numCycles 723761725 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582155 # Number of instructions committed system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed -system.cpu.discardedOps 14122871 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 14127209 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.428499 # CPI: cycles per instruction -system.cpu.ipc 0.700036 # IPC: instructions per cycle -system.cpu.tickCycles 687771211 # Number of cycles that the object actually ticked -system.cpu.idleCycles 35880820 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 17660 # number of replacements -system.cpu.icache.tags.tagsinuse 1187.686040 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200323378 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19531 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10256.688239 # Average number of references to valid blocks. +system.cpu.cpi 1.428715 # CPI: cycles per instruction +system.cpu.ipc 0.699929 # IPC: instructions per cycle +system.cpu.tickCycles 687792337 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35969388 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 17682 # number of replacements +system.cpu.icache.tags.tagsinuse 1187.679119 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 200328523 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19553 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10245.411088 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1187.686040 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.579925 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.579925 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1187.679119 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579921 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 304 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 400705349 # Number of tag accesses -system.cpu.icache.tags.data_accesses 400705349 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 200323378 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 200323378 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 200323378 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 200323378 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 200323378 # number of overall hits -system.cpu.icache.overall_hits::total 200323378 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19531 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19531 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19531 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19531 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19531 # number of overall misses -system.cpu.icache.overall_misses::total 19531 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 466485747 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 466485747 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 466485747 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 466485747 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 466485747 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 466485747 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 200342909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 200342909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 200342909 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 200342909 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 200342909 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 200342909 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23884.375966 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23884.375966 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23884.375966 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23884.375966 # average overall miss latency +system.cpu.icache.tags.tag_accesses 400715705 # Number of tag accesses +system.cpu.icache.tags.data_accesses 400715705 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 200328523 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 200328523 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 200328523 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 200328523 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 200328523 # number of overall hits +system.cpu.icache.overall_hits::total 200328523 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19553 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19553 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19553 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19553 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19553 # number of overall misses +system.cpu.icache.overall_misses::total 19553 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 468017498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 468017498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 468017498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 468017498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 468017498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 468017498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 200348076 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 200348076 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 200348076 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 200348076 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 200348076 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 200348076 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000098 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000098 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000098 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000098 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000098 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000098 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23935.840945 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23935.840945 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23935.840945 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23935.840945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23935.840945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23935.840945 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,122 +446,136 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19531 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 19531 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 19531 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 19531 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 19531 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 19531 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426041253 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 426041253 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426041253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 426041253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426041253 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 426041253 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21813.591368 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21813.591368 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19553 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 19553 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 19553 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 19553 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 19553 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 19553 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 427542502 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 427542502 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 427542502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 427542502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 427542502 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 427542502 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21865.826318 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21865.826318 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21865.826318 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21865.826318 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21865.826318 # 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Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3355897 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3395003 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1251392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141578176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142829568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2231712 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2231712 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2231712 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2184277000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29987747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30013998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744465986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1744433986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 111319 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27632.304905 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1684536 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 142508 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.820642 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 162493519500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23524.678269 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4107.626636 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.717916 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125355 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.843271 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 111337 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27632.941712 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1684357 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 142526 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 11.817893 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 162521333500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23524.774692 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4108.167019 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.717919 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125371 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.843290 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4925 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25872 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4930 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25866 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18352389 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18352389 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 763644 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 763644 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 18352622 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18352622 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 763650 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 763650 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1068421 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1068421 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.283008 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123867 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123867 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123867 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123867 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74511.369945 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74511.369945 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71051.007813 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71051.007813 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72089.140468 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72089.140468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72089.140468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72089.140468 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356400 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356400 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1163291 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1163291 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1163291 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1163291 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.053590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283013 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72389.176098 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72389.176098 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -570,120 +584,120 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 96516 # number of writebacks -system.cpu.l2cache.writebacks::total 96516 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 96521 # number of writebacks +system.cpu.l2cache.writebacks::total 96521 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58387.948385 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58387.948385 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59427.774963 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59427.774963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59427.774963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59427.774963 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43225 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 43225 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100866 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100866 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 144091 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144091 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 144091 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144091 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2672436250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2672436250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5933940000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5933940000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8606376250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8606376250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8606376250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8606376250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283013 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283013 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123865 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123865 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123865 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123865 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61826.171197 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61826.171197 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58829.932782 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58829.932782 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59728.756480 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59728.756480 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59728.756480 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59728.756480 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1139638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.125159 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169305637 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143734 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 148.028857 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1139642 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.128930 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169306917 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143738 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 148.029459 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4807181250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.125159 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993927 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993927 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.128930 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993928 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993928 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3499 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 342864800 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 342864800 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 112789835 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 112789835 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 53538720 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538720 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 342867294 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 342867294 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 112791129 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 112791129 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 53538706 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538706 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 166328555 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166328555 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 166328555 # number of overall hits -system.cpu.dcache.overall_hits::total 166328555 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 854310 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854310 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 700586 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700586 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 1554896 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1554896 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1554896 # number of overall misses -system.cpu.dcache.overall_misses::total 1554896 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13696134233 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13696134233 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20619900500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20619900500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 34316034733 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34316034733 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 34316034733 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34316034733 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 113644145 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 113644145 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.inst 166329835 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166329835 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 166329835 # number of overall hits +system.cpu.dcache.overall_hits::total 166329835 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 854261 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854261 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 700600 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700600 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 1554861 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1554861 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 1554861 # number of overall misses +system.cpu.dcache.overall_misses::total 1554861 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13692452733 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13692452733 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20709081750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20709081750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 34401534483 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34401534483 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 34401534483 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34401534483 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 113645390 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 113645390 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 167883451 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167883451 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 167883451 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167883451 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.inst 167884696 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167884696 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 167884696 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167884696 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007517 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007517 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.009262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.009262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16031.808399 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16031.808399 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29432.361623 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29432.361623 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22069.665581 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22069.665581 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.inst 0.009261 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009261 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.009261 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009261 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16028.418403 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16028.418403 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29559.066158 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29559.066158 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22125.151048 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22125.151048 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22125.151048 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22125.151048 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -694,30 +708,30 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1068421 # number of writebacks system.cpu.dcache.writebacks::total 1068421 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66718 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66718 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344444 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344444 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 411162 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411162 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 411162 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411162 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787592 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787592 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356142 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356142 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1143734 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1143734 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1143734 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1143734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11245323264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11245323264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10075452250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10075452250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21320775514 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21320775514 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21320775514 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21320775514 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66670 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66670 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344453 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344453 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 411123 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411123 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 411123 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411123 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787591 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787591 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356147 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356147 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1143738 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1143738 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1143738 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1143738 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11243518014 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11243518014 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10120311000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10120311000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21363829014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21363829014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21363829014 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21363829014 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006930 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006930 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses @@ -726,14 +740,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006813 system.cpu.dcache.demand_mshr_miss_rate::total 0.006813 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006813 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.107528 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.107528 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28290.547731 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28290.547731 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14275.833541 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14275.833541 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28416.106271 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28416.106271 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18678.953584 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18678.953584 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18678.953584 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18678.953584 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |