diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt | 236 |
1 files changed, 121 insertions, 115 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 7568a8b98..ad7524f92 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.707533 # Number of seconds simulated -sim_ticks 707533448500 # Number of ticks simulated -final_tick 707533448500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.707537 # Number of seconds simulated +sim_ticks 707536959500 # Number of ticks simulated +final_tick 707536959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1147583 # Simulator instruction rate (inst/s) -host_op_rate 1242781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1607870578 # Simulator tick rate (ticks/s) -host_mem_usage 316160 # Number of bytes of host memory used -host_seconds 440.04 # Real time elapsed on the host +host_inst_rate 1064510 # Simulator instruction rate (inst/s) +host_op_rate 1152817 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1491485099 # Simulator tick rate (ticks/s) +host_mem_usage 319084 # Number of bytes of host memory used +host_seconds 474.38 # Real time elapsed on the host sim_insts 504986854 # Number of instructions simulated sim_ops 546878105 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 139793 # Nu system.physmem.num_reads::total 142533 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 96032 # Number of write requests responded to by this memory system.physmem.num_writes::total 96032 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 247847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12644988 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12892835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 247847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 247847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8686583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8686583 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8686583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 247847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12644988 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21579418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 247846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12644925 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12892771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 247846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 247846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8686540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8686540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8686540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 247846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12644925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21579311 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1415066897 # number of cpu cycles simulated +system.cpu.numCycles 1415073919 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986854 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 172745235 # nu system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1415066896.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1415073918.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 121548302 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695379 # Class of executed instruction system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.318183 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4065.318106 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11716394500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318183 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 11716435500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318106 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138917 # n system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817723000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11817723000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11820971000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11820971000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8866220000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8866220000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20683943000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20683943000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20683943000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20683943000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20687191000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20687191000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20687191000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20687191000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.491859 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.491859 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.641825 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.641825 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24886.936507 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 24886.936507 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18161.062659 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18161.062659 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18161.046713 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18161.046713 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18163.914491 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18163.914491 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18163.898542 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18163.898542 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11035066000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11035066000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11038314000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11038314000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509960000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509960000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19545026000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19545026000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19545080000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19545080000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19548274000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19548274000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19548328000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19548328000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -336,26 +336,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14099.491859 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14099.491859 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14103.641825 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14103.641825 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23886.936507 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23886.936507 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17161.062659 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17161.062659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17161.095004 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17161.095004 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17163.914491 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17163.914491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17163.946834 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17163.946834 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.369510 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.371232 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.369510 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480161 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480161 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.371232 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id @@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 265181000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 265181000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 265181000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 265181000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 265181000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 265181000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 265444000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 265444000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 265444000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 265444000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 265444000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 265444000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses @@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23017.186008 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23017.186008 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23017.186008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23017.186008 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23040.013888 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23040.013888 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23040.013888 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23040.013888 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,38 +415,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253660000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 253660000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253660000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 253660000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253660000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 253660000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253923000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 253923000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253923000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 253923000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253923000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 253923000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22017.186008 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22017.186008 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22040.013888 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22040.013888 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109779 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27249.065072 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 27249.077163 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1743796 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 140956 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 12.371208 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 338493397000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23345.004709 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705162 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.355202 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 338494154000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23345.006122 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705462 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.365578 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.712433 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.110362 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831575 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.110363 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831576 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id @@ -485,14 +485,14 @@ system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5292536500 system.cpu.l2cache.ReadExReq_miss_latency::total 5292536500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 144147000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 144147000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053299500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053299500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053419500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053419500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 144147000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7345836000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7489983000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7345956000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7490103000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 144147000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7345836000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7489983000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7345956000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7490103000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 1064880 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1064880 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) @@ -523,14 +523,14 @@ system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.245004 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.245004 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52608.394161 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52608.394161 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52567.831541 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52567.831541 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52570.903738 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52570.903738 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52549.114942 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52549.956852 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52549.114942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52549.956852 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -559,14 +559,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285206500 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285206500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116747000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116747000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662699500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662699500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662819500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662819500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116747000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5947906000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6064653000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5948026000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6064773000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116747000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5947906000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6064653000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5948026000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6064773000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282751 # mshr miss rate for ReadExReq accesses @@ -585,15 +585,21 @@ system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42540.245004 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42540.245004 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42608.394161 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42608.394161 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42567.831541 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42567.831541 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42570.903738 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42570.903738 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 2295049 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1144662 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3461 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2140 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2139 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1160912 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 90016 # Transaction distribution @@ -609,14 +615,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 141780416 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 109779 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 2404828 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.045649 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.208724 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.003790 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.061455 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2295049 95.44% 95.44% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 109779 4.56% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2395714 99.62% 99.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9113 0.38% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 2404828 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2212404500 # Layer occupancy (ticks) @@ -646,9 +652,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 251058 # Request fanout histogram -system.membus.reqLayer0.occupancy 643796820 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 643796492 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 719009492 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 719009164 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |