diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt | 226 |
1 files changed, 113 insertions, 113 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index f9350b670..264bc47b4 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.717366 # Nu sim_ticks 717366012000 # Number of ticks simulated final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 512177 # Simulator instruction rate (inst/s) -host_op_rate 577137 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 727580493 # Simulator tick rate (ticks/s) -host_mem_usage 234620 # Number of bytes of host memory used -host_seconds 985.96 # Real time elapsed on the host +host_inst_rate 858996 # Simulator instruction rate (inst/s) +host_op_rate 967944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1220258898 # Simulator tick rate (ticks/s) +host_mem_usage 290524 # Number of bytes of host memory used +host_seconds 587.88 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 569034839 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory @@ -177,114 +177,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1134822 # number of replacements -system.cpu.dcache.tagsinuse 4065.297446 # Cycle average of tags in use -system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.992504 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits -system.cpu.dcache.overall_hits::total 176840704 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses -system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817433000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11817433000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8864744000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8864744000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20682177000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20682177000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20682177000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20682177000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.102034 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.102034 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24882.793465 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24882.793465 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18159.496118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18159.496118 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks -system.cpu.dcache.writebacks::total 1064905 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10252117000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10252117000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8152224000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152224000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18404341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18404341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18404341000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18404341000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13099.102034 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13099.102034 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22882.793465 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22882.793465 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 109895 # number of replacements system.cpu.l2cache.tagsinuse 27243.192324 # Cycle average of tags in use system.cpu.l2cache.total_refs 1668833 # Total number of references to valid blocks. @@ -423,5 +315,113 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1134822 # number of replacements +system.cpu.dcache.tagsinuse 4065.297446 # Cycle average of tags in use +system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits +system.cpu.dcache.overall_hits::total 176840704 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses +system.cpu.dcache.overall_misses::total 1138918 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817433000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11817433000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8864744000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8864744000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20682177000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20682177000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20682177000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20682177000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.102034 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.102034 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24882.793465 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24882.793465 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18159.496118 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18159.496118 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks +system.cpu.dcache.writebacks::total 1064905 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10252117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10252117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8152224000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152224000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18404341000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18404341000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18404341000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18404341000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13099.102034 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13099.102034 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22882.793465 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22882.793465 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |