diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 0a916209d..84569a240 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.708539 # Nu sim_ticks 708539449500 # Number of ticks simulated final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 318121 # Simulator instruction rate (inst/s) -host_op_rate 344511 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 446353500 # Simulator tick rate (ticks/s) -host_mem_usage 303968 # Number of bytes of host memory used -host_seconds 1587.40 # Real time elapsed on the host +host_inst_rate 973862 # Simulator instruction rate (inst/s) +host_op_rate 1054649 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1366418821 # Simulator tick rate (ticks/s) +host_mem_usage 273224 # Number of bytes of host memory used +host_seconds 518.54 # Real time elapsed on the host sim_insts 504984064 # Number of instructions simulated sim_ops 546875315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -302,8 +302,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks system.cpu.dcache.writebacks::total 1065708 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses @@ -346,7 +344,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. @@ -407,8 +404,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 9788 # number of writebacks system.cpu.icache.writebacks::total 9788 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses @@ -435,7 +430,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 110394 # number of replacements system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. @@ -543,8 +537,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks system.cpu.l2cache.writebacks::total 96330 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses @@ -599,7 +591,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |