diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 925783e41..59b7a6f8a 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.708539 # Nu sim_ticks 708539449500 # Number of ticks simulated final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1440714 # Simulator instruction rate (inst/s) -host_op_rate 1560229 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2021455048 # Simulator tick rate (ticks/s) -host_mem_usage 314896 # Number of bytes of host memory used -host_seconds 350.51 # Real time elapsed on the host +host_inst_rate 1462928 # Simulator instruction rate (inst/s) +host_op_rate 1584286 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2052623495 # Simulator tick rate (ticks/s) +host_mem_usage 315564 # Number of bytes of host memory used +host_seconds 345.19 # Real time elapsed on the host sim_insts 504984064 # Number of instructions simulated sim_ops 546875315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory @@ -36,7 +37,9 @@ system.physmem.bw_total::writebacks 8701167 # To system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -66,6 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -95,6 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -124,6 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -154,6 +160,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 708539449500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1417078899 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -214,6 +221,7 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1136276 # number of replacements system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks. @@ -232,6 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits @@ -344,6 +353,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 9788 # number of replacements system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. @@ -362,6 +372,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits @@ -430,6 +441,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 110394 # number of replacements system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. @@ -451,6 +463,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits @@ -597,6 +610,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution @@ -629,6 +643,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 17281500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 41576 # Transaction distribution system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution system.membus.trans_dist::CleanEvict 11920 # Transaction distribution |