diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt | 685 |
1 files changed, 0 insertions, 685 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt deleted file mode 100644 index 78d65a20d..000000000 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ /dev/null @@ -1,685 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.708700 -sim_ticks 708700329500 -final_tick 708700329500 -sim_freq 1000000000000 -host_inst_rate 679420 -host_op_rate 735782 -host_tick_rate 953505845 -host_mem_usage 285772 -host_seconds 743.26 -sim_insts 504984064 -sim_ops 546875315 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.physmem.bytes_read::cpu.inst 147392 -system.physmem.bytes_read::cpu.data 8988096 -system.physmem.bytes_read::total 9135488 -system.physmem.bytes_inst_read::cpu.inst 147392 -system.physmem.bytes_inst_read::total 147392 -system.physmem.bytes_written::writebacks 6185472 -system.physmem.bytes_written::total 6185472 -system.physmem.num_reads::cpu.inst 2303 -system.physmem.num_reads::cpu.data 140439 -system.physmem.num_reads::total 142742 -system.physmem.num_writes::writebacks 96648 -system.physmem.num_writes::total 96648 -system.physmem.bw_read::cpu.inst 207975 -system.physmem.bw_read::cpu.data 12682506 -system.physmem.bw_read::total 12890481 -system.physmem.bw_inst_read::cpu.inst 207975 -system.physmem.bw_inst_read::total 207975 -system.physmem.bw_write::writebacks 8727909 -system.physmem.bw_write::total 8727909 -system.physmem.bw_total::writebacks 8727909 -system.physmem.bw_total::cpu.inst 207975 -system.physmem.bw_total::cpu.data 12682506 -system.physmem.bw_total::total 21618390 -system.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu_clk_domain.clock 500 -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.hits 0 -system.cpu.dstage2_mmu.stage2_tlb.misses 0 -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu.dtb.walker.walks 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dtb.walker.walkRequestOrigin::total 0 -system.cpu.dtb.inst_hits 0 -system.cpu.dtb.inst_misses 0 -system.cpu.dtb.read_hits 0 -system.cpu.dtb.read_misses 0 -system.cpu.dtb.write_hits 0 -system.cpu.dtb.write_misses 0 -system.cpu.dtb.flush_tlb 0 -system.cpu.dtb.flush_tlb_mva 0 -system.cpu.dtb.flush_tlb_mva_asid 0 -system.cpu.dtb.flush_tlb_asid 0 -system.cpu.dtb.flush_entries 0 -system.cpu.dtb.align_faults 0 -system.cpu.dtb.prefetch_faults 0 -system.cpu.dtb.domain_faults 0 -system.cpu.dtb.perms_faults 0 -system.cpu.dtb.read_accesses 0 -system.cpu.dtb.write_accesses 0 -system.cpu.dtb.inst_accesses 0 -system.cpu.dtb.hits 0 -system.cpu.dtb.misses 0 -system.cpu.dtb.accesses 0 -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 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