diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/arm/linux')
4 files changed, 1663 insertions, 1653 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 55f9db9e0..3a2939b58 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366439 # Number of seconds simulated -sim_ticks 366439129500 # Number of ticks simulated -final_tick 366439129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366632 # Number of seconds simulated +sim_ticks 366631719500 # Number of ticks simulated +final_tick 366631719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188596 # Simulator instruction rate (inst/s) -host_op_rate 204275 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 136422977 # Simulator tick rate (ticks/s) -host_mem_usage 271112 # Number of bytes of host memory used -host_seconds 2686.05 # Real time elapsed on the host +host_inst_rate 211005 # Simulator instruction rate (inst/s) +host_op_rate 228546 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152712719 # Simulator tick rate (ticks/s) +host_mem_usage 277288 # Number of bytes of host memory used +host_seconds 2400.79 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9028544 # Number of bytes read from this memory -system.physmem.bytes_read::total 9208384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory +system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6219648 # Number of bytes written to this memory -system.physmem.bytes_written::total 6219648 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6241792 # Number of bytes written to this memory +system.physmem.bytes_written::total 6241792 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141071 # Number of read requests responded to by this memory -system.physmem.num_reads::total 143881 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97182 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97182 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 490777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24638591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25129369 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 490777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 490777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16973209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16973209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16973209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 490777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24638591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42102578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 143881 # Number of read requests accepted -system.physmem.writeReqs 97182 # Number of write requests accepted -system.physmem.readBursts 143881 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97182 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9201344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue -system.physmem.bytesWritten 6217600 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9208384 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6219648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 141459 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144269 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 490519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24693379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25183898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 490519 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 490519 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17024692 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17024692 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17024692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 490519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24693379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42208590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144269 # Number of read requests accepted +system.physmem.writeReqs 97528 # Number of write requests accepted +system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9226688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue +system.physmem.bytesWritten 6240064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9364 # Per bank write bursts -system.physmem.perBankRdBursts::1 8912 # Per bank write bursts -system.physmem.perBankRdBursts::2 8949 # Per bank write bursts -system.physmem.perBankRdBursts::3 8655 # Per bank write bursts -system.physmem.perBankRdBursts::4 9392 # Per bank write bursts -system.physmem.perBankRdBursts::5 9355 # Per bank write bursts -system.physmem.perBankRdBursts::6 8959 # Per bank write bursts -system.physmem.perBankRdBursts::7 8100 # Per bank write bursts -system.physmem.perBankRdBursts::8 8596 # Per bank write bursts -system.physmem.perBankRdBursts::9 8629 # Per bank write bursts -system.physmem.perBankRdBursts::10 8739 # Per bank write bursts -system.physmem.perBankRdBursts::11 9451 # Per bank write bursts -system.physmem.perBankRdBursts::12 9334 # Per bank write bursts -system.physmem.perBankRdBursts::13 9512 # Per bank write bursts -system.physmem.perBankRdBursts::14 8707 # Per bank write bursts -system.physmem.perBankRdBursts::15 9117 # Per bank write bursts -system.physmem.perBankWrBursts::0 6231 # Per bank write bursts -system.physmem.perBankWrBursts::1 6102 # Per bank write bursts -system.physmem.perBankWrBursts::2 6028 # Per bank write bursts -system.physmem.perBankWrBursts::3 5879 # Per bank write bursts -system.physmem.perBankWrBursts::4 6243 # Per bank write bursts -system.physmem.perBankWrBursts::5 6239 # Per bank write bursts -system.physmem.perBankWrBursts::6 6050 # Per bank write bursts -system.physmem.perBankWrBursts::7 5507 # Per bank write bursts -system.physmem.perBankWrBursts::8 5786 # Per bank write bursts -system.physmem.perBankWrBursts::9 5859 # Per bank write bursts -system.physmem.perBankWrBursts::10 5978 # Per bank write bursts -system.physmem.perBankWrBursts::11 6493 # Per bank write bursts -system.physmem.perBankWrBursts::12 6351 # Per bank write bursts -system.physmem.perBankWrBursts::13 6319 # Per bank write bursts -system.physmem.perBankWrBursts::14 5995 # Per bank write bursts -system.physmem.perBankWrBursts::15 6090 # Per bank write bursts +system.physmem.perBankRdBursts::0 9376 # Per bank write bursts +system.physmem.perBankRdBursts::1 8929 # Per bank write bursts +system.physmem.perBankRdBursts::2 8964 # Per bank write bursts +system.physmem.perBankRdBursts::3 8666 # Per bank write bursts +system.physmem.perBankRdBursts::4 9423 # Per bank write bursts +system.physmem.perBankRdBursts::5 9371 # Per bank write bursts +system.physmem.perBankRdBursts::6 8974 # Per bank write bursts +system.physmem.perBankRdBursts::7 8126 # Per bank write bursts +system.physmem.perBankRdBursts::8 8634 # Per bank write bursts +system.physmem.perBankRdBursts::9 8697 # Per bank write bursts +system.physmem.perBankRdBursts::10 8760 # Per bank write bursts +system.physmem.perBankRdBursts::11 9487 # Per bank write bursts +system.physmem.perBankRdBursts::12 9347 # Per bank write bursts +system.physmem.perBankRdBursts::13 9550 # Per bank write bursts +system.physmem.perBankRdBursts::14 8728 # Per bank write bursts +system.physmem.perBankRdBursts::15 9135 # Per bank write bursts +system.physmem.perBankWrBursts::0 6252 # Per bank write bursts +system.physmem.perBankWrBursts::1 6118 # Per bank write bursts +system.physmem.perBankWrBursts::2 6042 # Per bank write bursts +system.physmem.perBankWrBursts::3 5901 # Per bank write bursts +system.physmem.perBankWrBursts::4 6273 # Per bank write bursts +system.physmem.perBankWrBursts::5 6263 # Per bank write bursts +system.physmem.perBankWrBursts::6 6069 # Per bank write bursts +system.physmem.perBankWrBursts::7 5534 # Per bank write bursts +system.physmem.perBankWrBursts::8 5815 # Per bank write bursts +system.physmem.perBankWrBursts::9 5920 # Per bank write bursts +system.physmem.perBankWrBursts::10 5985 # Per bank write bursts +system.physmem.perBankWrBursts::11 6510 # Per bank write bursts +system.physmem.perBankWrBursts::12 6360 # Per bank write bursts +system.physmem.perBankWrBursts::13 6344 # Per bank write bursts +system.physmem.perBankWrBursts::14 6013 # Per bank write bursts +system.physmem.perBankWrBursts::15 6102 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 366439104000 # Total gap between requests +system.physmem.totGap 366631694000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 143881 # Read request sizes (log2) +system.physmem.readPktSize::6 144269 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97182 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97528 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,34 +145,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -194,118 +194,106 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65604 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.015914 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.088937 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.071665 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24900 37.96% 37.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18453 28.13% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7121 10.85% 76.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7867 11.99% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1977 3.01% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1093 1.67% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 809 1.23% 94.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 630 0.96% 95.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2754 4.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65604 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5611 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.620745 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 380.610137 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5609 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 63306 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 244.314283 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.017060 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 244.594379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22538 35.60% 35.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17961 28.37% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7327 11.57% 75.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7996 12.63% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2051 3.24% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1180 1.86% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 835 1.32% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 660 1.04% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2758 4.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63306 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5727 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.172342 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.597400 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 376.088417 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5724 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5611 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5611 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.314204 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.219748 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.335766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2654 47.30% 47.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2805 49.99% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 62 1.10% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 24 0.43% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 17 0.30% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 10 0.18% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 10 0.18% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.04% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 4 0.07% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 2 0.04% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::98-99 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5611 # Writes before turning the bus around for reads -system.physmem.totQLat 1554447250 # Total ticks spent queuing -system.physmem.totMemAccLat 4250153500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 718855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10811.97 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5727 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5727 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.024795 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.995243 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.004050 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2743 47.90% 47.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 142 2.48% 50.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2814 49.14% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 20 0.35% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 6 0.10% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5727 # Writes before turning the bus around for reads +system.physmem.totQLat 1581653750 # Total ticks spent queuing +system.physmem.totMemAccLat 4284785000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720835000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10970.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29561.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.97 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.97 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29720.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.60 # Average write queue length when enqueuing -system.physmem.readRowHits 110522 # Number of row buffer hits during reads -system.physmem.writeRowHits 64789 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes -system.physmem.avgGap 1520096.84 # Average gap between requests -system.physmem.pageHitRate 72.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 249842880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 136323000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 559080600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 312783120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23933850720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47987220420 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 177768013500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250947114240 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.830589 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 295423376000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12236120000 # Time in different power states +system.physmem.avgWrQLen 20.20 # Average write queue length when enqueuing +system.physmem.readRowHits 110439 # Number of row buffer hits during reads +system.physmem.writeRowHits 67921 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.64 # Row buffer hit rate for writes +system.physmem.avgGap 1516278.92 # Average gap between requests +system.physmem.pageHitRate 73.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 239652000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130762500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560266200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 313968960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47282173740 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 178503263250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250976651370 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.547573 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 296644648000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12242620000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 58777294250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 57744168750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 246017520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134235750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562114800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 316645200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23933850720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47395195335 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178287321750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250875381075 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.634868 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296291389000 # Time in different power states -system.physmem_1.memoryStateTime::REF 12236120000 # Time in different power states +system.physmem_1.actEnergy 238941360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 130374750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 564213000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 317837520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47121480765 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178644216000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250963628115 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.512070 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296880094250 # Time in different power states +system.physmem_1.memoryStateTime::REF 12242620000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57909758500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57508713250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 132103761 # Number of BP lookups -system.cpu.branchPred.condPredicted 98193255 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5910050 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68601566 # Number of BTB lookups -system.cpu.branchPred.BTBHits 60590451 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 132103795 # Number of BP lookups +system.cpu.branchPred.condPredicted 98193288 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68601542 # Number of BTB lookups +system.cpu.branchPred.BTBHits 60590460 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.322256 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 88.322300 # BTB Hit Percentage system.cpu.branchPred.usedRAS 10017120 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3891572 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 3891574 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 3883027 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 8545 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -335,7 +323,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -365,7 +353,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -395,7 +383,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -426,16 +414,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 732878259 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 733263439 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506579366 # Number of instructions committed system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12939743 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12939754 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446720 # CPI: cycles per instruction -system.cpu.ipc 0.691219 # IPC: instructions per cycle +system.cpu.cpi 1.447480 # CPI: cycles per instruction +system.cpu.ipc 0.690856 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction @@ -471,29 +459,29 @@ system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 548692589 # Class of committed instruction -system.cpu.tickCycles 694071941 # Number of cycles that the object actually ticked -system.cpu.idleCycles 38806318 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 694072576 # Number of cycles that the object actually ticked +system.cpu.idleCycles 39190863 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1141337 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.313641 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171083825 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4070.301946 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171083822 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.361704 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5033914500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.313641 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993729 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993729 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 149.361702 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5036525500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.301946 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993726 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993726 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346338115 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346338115 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114566020 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114566020 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 346338109 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346338109 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114566017 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114566017 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53537929 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 53537929 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits @@ -502,10 +490,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168103949 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168103949 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168106743 # number of overall hits -system.cpu.dcache.overall_hits::total 168106743 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168103946 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168103946 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168106740 # number of overall hits +system.cpu.dcache.overall_hits::total 168106740 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 811381 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 811381 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 701120 # number of WriteReq misses @@ -516,16 +504,16 @@ system.cpu.dcache.demand_misses::cpu.data 1512501 # n system.cpu.dcache.demand_misses::total 1512501 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1512516 # number of overall misses system.cpu.dcache.overall_misses::total 1512516 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13462011000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13462011000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21943272000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21943272000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35405283000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35405283000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35405283000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35405283000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115377401 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115377401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13515584500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13515584500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22200332500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22200332500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35715917000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35715917000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35715917000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35715917000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115377398 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115377398 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) @@ -534,10 +522,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169616450 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169616450 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169619259 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169619259 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169616447 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169616447 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169619256 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169619256 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses @@ -548,22 +536,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16591.479219 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16591.479219 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31297.455500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31297.455500 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23408.436094 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23408.436094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23408.203946 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23408.203946 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16657.506769 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16657.506769 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31664.098157 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31664.098157 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23613.813809 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23613.813809 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23613.579625 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23613.579625 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1069267 # number of writebacks -system.cpu.dcache.writebacks::total 1069267 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks +system.cpu.dcache.writebacks::total 1068942 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22348 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 22348 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344732 # number of WriteReq MSHR hits @@ -582,16 +570,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12369658000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12369658000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11145800500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11145800500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1093500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1093500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23515458500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23515458500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23516552000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23516552000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12423186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12423186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11274063500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11274063500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 942500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 942500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23697250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23697250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23698192500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23698192500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses @@ -602,26 +590,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15676.984359 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15676.984359 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31274.342851 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31274.342851 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 91125 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 91125 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.969767 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.969767 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20530.709347 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20530.709347 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15744.824995 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15744.824995 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31634.239930 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31634.239930 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78541.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78541.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20688.681280 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20688.681280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20689.287370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20689.287370 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 18175 # number of replacements -system.cpu.icache.tags.tagsinuse 1187.153068 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199148908 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1187.102530 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199148962 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 20047 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9934.100264 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 9934.102958 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1187.153068 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.579665 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.579665 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1187.102530 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579640 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579640 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id @@ -629,45 +617,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 57 system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398357957 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398357957 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 199148908 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199148908 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199148908 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199148908 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199148908 # number of overall hits -system.cpu.icache.overall_hits::total 199148908 # number of overall hits +system.cpu.icache.tags.tag_accesses 398358065 # Number of tag accesses +system.cpu.icache.tags.data_accesses 398358065 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 199148962 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 199148962 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 199148962 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 199148962 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 199148962 # number of overall hits +system.cpu.icache.overall_hits::total 199148962 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 20047 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 20047 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 20047 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 20047 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 20047 # number of overall misses system.cpu.icache.overall_misses::total 20047 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 455856500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 455856500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 455856500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 455856500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 455856500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 455856500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 199168955 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 199168955 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 199168955 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 199168955 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 199168955 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 199168955 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 467837000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 467837000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 467837000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 467837000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 467837000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 467837000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 199169009 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 199169009 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 199169009 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 199169009 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 199169009 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 199169009 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.387440 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22739.387440 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.387440 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22739.387440 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.387440 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22739.387440 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23337.008031 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23337.008031 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23337.008031 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23337.008031 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -682,89 +670,89 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 20047 system.cpu.icache.demand_mshr_misses::total 20047 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 20047 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 20047 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435809500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 435809500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435809500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 435809500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435809500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 435809500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 447790000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 447790000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 447790000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 447790000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 447790000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 447790000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.387440 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.387440 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.387440 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.387440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.387440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.387440 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 112318 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27616.037174 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1771878 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 143528 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.345173 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 165163715500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23489.264935 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.326790 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3818.445449 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.716835 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009409 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.116530 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.842775 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31210 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4934 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952454 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 19060134 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 19060134 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 1069267 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1069267 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22337.008031 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22337.008031 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 112761 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29068.883602 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2174452 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.941709 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 101788000000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 134.067060 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.855024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28626.961519 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.004091 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009395 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.873626 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.887112 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 981 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140171 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050893 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050893 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051320 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051320 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123160 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123452 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123160 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123452 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68559.032766 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68559.032766 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69662.989324 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69662.989324 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72343.612993 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72343.612993 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69662.989324 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.995350 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69636.522543 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69662.989324 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.995350 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69636.522543 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69794.861257 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.861257 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73887.544484 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73887.544484 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73057.310837 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73057.310837 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 2324992 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159582 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2610 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 808842 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1166449 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 18175 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 87206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 20047 # Transaction distribution @@ -888,53 +876,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 3490472 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141740800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 144187008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 112318 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6219648 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1277798 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.006010 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.077318 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 144166208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112761 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1278241 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006014 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077345 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1270122 99.40% 99.40% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7673 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1270557 99.40% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7681 0.60% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1277798 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2249938000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1278241 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2249613000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30093953 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30094452 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1718157484 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 42954 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97182 # Transaction distribution -system.membus.trans_dist::CleanEvict 12526 # Transaction distribution -system.membus.trans_dist::ReadExReq 100927 # Transaction distribution -system.membus.trans_dist::ReadExResp 100927 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 42954 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 397470 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15428032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15428032 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 254412 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 110315 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 43291 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution +system.membus.trans_dist::CleanEvict 12615 # Transaction distribution +system.membus.trans_dist::ReadExReq 100978 # Transaction distribution +system.membus.trans_dist::ReadExResp 100978 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 43291 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398681 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 398681 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15475008 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15475008 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 253589 # Request fanout histogram +system.membus.snoop_fanout::samples 144269 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253589 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 144269 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253589 # Request fanout histogram -system.membus.reqLayer0.occupancy 685523500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 144269 # Request fanout histogram +system.membus.reqLayer0.occupancy 685129000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 763755750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765930250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index d31d95a5e..f10b69af3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.232865 # Number of seconds simulated -sim_ticks 232864525000 # Number of ticks simulated -final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233363 # Number of seconds simulated +sim_ticks 233363457000 # Number of ticks simulated +final_tick 233363457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 208842 # Simulator instruction rate (inst/s) -host_op_rate 226249 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96255881 # Simulator tick rate (ticks/s) -host_mem_usage 295820 # Number of bytes of host memory used -host_seconds 2419.22 # Real time elapsed on the host +host_inst_rate 153279 # Simulator instruction rate (inst/s) +host_op_rate 166055 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70798116 # Simulator tick rate (ticks/s) +host_mem_usage 302508 # Number of bytes of host memory used +host_seconds 3296.18 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory -system.physmem.bytes_read::total 27130944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 523840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 523840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18710656 # Number of bytes written to this memory -system.physmem.bytes_written::total 18710656 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158536 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257200 # Number of read requests responded to by this memory -system.physmem.num_reads::total 423921 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292354 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292354 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2249548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 43571703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70688311 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116509563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2249548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2249548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80349963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80349963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80349963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2249548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 43571703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70688311 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 196859526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423921 # Number of read requests accepted -system.physmem.writeReqs 292354 # Number of write requests accepted -system.physmem.readBursts 423921 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292354 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26979136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 151808 # Total number of bytes read from write queue -system.physmem.bytesWritten 18708352 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27130944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18710656 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2372 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 641792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10513600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16409344 # Number of bytes read from this memory +system.physmem.bytes_read::total 27564736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 641792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 641792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18651328 # Number of bytes written to this memory +system.physmem.bytes_written::total 18651328 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10028 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 164275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 256396 # Number of read requests responded to by this memory +system.physmem.num_reads::total 430699 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 291427 # Number of write requests responded to by this memory +system.physmem.num_writes::total 291427 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2750182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45052469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70316682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 118119333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2750182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2750182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 79923945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 79923945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 79923945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2750182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45052469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70316682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 198043278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 430699 # Number of read requests accepted +system.physmem.writeReqs 291427 # Number of write requests accepted +system.physmem.readBursts 430699 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 291427 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27407296 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 157440 # Total number of bytes read from write queue +system.physmem.bytesWritten 18649728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27564736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18651328 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2460 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26585 # Per bank write bursts -system.physmem.perBankRdBursts::1 25966 # Per bank write bursts -system.physmem.perBankRdBursts::2 25309 # Per bank write bursts -system.physmem.perBankRdBursts::3 32108 # Per bank write bursts -system.physmem.perBankRdBursts::4 27451 # Per bank write bursts -system.physmem.perBankRdBursts::5 28247 # Per bank write bursts -system.physmem.perBankRdBursts::6 25115 # Per bank write bursts -system.physmem.perBankRdBursts::7 24228 # Per bank write bursts -system.physmem.perBankRdBursts::8 25496 # Per bank write bursts -system.physmem.perBankRdBursts::9 25694 # Per bank write bursts -system.physmem.perBankRdBursts::10 25307 # Per bank write bursts -system.physmem.perBankRdBursts::11 26044 # Per bank write bursts -system.physmem.perBankRdBursts::12 27396 # Per bank write bursts -system.physmem.perBankRdBursts::13 26024 # Per bank write bursts -system.physmem.perBankRdBursts::14 24983 # Per bank write bursts -system.physmem.perBankRdBursts::15 25596 # Per bank write bursts -system.physmem.perBankWrBursts::0 18605 # Per bank write bursts -system.physmem.perBankWrBursts::1 18353 # Per bank write bursts -system.physmem.perBankWrBursts::2 18036 # Per bank write bursts -system.physmem.perBankWrBursts::3 17927 # Per bank write bursts -system.physmem.perBankWrBursts::4 18566 # Per bank write bursts -system.physmem.perBankWrBursts::5 18339 # Per bank write bursts -system.physmem.perBankWrBursts::6 17904 # Per bank write bursts -system.physmem.perBankWrBursts::7 17705 # Per bank write bursts -system.physmem.perBankWrBursts::8 17878 # Per bank write bursts -system.physmem.perBankWrBursts::9 17947 # Per bank write bursts -system.physmem.perBankWrBursts::10 18182 # Per bank write bursts -system.physmem.perBankWrBursts::11 18731 # Per bank write bursts -system.physmem.perBankWrBursts::12 18803 # Per bank write bursts -system.physmem.perBankWrBursts::13 18363 # Per bank write bursts -system.physmem.perBankWrBursts::14 18474 # Per bank write bursts -system.physmem.perBankWrBursts::15 18505 # Per bank write bursts +system.physmem.perBankRdBursts::0 27205 # Per bank write bursts +system.physmem.perBankRdBursts::1 26463 # Per bank write bursts +system.physmem.perBankRdBursts::2 25602 # Per bank write bursts +system.physmem.perBankRdBursts::3 32969 # Per bank write bursts +system.physmem.perBankRdBursts::4 28037 # Per bank write bursts +system.physmem.perBankRdBursts::5 29890 # Per bank write bursts +system.physmem.perBankRdBursts::6 25340 # Per bank write bursts +system.physmem.perBankRdBursts::7 24398 # Per bank write bursts +system.physmem.perBankRdBursts::8 25649 # Per bank write bursts +system.physmem.perBankRdBursts::9 25581 # Per bank write bursts +system.physmem.perBankRdBursts::10 25884 # Per bank write bursts +system.physmem.perBankRdBursts::11 26303 # Per bank write bursts +system.physmem.perBankRdBursts::12 27555 # Per bank write bursts +system.physmem.perBankRdBursts::13 26148 # Per bank write bursts +system.physmem.perBankRdBursts::14 24908 # Per bank write bursts +system.physmem.perBankRdBursts::15 26307 # Per bank write bursts +system.physmem.perBankWrBursts::0 18644 # Per bank write bursts +system.physmem.perBankWrBursts::1 18139 # Per bank write bursts +system.physmem.perBankWrBursts::2 17950 # Per bank write bursts +system.physmem.perBankWrBursts::3 17944 # Per bank write bursts +system.physmem.perBankWrBursts::4 18581 # Per bank write bursts +system.physmem.perBankWrBursts::5 18235 # Per bank write bursts +system.physmem.perBankWrBursts::6 17841 # Per bank write bursts +system.physmem.perBankWrBursts::7 17708 # Per bank write bursts +system.physmem.perBankWrBursts::8 18005 # Per bank write bursts +system.physmem.perBankWrBursts::9 17734 # Per bank write bursts +system.physmem.perBankWrBursts::10 18244 # Per bank write bursts +system.physmem.perBankWrBursts::11 18783 # Per bank write bursts +system.physmem.perBankWrBursts::12 18680 # Per bank write bursts +system.physmem.perBankWrBursts::13 18156 # Per bank write bursts +system.physmem.perBankWrBursts::14 18369 # Per bank write bursts +system.physmem.perBankWrBursts::15 18389 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 232864472500 # Total gap between requests +system.physmem.totGap 233363404500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 423921 # Read request sizes (log2) +system.physmem.readPktSize::6 430699 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292354 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 324214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3284 # What read queue length does an incoming req see +system.physmem.writePktSize::6 291427 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 330391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3274 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -149,41 +149,41 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see @@ -198,118 +198,117 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 322606 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 141.616907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 99.575706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 179.865264 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 203481 63.07% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79249 24.57% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15283 4.74% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7278 2.26% 94.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4895 1.52% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2519 0.78% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1928 0.60% 97.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1485 0.46% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6488 2.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 322606 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17068 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.693051 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 142.945620 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17066 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 328347 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 140.266048 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.833830 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 178.808988 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 208753 63.58% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 80037 24.38% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14980 4.56% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7256 2.21% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4857 1.48% 96.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2521 0.77% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1858 0.57% 97.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1524 0.46% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6561 2.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 328347 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 16970 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.230642 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 145.328941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 16968 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17068 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17068 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.126670 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.068877 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.479655 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 9203 53.92% 53.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 342 2.00% 55.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5412 31.71% 87.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1340 7.85% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 381 2.23% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 185 1.08% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 84 0.49% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 48 0.28% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 28 0.16% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 13 0.08% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 9 0.05% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 6 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 6 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 3 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17068 # Writes before turning the bus around for reads -system.physmem.totQLat 8669198966 # Total ticks spent queuing -system.physmem.totMemAccLat 16573242716 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2107745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20565.10 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 16970 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 16970 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.171597 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.099419 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.840930 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 9436 55.60% 55.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 6694 39.45% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 588 3.46% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 150 0.88% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 55 0.32% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 20 0.12% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 4 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 8 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 4 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::94-95 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 16970 # Writes before turning the bus around for reads +system.physmem.totQLat 8687632010 # Total ticks spent queuing +system.physmem.totMemAccLat 16717113260 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2141195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20286.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39315.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 115.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.35 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39036.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 117.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 79.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 118.12 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 79.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.53 # Data bus utilization in percentage -system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.54 # Data bus utilization in percentage +system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.66 # Average write queue length when enqueuing -system.physmem.readRowHits 306141 # Number of row buffer hits during reads -system.physmem.writeRowHits 85116 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.11 # Row buffer hit rate for writes -system.physmem.avgGap 325104.84 # Average gap between requests -system.physmem.pageHitRate 54.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1231478640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 671937750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1677023400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 942418800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 82038252060 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 67754804250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 169525418820 # Total energy per rank (pJ) -system.physmem_0.averagePower 728.002962 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 112181922825 # Time in different power states -system.physmem_0.memoryStateTime::REF 7775820000 # Time in different power states +system.physmem.avgWrQLen 21.52 # Average write queue length when enqueuing +system.physmem.readRowHits 308039 # Number of row buffer hits during reads +system.physmem.writeRowHits 83248 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.57 # Row buffer hit rate for writes +system.physmem.avgGap 323161.62 # Average gap between requests +system.physmem.pageHitRate 54.37 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1261242360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 688177875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1715142000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 939872160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15242051760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86511761685 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64129665000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 170487912840 # Total energy per rank (pJ) +system.physmem_0.averagePower 730.572857 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 106127593352 # Time in different power states +system.physmem_0.memoryStateTime::REF 7792460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 112906030175 # Time in different power states +system.physmem_0.memoryStateTime::ACT 119441919148 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1207422720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 658812000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1610934000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 951801840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 78953270130 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 70460943000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 169052687610 # Total energy per rank (pJ) -system.physmem_1.averagePower 725.972811 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 116702858630 # Time in different power states -system.physmem_1.memoryStateTime::REF 7775820000 # Time in different power states +system.physmem_1.actEnergy 1221045840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 666245250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1624857000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 948412800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15242051760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 81485025165 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 68539083000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 169726720815 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.311005 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 113492657633 # Time in different power states +system.physmem_1.memoryStateTime::REF 7792460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 108384997620 # Time in different power states +system.physmem_1.memoryStateTime::ACT 112077139867 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174583649 # Number of BP lookups -system.cpu.branchPred.condPredicted 131051926 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7234327 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90400017 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79003628 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174594135 # Number of BP lookups +system.cpu.branchPred.condPredicted 131061438 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7233022 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90315091 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79002409 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.393377 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12104831 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104507 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 4687804 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4673781 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14023 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 53864 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 87.474206 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12105110 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104499 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 4687937 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4674274 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 13663 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53871 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -339,7 +338,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -369,7 +368,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,7 +398,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -430,233 +429,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 465729051 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 466726915 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7627967 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 727492581 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174583649 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95782240 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 450186491 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14522705 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 141 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13015 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 235271545 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 36405 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 465093244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.693494 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.182412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7649319 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 727510991 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174594135 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95781793 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 451018276 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14520177 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5415 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13360 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 235275678 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 36827 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465946604 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.690437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.183518 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95400849 20.51% 20.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132044062 28.39% 48.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57356261 12.33% 61.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 180292072 38.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 96241342 20.66% 20.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132050994 28.34% 49.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57360477 12.31% 61.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 180293791 38.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 465093244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.374861 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.562051 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32522816 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 120066297 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 282921194 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22809829 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6773108 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 23856996 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495879 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 710982293 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29095211 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6773108 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63338503 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55962062 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40377047 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 273519607 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25122917 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 682713266 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 12851705 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9930975 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2510705 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1794472 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1920747 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 827509638 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3000483792 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 718633951 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 465946604 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.374082 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.558751 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32536552 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 120918293 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 282902203 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22817634 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6771922 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 23855471 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 495849 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 710960604 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29091371 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6771922 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63349282 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 56784032 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40401553 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 273510163 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25129652 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 682692967 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 12844145 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9945202 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2511648 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1805093 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1905777 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 827472920 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3000392013 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 718609980 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 96 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 173413964 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1545834 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1536299 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43818789 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 142365669 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67523427 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12892964 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11349045 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 664768510 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2979350 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608926727 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5749477 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 120399705 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 306541324 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1718 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 465093244 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.309257 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101839 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 173377246 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1545812 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1536134 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43839802 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 142358029 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67522859 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12902461 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11335768 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 664750936 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2979334 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608926553 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5748894 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 120382115 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 306467952 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1702 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465946604 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.306859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.102130 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 148683316 31.97% 31.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100887288 21.69% 53.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145497620 31.28% 84.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63056493 13.56% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6967915 1.50% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 612 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 149520607 32.09% 32.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100880237 21.65% 53.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145552540 31.24% 84.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63032249 13.53% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6960366 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 605 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 465093244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465946604 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71909518 53.13% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44304480 32.74% 85.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19119642 14.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71896734 53.12% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44291867 32.73% 85.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19147796 14.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412592470 67.76% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352106 0.06% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133579374 21.94% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62402774 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412590919 67.76% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352109 0.06% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133574983 21.94% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62408539 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608926727 # Type of FU issued -system.cpu.iq.rate 1.307470 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135333670 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222250 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1824029756 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 788176792 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594203276 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 89 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 608926553 # Type of FU issued +system.cpu.iq.rate 1.304674 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135336427 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222254 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1824884935 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 788141663 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594200588 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 96 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744260342 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7285470 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 744262920 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 60 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7284479 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26482386 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24610 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29757 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10663207 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26474746 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24624 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29798 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10662639 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225824 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22615 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225013 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22508 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6773108 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22711376 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 916891 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 669240779 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6771922 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22843049 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 918168 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 669223084 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 142365669 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67523427 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1490808 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 256518 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 523375 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29757 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3591194 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3743418 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7334612 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 598426944 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129087025 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10499783 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 142358029 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67522859 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1490792 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 256633 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 523882 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29798 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3590923 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3742651 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7333574 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 598420503 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129081054 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10506050 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1492919 # number of nop insts executed -system.cpu.iew.exec_refs 190006687 # number of memory reference insts executed -system.cpu.iew.exec_branches 131263664 # Number of branches executed -system.cpu.iew.exec_stores 60919662 # Number of stores executed -system.cpu.iew.exec_rate 1.284925 # Inst execution rate -system.cpu.iew.wb_sent 595449226 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594203292 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349565798 # num instructions producing a value -system.cpu.iew.wb_consumers 571378084 # num instructions consuming a value -system.cpu.iew.wb_rate 1.275856 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611794 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 107129246 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1492814 # number of nop insts executed +system.cpu.iew.exec_refs 190002009 # number of memory reference insts executed +system.cpu.iew.exec_branches 131263961 # Number of branches executed +system.cpu.iew.exec_stores 60920955 # Number of stores executed +system.cpu.iew.exec_rate 1.282164 # Inst execution rate +system.cpu.iew.wb_sent 595445456 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594200604 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349565575 # num instructions producing a value +system.cpu.iew.wb_consumers 571385188 # num instructions consuming a value +system.cpu.iew.wb_rate 1.273123 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611786 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 107116116 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6746083 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 448430808 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.223582 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.891618 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6744856 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 449285999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.221253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.890713 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 219662042 48.98% 48.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116371870 25.95% 74.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43476650 9.70% 84.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23164070 5.17% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11528126 2.57% 92.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7755918 1.73% 94.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8275201 1.85% 95.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4244089 0.95% 96.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13952842 3.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 220514428 49.08% 49.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116376748 25.90% 74.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43480691 9.68% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23177999 5.16% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11514242 2.56% 92.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7755129 1.73% 94.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8259802 1.84% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4227193 0.94% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13979767 3.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 448430808 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 449285999 # Number of insts commited each cycle system.cpu.commit.committedInsts 506578818 # Number of instructions committed system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -702,555 +701,560 @@ system.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction -system.cpu.commit.bw_lim_events 13952842 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1090292113 # The number of ROB reads -system.cpu.rob.rob_writes 1328334369 # The number of ROB writes -system.cpu.timesIdled 12786 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 635807 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13979767 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1091107249 # The number of ROB reads +system.cpu.rob.rob_writes 1328306301 # The number of ROB writes +system.cpu.timesIdled 14326 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 780311 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505234934 # Number of Instructions Simulated system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.921807 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.921807 # CPI: Total CPI of All Threads -system.cpu.ipc 1.084826 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.084826 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 610135542 # number of integer regfile reads -system.cpu.int_regfile_writes 327337405 # number of integer regfile writes +system.cpu.cpi 0.923782 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.923782 # CPI: Total CPI of All Threads +system.cpu.ipc 1.082507 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.082507 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 610129735 # number of integer regfile reads +system.cpu.int_regfile_writes 327331512 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2166261838 # number of cc regfile reads -system.cpu.cc_regfile_writes 376539611 # number of cc regfile writes -system.cpu.misc_regfile_reads 217603179 # number of misc regfile reads +system.cpu.cc_regfile_reads 2166233884 # number of cc regfile reads +system.cpu.cc_regfile_writes 376536291 # number of cc regfile writes +system.cpu.misc_regfile_reads 217601523 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2817145 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.627957 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168870791 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2817657 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 59.933055 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.627957 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2817306 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.628303 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168866082 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817818 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 59.927959 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 501259000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.628303 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999274 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999274 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 355267161 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 355267161 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114168570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114168570 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51722271 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51722271 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2788 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2788 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 355259202 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 355259202 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114162091 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114162091 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51724043 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51724043 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2789 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2789 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 165890841 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 165890841 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 165893629 # number of overall hits -system.cpu.dcache.overall_hits::total 165893629 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4837166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4837166 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2516778 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2516778 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 165886134 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 165886134 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 165888923 # number of overall hits +system.cpu.dcache.overall_hits::total 165888923 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4839586 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4839586 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2515006 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2515006 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7353944 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7353944 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7353956 # number of overall misses -system.cpu.dcache.overall_misses::total 7353956 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57478265500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57478265500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18947607428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18947607428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1052500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1052500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 76425872928 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 76425872928 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 76425872928 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 76425872928 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119005736 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119005736 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7354592 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7354592 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7354602 # number of overall misses +system.cpu.dcache.overall_misses::total 7354602 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58596122500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58596122500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18922626430 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18922626430 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1155000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1155000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 77518748930 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 77518748930 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 77518748930 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 77518748930 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119001677 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119001677 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2800 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2800 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2799 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2799 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173244785 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173244785 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173247585 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173247585 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040646 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040646 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046402 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046402 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004286 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.004286 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173240726 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173240726 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173243525 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173243525 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040668 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040668 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046369 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046369 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003573 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003573 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042448 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042448 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042448 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042448 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11882.632413 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11882.632413 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7528.517584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7528.517584 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15946.969697 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15946.969697 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10392.501347 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10392.501347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10392.484389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10392.484389 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 916660 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221191 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.144201 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2817145 # number of writebacks -system.cpu.dcache.writebacks::total 2817145 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2539309 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2539309 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996958 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1996958 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.042453 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042453 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042452 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042452 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12107.672536 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12107.672536 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7523.889180 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7523.889180 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10540.183457 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10540.183457 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10540.169125 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10540.169125 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 907373 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221320 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.099824 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2817306 # number of writebacks +system.cpu.dcache.writebacks::total 2817306 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541564 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2541564 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995189 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1995189 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4536267 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4536267 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4536267 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4536267 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297857 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2297857 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519820 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519820 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2817677 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2817677 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2817687 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2817687 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29541351500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29541351500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603156994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603156994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 669500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 669500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34144508494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 34144508494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34145177994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 34145177994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 4536753 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4536753 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4536753 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4536753 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298022 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2298022 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519817 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519817 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2817839 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2817839 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34719285995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 34719285995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019311 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019311 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003571 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003571 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 470619957 # Number of tag accesses -system.cpu.icache.tags.data_accesses 470619957 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 235186472 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 235186472 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 235186472 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 235186472 # 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number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1359599197 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1359599197 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 235271444 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 235271444 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 235271444 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 235271444 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 235271444 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 235271444 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000361 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000361 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000361 # 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number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77071 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 77071 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 77071 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 77071 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 77071 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 77071 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1127867788 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1127867788 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1127867788 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1127867788 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1127867788 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1127867788 # number of overall MSHR miss cycles +system.cpu.icache.tags.tag_accesses 470628332 # Number of tag accesses +system.cpu.icache.tags.data_accesses 470628332 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 235189788 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 235189788 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 235189788 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 235189788 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 235189788 # number of overall hits +system.cpu.icache.overall_hits::total 235189788 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 85789 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 85789 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 85789 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 85789 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 85789 # number of overall misses +system.cpu.icache.overall_misses::total 85789 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1556704687 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1556704687 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1556704687 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1556704687 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1556704687 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1556704687 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 235275577 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 235275577 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 235275577 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 235275577 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 235275577 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 235275577 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000365 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000365 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000365 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000365 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000365 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000365 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18145.737647 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18145.737647 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18145.737647 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18145.737647 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18145.737647 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18145.737647 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 171831 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 200 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6857 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.059210 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 76636 # number of writebacks +system.cpu.icache.writebacks::total 76636 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8610 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8610 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8610 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8610 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 8610 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 8610 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77179 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 77179 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 77179 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 77179 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 77179 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 77179 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1268632793 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1268632793 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1268632793 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1268632793 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1268632793 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1268632793 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14634.139793 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14634.139793 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # 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average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 8513734 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8515093 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 374 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 395630 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15127.357564 # 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Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2699085 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 406018 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.647698 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14926.062493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 74.046079 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.911015 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004519 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.915534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 114 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15501 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 17 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 46 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 49 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5426 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6626 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2533 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006958 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946106 # 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average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 1977 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 292354 # number of writebacks -system.cpu.l2cache.writebacks::total 292354 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1396 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1396 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 9 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4126 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4126 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5522 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 164278 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 356222 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 530528 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18747915458 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18747915458 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 462000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 462000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 336888000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 336888000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 689794500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 689794500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11439165000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11439165000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 689794500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11776053000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12465847500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 689794500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11776053000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18747915458 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31213762958 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007088 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007088 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.106248 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067449 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067449 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056266 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.057596 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056266 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007015 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007015 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069961 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069961 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058300 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060210 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058300 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.178797 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53136.776573 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14650 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14650 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89883.243243 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89883.243243 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66851.130116 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66851.130116 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70149.575686 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70149.575686 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70425.583153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5788431 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893715 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 543102 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 266298 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 392168 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.183259 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 52629.864124 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15400 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15400 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91995.630803 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91995.630803 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68786.846829 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68786.846829 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71220.582009 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71220.582009 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68786.846829 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71683.688625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71517.030395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68786.846829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71683.688625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58835.279114 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5788969 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893984 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23717 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 99826 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99825 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2372984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2645368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 540001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 397627 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 30 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 30 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 522011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 522011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 77071 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295646 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230634 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452520 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8683154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9828032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360627392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370455424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 950855 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18712896 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3845578 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.078356 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.284056 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 522012 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 522012 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 77179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295806 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230958 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453003 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8683961 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9841856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360648000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370489856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 788066 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18653632 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3683057 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.033555 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.180083 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3560544 92.59% 92.59% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 268745 6.99% 99.58% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 16289 0.42% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3559472 96.64% 96.64% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 123584 3.36% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3845578 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5787888505 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3683057 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5788426505 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 115689827 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 115796940 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4226522955 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4226763956 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 420223 # Transaction distribution -system.membus.trans_dist::WritebackDirty 292354 # Transaction distribution -system.membus.trans_dist::CleanEvict 98859 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33 # Transaction distribution -system.membus.trans_dist::ReadExReq 3697 # Transaction distribution -system.membus.trans_dist::ReadExResp 3697 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 420224 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239087 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1239087 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45841536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45841536 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 821136 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 414105 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 427040 # Transaction distribution +system.membus.trans_dist::WritebackDirty 291427 # Transaction distribution +system.membus.trans_dist::CleanEvict 98976 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34 # Transaction distribution +system.membus.trans_dist::ReadExReq 3658 # Transaction distribution +system.membus.trans_dist::ReadExResp 3658 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 427041 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251834 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1251834 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46216000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46216000 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 815167 # Request fanout histogram +system.membus.snoop_fanout::samples 430733 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 815167 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430733 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 815167 # Request fanout histogram -system.membus.reqLayer0.occupancy 2211611288 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2242842427 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 430733 # Request fanout histogram +system.membus.reqLayer0.occupancy 2217216132 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 2280002282 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index e8a891fe8..6a67fce1b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279361 # Nu sim_ticks 279360903000 # Number of ticks simulated final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1100009 # Simulator instruction rate (inst/s) -host_op_rate 1191455 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 606617028 # Simulator tick rate (ticks/s) -host_mem_usage 259840 # Number of bytes of host memory used -host_seconds 460.52 # Real time elapsed on the host +host_inst_rate 1206466 # Simulator instruction rate (inst/s) +host_op_rate 1306763 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 665324846 # Simulator tick rate (ticks/s) +host_mem_usage 263448 # Number of bytes of host memory used +host_seconds 419.89 # Real time elapsed on the host sim_insts 506578818 # Number of instructions simulated sim_ops 548692039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 630707528 # Transaction distribution system.membus.trans_dist::ReadResp 632196069 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 2705349287 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 687926230 # Request fanout histogram -system.membus.snoop_fanout::mean 0.750965 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.432454 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 171317644 24.90% 24.90% # Request fanout histogram -system.membus.snoop_fanout::1 516608586 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 687926230 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 687926230 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index a77764c75..9780dac13 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.708539 # Number of seconds simulated -sim_ticks 708539449500 # Number of ticks simulated -final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.708700 # Number of seconds simulated +sim_ticks 708700329500 # Number of ticks simulated +final_tick 708700329500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 665557 # Simulator instruction rate (inst/s) -host_op_rate 720769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 933837970 # Simulator tick rate (ticks/s) -host_mem_usage 269828 # Number of bytes of host memory used -host_seconds 758.74 # Real time elapsed on the host +host_inst_rate 820539 # Simulator instruction rate (inst/s) +host_op_rate 888607 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1151553403 # Simulator tick rate (ticks/s) +host_mem_usage 275232 # Number of bytes of host memory used +host_seconds 615.43 # Real time elapsed on the host sim_insts 504984064 # Number of instructions simulated sim_ops 546875315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory -system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8988096 # Number of bytes read from this memory +system.physmem.bytes_read::total 9135488 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory -system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6185472 # Number of bytes written to this memory +system.physmem.bytes_written::total 6185472 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 140439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142742 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96648 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96648 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 207975 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12682506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12890481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 207975 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 207975 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8727909 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8727909 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8727909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 207975 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12682506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21618390 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 708539449500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1417078899 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 708700329500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1417400659 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504984064 # Number of instructions committed @@ -182,7 +182,7 @@ system.cpu.num_mem_refs 172743505 # nu system.cpu.num_load_insts 115883283 # Number of load instructions system.cpu.num_store_insts 56860222 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1417400658.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 121552863 # Number of branches fetched @@ -221,16 +221,16 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1136276 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4065.253828 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 11754931500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.253828 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992494 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992494 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id @@ -240,7 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits @@ -265,14 +265,14 @@ system.cpu.dcache.demand_misses::cpu.data 1140371 # n system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses system.cpu.dcache.overall_misses::total 1140372 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12176129500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12176129500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9680337500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9680337500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21856467000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21856467000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21856467000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21856467000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) @@ -297,22 +297,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15533.491822 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15533.491822 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27153.212551 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27153.212551 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19166.102084 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19166.102084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19166.085277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19166.085277 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks -system.cpu.dcache.writebacks::total 1065708 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1065429 # number of writebacks +system.cpu.dcache.writebacks::total 1065429 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses @@ -323,16 +323,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11392266500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11392266500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9323829500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9323829500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20716096000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20716096000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20716158000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20716158000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses @@ -343,26 +343,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14533.491822 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14533.491822 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26153.212551 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26153.212551 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18166.102084 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18166.102084 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18166.140523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18166.140523 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.167360 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.167360 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480062 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480062 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id @@ -372,7 +372,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits @@ -385,12 +385,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 263211000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 263211000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 263211000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 265513000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 265513000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 265513000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 265513000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 265513000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 265513000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516608587 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516608587 # number of demand (read+write) accesses @@ -403,12 +403,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22846.193907 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22846.193907 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22846.193907 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23046.002951 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23046.002951 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23046.002951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23046.002951 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -423,89 +423,89 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 251690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 251690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251690000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 251690000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253992000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 253992000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253992000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 253992000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253992000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 253992000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 110394 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.053019 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.713374 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.110964 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831668 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7098557500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7215061500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282835 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282835 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050527 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050527 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50540.170381 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50540.170381 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50587.928789 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50587.928789 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50559.018836 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50559.018836 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2153 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2152 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1162077 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 85012 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution @@ -623,53 +623,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 110394 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6165120 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141171264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142535040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 110813 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6185472 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1262706 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.067461 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1256936 99.54% 99.54% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5769 0.46% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1262706 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2224195500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 41576 # Transaction distribution -system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution -system.membus.trans_dist::CleanEvict 11920 # Transaction distribution -system.membus.trans_dist::ReadExReq 100788 # Transaction distribution -system.membus.trans_dist::ReadExResp 100788 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 251405 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 108784 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 41909 # Transaction distribution +system.membus.trans_dist::WritebackDirty 96648 # Transaction distribution +system.membus.trans_dist::CleanEvict 12014 # Transaction distribution +system.membus.trans_dist::ReadExReq 100833 # Transaction distribution +system.membus.trans_dist::ReadExResp 100833 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 41909 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394146 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394146 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15320960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15320960 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 250615 # Request fanout histogram +system.membus.snoop_fanout::samples 142743 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 142743 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 250615 # Request fanout histogram -system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 142743 # Request fanout histogram +system.membus.reqLayer0.occupancy 644372828 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 713710000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |