diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt | 1346 |
1 files changed, 673 insertions, 673 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 72d60096c..0b91be0ea 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.425005 # Number of seconds simulated -sim_ticks 425004962000 # Number of ticks simulated -final_tick 425004962000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.447151 # Number of seconds simulated +sim_ticks 447151291000 # Number of ticks simulated +final_tick 447151291000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69307 # Simulator instruction rate (inst/s) -host_op_rate 128157 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35623080 # Simulator tick rate (ticks/s) -host_mem_usage 342928 # Number of bytes of host memory used -host_seconds 11930.61 # Real time elapsed on the host +host_inst_rate 99582 # Simulator instruction rate (inst/s) +host_op_rate 184139 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53851139 # Simulator tick rate (ticks/s) +host_mem_usage 337048 # Number of bytes of host memory used +host_seconds 8303.47 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988699 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 225344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 27603520 # Number of bytes read from this memory -system.physmem.bytes_read::total 27828864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 225344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 225344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20794944 # Number of bytes written to this memory -system.physmem.bytes_written::total 20794944 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3521 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 431305 # Number of read requests responded to by this memory -system.physmem.num_reads::total 434826 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 324921 # Number of write requests responded to by this memory -system.physmem.num_writes::total 324921 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 530215 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 64948701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 65478916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 530215 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 530215 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 48928709 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 48928709 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 48928709 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 530215 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 64948701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 114407624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 434829 # Total number of read requests seen -system.physmem.writeReqs 324921 # Total number of write requests seen -system.physmem.cpureqs 946181 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 27828864 # Total number of bytes read from memory -system.physmem.bytesWritten 20794944 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 27828864 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 20794944 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 530 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 186431 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 25473 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28169 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 26795 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 25192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 26852 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 26027 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 26097 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27939 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27190 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 26694 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 21362 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 19642 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 20883 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 21132 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 20800 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 20650 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 19810 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 19986 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 19177 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 20342 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 19625 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 19675 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 20834 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 20387 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 20379 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 20237 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 207040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24466624 # Number of bytes read from this memory +system.physmem.bytes_read::total 24673664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 207040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 207040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18786368 # Number of bytes written to this memory +system.physmem.bytes_written::total 18786368 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3235 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382291 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385526 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293537 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293537 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 463020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 54716657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 55179677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 463020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 463020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 42013449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 42013449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 42013449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 463020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 54716657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 97193127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385528 # Total number of read requests seen +system.physmem.writeReqs 293537 # Total number of write requests seen +system.physmem.cpureqs 863596 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24673664 # Total number of bytes read from memory +system.physmem.bytesWritten 18786368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24673664 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18786368 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 164 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 184531 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 24996 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 23035 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 24534 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 25301 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 24892 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24563 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 23920 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24683 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 22800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23577 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 23208 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 23396 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 24161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 24133 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 24010 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 24155 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 19354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 17947 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18690 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 18990 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 19041 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18099 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18501 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 17450 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 17927 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 17723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 17609 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 18440 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 18279 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 18321 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 18443 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 425004950500 # Total gap between requests +system.physmem.totGap 447151273000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 434829 # Categorize read packet sizes +system.physmem.readPktSize::6 385528 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 324921 # categorize write packet sizes +system.physmem.writePktSize::6 293537 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,17 +102,17 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 186431 # categorize neither packet sizes +system.physmem.neitherpktsize::6 184531 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 423801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 992 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 380682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 14107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 14125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 14127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,266 +171,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2315570683 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11699376683 # Sum of mem lat for all requests -system.physmem.totBusLat 1737188000 # Total cycles spent in databus access -system.physmem.totBankLat 7646618000 # Total cycles spent in bank access -system.physmem.avgQLat 5331.74 # Average queueing delay per request -system.physmem.avgBankLat 17606.81 # Average bank access latency per request -system.physmem.avgBusLat 3999.98 # Average bus latency per request -system.physmem.avgMemAccLat 26938.53 # Average memory access latency -system.physmem.avgRdBW 65.48 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 48.93 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 65.48 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 48.93 # Average consumed write bandwidth in MB/s +system.physmem.totQLat 3526127005 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11592689005 # Sum of mem lat for all requests +system.physmem.totBusLat 1541456000 # Total cycles spent in databus access +system.physmem.totBankLat 6525106000 # Total cycles spent in bank access +system.physmem.avgQLat 9150.12 # Average queueing delay per request +system.physmem.avgBankLat 16932.32 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30082.44 # Average memory access latency +system.physmem.avgRdBW 55.18 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 42.01 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 55.18 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 42.01 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.72 # Data bus utilization in percentage +system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 10.61 # Average write queue length over time -system.physmem.readRowHits 372606 # Number of row buffer hits during reads -system.physmem.writeRowHits 225570 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 69.42 # Row buffer hit rate for writes -system.physmem.avgGap 559401.05 # Average gap between requests +system.physmem.avgWrQLen 8.93 # Average write queue length over time +system.physmem.readRowHits 340552 # Number of row buffer hits during reads +system.physmem.writeRowHits 151633 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 51.66 # Row buffer hit rate for writes +system.physmem.avgGap 658480.81 # Average gap between requests system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 850009925 # number of cpu cycles simulated +system.cpu.numCycles 894302583 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 221647941 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 221647941 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14406573 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 156865582 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 152803842 # Number of BTB hits +system.cpu.BPredUnit.lookups 221834419 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 221834419 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14438837 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 157195941 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 152967077 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 187050304 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1232910947 # Number of instructions fetch has processed -system.cpu.fetch.Branches 221647941 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 152803842 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 383000973 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 91957921 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 194367409 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 27532 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 281947 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 179514226 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4153507 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 842043655 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.718190 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.421187 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 187305514 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1233712111 # Number of instructions fetch has processed +system.cpu.fetch.Branches 221834419 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 152967077 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 383213555 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 92482547 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 231997744 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 302541 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 179659779 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4113909 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 880638441 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.600745 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.391861 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 463448237 55.04% 55.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25479263 3.03% 58.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28153869 3.34% 61.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 29472837 3.50% 64.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 19000698 2.26% 67.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25093035 2.98% 70.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31632323 3.76% 73.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30740236 3.65% 77.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 189023157 22.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 501847528 56.99% 56.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25496575 2.90% 59.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28121767 3.19% 63.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 29451767 3.34% 66.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18987914 2.16% 68.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25123088 2.85% 71.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31720196 3.60% 75.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30784274 3.50% 78.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 189105332 21.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 842043655 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.260759 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.450467 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 241549987 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 153599929 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 326439638 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 43138611 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 77315490 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2235464595 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 77315490 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 274523548 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 31537330 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13263 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 335098725 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 123555299 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2183717460 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4657 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17805168 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 90736739 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 132 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2283770499 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5522648237 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5522400911 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 247326 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 880638441 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.248053 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.379524 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 244537844 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 188536263 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 324191261 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45585175 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 77787898 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2236907904 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 77787898 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 278585274 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 54813178 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15041 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 333395312 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 136041738 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2184748951 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 34526 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20261515 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 101530735 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 116 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2284488026 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5524710294 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5524485031 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 225263 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 669729648 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1332 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1314 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 306041131 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528315963 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210729777 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 206411035 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 60542315 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2088035741 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 33633 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1834967448 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 958048 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 553034175 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 917867353 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 33080 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 842043655 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.179183 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.902262 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 670447175 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1310 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1291 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 328673064 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 528947917 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 211077156 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 202192665 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58804191 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2090539379 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34704 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1836706736 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 960329 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 555260187 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 919296135 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 34151 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 880638441 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.085654 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.886104 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 224002778 26.60% 26.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 138530201 16.45% 43.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 132512875 15.74% 58.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 132981805 15.79% 74.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 103723627 12.32% 86.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60327569 7.16% 94.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 35793527 4.25% 98.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12197617 1.45% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1973656 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 249855133 28.37% 28.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 147643393 16.77% 45.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 139523467 15.84% 60.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 137737388 15.64% 76.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 97163823 11.03% 87.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 59916022 6.80% 94.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34917189 3.96% 98.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11990499 1.36% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1891527 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 842043655 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 880638441 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5036793 29.93% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9138103 54.31% 84.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2651049 15.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5040061 32.96% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7632140 49.91% 82.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2619273 17.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2710381 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1209906674 65.94% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 444393956 24.22% 90.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 177956437 9.70% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2704214 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1211533027 65.96% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 444457178 24.20% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 178012317 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1834967448 # Type of FU issued -system.cpu.iq.rate 2.158760 # Inst issue rate -system.cpu.iq.fu_busy_cnt 16825945 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009170 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4529719072 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2641264974 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1791788720 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 43472 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82738 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10238 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1849062833 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 20179 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 168239222 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1836706736 # Type of FU issued +system.cpu.iq.rate 2.053787 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15291474 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008325 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4570263035 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2646020420 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1794037475 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 40681 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 76210 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 9614 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1849275039 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 18957 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170130474 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144213807 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 600713 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 256350 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61570124 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 144845761 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 503638 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 274982 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61917680 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 8445 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10585 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 592 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 77315490 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4278866 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 415483 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2088069374 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2542491 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528315963 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 210730309 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5324 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 253060 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 9562 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 256350 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10027874 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4925644 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 14953518 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1804855171 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 436117290 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30112277 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 77787898 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17508647 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2908748 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2090574083 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2437552 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 528947917 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 211077865 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5687 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1841603 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73588 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 274982 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10048689 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4929582 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 14978271 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1806703840 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 436137965 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30002896 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 608678492 # number of memory reference insts executed -system.cpu.iew.exec_branches 171062939 # Number of branches executed -system.cpu.iew.exec_stores 172561202 # Number of stores executed -system.cpu.iew.exec_rate 2.123334 # Inst execution rate -system.cpu.iew.wb_sent 1799249201 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1791798958 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1362830081 # num instructions producing a value -system.cpu.iew.wb_consumers 2000862713 # num instructions consuming a value +system.cpu.iew.exec_refs 608784008 # number of memory reference insts executed +system.cpu.iew.exec_branches 171260555 # Number of branches executed +system.cpu.iew.exec_stores 172646043 # Number of stores executed +system.cpu.iew.exec_rate 2.020238 # Inst execution rate +system.cpu.iew.wb_sent 1801373489 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1794047089 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1362133405 # num instructions producing a value +system.cpu.iew.wb_consumers 1992639116 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.107974 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.681121 # average fanout of values written-back +system.cpu.iew.wb_rate 2.006085 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.683583 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 559102384 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 561620004 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14433850 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 764728165 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.999389 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.465219 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14469462 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 802850543 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.904450 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.430311 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272413651 35.62% 35.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 194503439 25.43% 61.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 61238057 8.01% 69.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 90227004 11.80% 80.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27738655 3.63% 84.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 29159140 3.81% 88.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10333164 1.35% 89.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10341610 1.35% 91.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 68773445 8.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 304835163 37.97% 37.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 198905096 24.77% 62.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63436109 7.90% 70.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92154984 11.48% 82.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 26044111 3.24% 85.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 29384573 3.66% 89.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9423573 1.17% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10229786 1.27% 91.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 68437148 8.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 764728165 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 802850543 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -441,311 +441,311 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 68773445 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 68437148 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2784045803 # The number of ROB reads -system.cpu.rob.rob_writes 4253715555 # The number of ROB writes -system.cpu.timesIdled 179238 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7966270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2825022098 # The number of ROB reads +system.cpu.rob.rob_writes 4259228710 # The number of ROB writes +system.cpu.timesIdled 301112 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13664142 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.027976 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.027976 # CPI: Total CPI of All Threads -system.cpu.ipc 0.972785 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.972785 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3390214587 # number of integer regfile reads -system.cpu.int_regfile_writes 1871573439 # number of integer regfile writes -system.cpu.fp_regfile_reads 10236 # number of floating regfile reads +system.cpu.cpi 1.081542 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.081542 # CPI: Total CPI of All Threads +system.cpu.ipc 0.924606 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.924606 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3392416402 # number of integer regfile reads +system.cpu.int_regfile_writes 1873878910 # number of integer regfile writes +system.cpu.fp_regfile_reads 9612 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.misc_regfile_reads 993130827 # number of misc regfile reads -system.cpu.icache.replacements 5731 # number of replacements -system.cpu.icache.tagsinuse 1034.037523 # Cycle average of tags in use -system.cpu.icache.total_refs 179301494 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7346 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24408.044378 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 993805261 # number of misc regfile reads +system.cpu.icache.replacements 5664 # number of replacements +system.cpu.icache.tagsinuse 1040.414195 # Cycle average of tags in use +system.cpu.icache.total_refs 179444520 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7258 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24723.686966 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1034.037523 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.504901 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.504901 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 179317731 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 179317731 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 179317731 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 179317731 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 179317731 # number of overall hits -system.cpu.icache.overall_hits::total 179317731 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 196495 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 196495 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 196495 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 196495 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 196495 # number of overall misses -system.cpu.icache.overall_misses::total 196495 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 965132000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 965132000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 965132000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 965132000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 965132000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 965132000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 179514226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 179514226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 179514226 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 179514226 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 179514226 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 179514226 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001095 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001095 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001095 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001095 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001095 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001095 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 4911.738212 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 4911.738212 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 4911.738212 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 4911.738212 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 4911.738212 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 4911.738212 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1040.414195 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.508015 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.508015 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 179464097 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 179464097 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 179464097 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 179464097 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 179464097 # number of overall hits +system.cpu.icache.overall_hits::total 179464097 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 195682 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 195682 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 195682 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 195682 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 195682 # number of overall misses +system.cpu.icache.overall_misses::total 195682 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1231899498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1231899498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1231899498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1231899498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1231899498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1231899498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 179659779 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 179659779 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 179659779 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 179659779 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 179659779 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 179659779 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001089 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001089 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001089 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001089 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001089 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001089 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6295.415511 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6295.415511 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6295.415511 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6295.415511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6295.415511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6295.415511 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 959 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56.411765 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 532960000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 532960000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 532960000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 532960000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 532960000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 532960000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001087 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001087 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001087 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001087 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001087 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 2730.215975 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 2730.215975 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 2730.215975 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 2730.215975 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 2730.215975 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 2730.215975 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2352 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2352 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2352 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 781617498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 781617498 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 781617498 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001076 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001076 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001076 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4042.918833 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4042.918833 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4042.918833 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4042.918833 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4042.918833 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4042.918833 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2528528 # number of replacements -system.cpu.dcache.tagsinuse 4087.799057 # Cycle average of tags in use -system.cpu.dcache.total_refs 412295597 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2532624 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 162.793844 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1757376000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.799057 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997998 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997998 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 263850158 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 263850158 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148199214 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148199214 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 412049372 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 412049372 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 412049372 # number of overall hits -system.cpu.dcache.overall_hits::total 412049372 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2450927 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2450927 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 960987 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 960987 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3411914 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3411914 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3411914 # number of overall misses -system.cpu.dcache.overall_misses::total 3411914 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 21876345500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 21876345500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10305852000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10305852000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32182197500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32182197500 # 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Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998042 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 261613799 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 261613799 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148186041 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148186041 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 409799840 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 409799840 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 409799840 # number of overall hits +system.cpu.dcache.overall_hits::total 409799840 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2816252 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2816252 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 974160 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 974160 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3790412 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3790412 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3790412 # number of overall misses +system.cpu.dcache.overall_misses::total 3790412 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 49180630000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 49180630000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23742046000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23742046000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 72922676000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 72922676000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 72922676000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 72922676000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264430051 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264430051 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 415461286 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 415461286 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 415461286 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 415461286 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009204 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009204 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006443 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006443 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008212 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008212 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008212 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008212 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8925.743402 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8925.743402 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10724.236644 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10724.236644 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9432.300316 # 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miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006531 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009165 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009165 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009165 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009165 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17463.149605 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17463.149605 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24371.813665 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24371.813665 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19238.720224 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19238.720224 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19238.720224 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19238.720224 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6306 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 671 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.397914 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2303917 # number of writebacks -system.cpu.dcache.writebacks::total 2303917 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 688869 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 688869 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2605 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2605 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 691474 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 691474 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 691474 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 691474 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762058 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762058 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19289360500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19289360500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19289360500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006425 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006425 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006548 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006548 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52949.490122 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -754,60 +754,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 324921 # number of writebacks -system.cpu.l2cache.writebacks::total 324921 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3522 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222082 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 225604 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12076834443 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12207243772 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.481542 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126115 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127585 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992439 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992439 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271180 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271180 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.481542 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170315 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.171211 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.481542 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170315 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.171211 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37027.066723 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30366.459628 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30470.441198 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1026.953341 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1026.953341 # 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number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3236 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175667 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178903 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 184491 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 184491 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206666 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206666 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3236 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382333 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385569 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3236 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15331875607 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15478813969 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 146938362 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15331875607 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15478813969 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.448572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099680 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101102 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991807 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991807 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.267847 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.267847 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.448572 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150888 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151733 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.448572 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150888 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151733 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45407.404821 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39729.345603 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39832.050418 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.352722 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.352722 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40416.617407 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40416.617407 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45407.404821 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40100.843001 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40145.379865 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45407.404821 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40100.843001 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40145.379865 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |