diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt | 1083 |
1 files changed, 542 insertions, 541 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 4a5cfadf8..46181ad4f 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.459938 # Number of seconds simulated -sim_ticks 459937575500 # Number of ticks simulated -final_tick 459937575500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.455813 # Number of seconds simulated +sim_ticks 455813328500 # Number of ticks simulated +final_tick 455813328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70939 # Simulator instruction rate (inst/s) -host_op_rate 131174 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39458742 # Simulator tick rate (ticks/s) -host_mem_usage 264492 # Number of bytes of host memory used -host_seconds 11656.16 # Real time elapsed on the host +host_inst_rate 110548 # Simulator instruction rate (inst/s) +host_op_rate 204416 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60939389 # Simulator tick rate (ticks/s) +host_mem_usage 266636 # Number of bytes of host memory used +host_seconds 7479.78 # Real time elapsed on the host sim_insts 826877144 # Number of instructions simulated sim_ops 1528988756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 379264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 37103744 # Number of bytes read from this memory -system.physmem.bytes_read::total 37483008 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 379264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 379264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 26316864 # Number of bytes written to this memory -system.physmem.bytes_written::total 26316864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 579746 # Number of read requests responded to by this memory -system.physmem.num_reads::total 585672 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 411201 # Number of write requests responded to by this memory -system.physmem.num_writes::total 411201 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 824599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 80671261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 81495859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 824599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 824599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 57218339 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 57218339 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 57218339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 824599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 80671261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 138714198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 220672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 27604992 # Number of bytes read from this memory +system.physmem.bytes_read::total 27825664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20791296 # Number of bytes written to this memory +system.physmem.bytes_written::total 20791296 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3448 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 431328 # Number of read requests responded to by this memory +system.physmem.num_reads::total 434776 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 324864 # Number of write requests responded to by this memory +system.physmem.num_writes::total 324864 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 484128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60562055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61046183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 484128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 484128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45613620 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45613620 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45613620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 484128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60562055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106659803 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 919875152 # number of cpu cycles simulated +system.cpu.numCycles 911626658 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 225607243 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 225607243 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14288733 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 160422197 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 155872353 # Number of BTB hits +system.cpu.BPredUnit.lookups 225614318 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 225614318 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14285714 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 160541063 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 155870604 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 191636234 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1263077256 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225607243 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155872353 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 392059630 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 98480346 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 233495655 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 26883 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 277282 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 183482871 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3659349 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 901432928 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.597231 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.389695 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 191565109 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1263061891 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225614318 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155870604 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 392054994 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 98473885 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 230412581 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25920 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 273577 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 183478574 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3652581 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 898267437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.606318 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.392133 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 513839664 57.00% 57.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25974503 2.88% 59.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 29108148 3.23% 63.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 30308604 3.36% 66.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 19639160 2.18% 68.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25619098 2.84% 71.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 32630243 3.62% 75.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30828862 3.42% 78.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 193484646 21.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 510675527 56.85% 56.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25992328 2.89% 59.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 29100733 3.24% 62.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 30303597 3.37% 66.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 19641643 2.19% 68.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25615145 2.85% 71.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32617140 3.63% 75.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30849776 3.43% 78.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 193471548 21.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 901432928 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.245259 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.373096 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 252952155 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 185449202 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 329948666 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49145661 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 83937244 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2290194252 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 83937244 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 289581235 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 42452690 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14732 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 340327979 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 145119048 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2240246263 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3253 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 23409384 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 104435988 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 12914 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2886886923 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6492696430 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6491823905 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 872525 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 898267437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.247485 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.385503 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 252696641 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 182534450 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 330171612 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 48929478 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 83935256 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2290198570 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 83935256 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 289311592 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40780199 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14639 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 340344585 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 143881166 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2240282902 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2186 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 22940117 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 103602655 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 11705 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2887046684 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6493129070 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6492267923 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 861147 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993077484 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 893809439 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1297 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1279 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 347581498 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 540130264 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 217339026 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 215698631 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 63624557 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2143116411 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 61984 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1846710444 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1594990 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 612455576 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1230055220 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 61431 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 901432928 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.048639 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.805034 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 893969200 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1261 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1244 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 345524950 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 540216674 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 217364695 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 216116185 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 63552241 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2143188368 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 61311 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1846653007 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1596963 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 612532438 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1230905034 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 60758 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 898267437 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.055794 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.806511 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 246353790 27.33% 27.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 156616035 17.37% 44.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 150729220 16.72% 61.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 147768173 16.39% 77.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 103385508 11.47% 89.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58828894 6.53% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 27652970 3.07% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9059576 1.01% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1038762 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 244119309 27.18% 27.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 156083539 17.38% 44.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 150204364 16.72% 61.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 147125554 16.38% 77.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 103909500 11.57% 89.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58948328 6.56% 95.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 27781277 3.09% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9047752 1.01% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1047814 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 901432928 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 898267437 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2653442 16.77% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9987443 63.11% 79.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3184017 20.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2653512 16.69% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 10033753 63.11% 79.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3212720 20.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2723282 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1219442774 66.03% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2721869 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1219400147 66.03% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.18% # Type of FU issued @@ -195,86 +195,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 447111847 24.21% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 177432541 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 447092064 24.21% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177438927 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1846710444 # Type of FU issued -system.cpu.iq.rate 2.007566 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15824902 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008569 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4612265736 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2755596507 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1806213833 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 7972 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 299756 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 262 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1859809264 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2800 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 168051220 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1846653007 # Type of FU issued +system.cpu.iq.rate 2.025668 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15899985 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008610 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4609062574 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2755747075 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1806129295 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 7825 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 296338 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 285 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1859828366 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2757 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 167960734 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 156028104 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 428762 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 273999 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 68179105 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 156114514 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 428176 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 272950 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 68204770 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6544 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6724 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 83937244 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7052726 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1164788 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2143178395 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2770813 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 540130264 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 217339290 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5780 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 918370 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16344 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 273999 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10084956 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5239444 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 15324400 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1818728049 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 438648218 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27982395 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 83935256 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5705090 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1089193 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2143249679 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2772043 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 540216674 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 217364955 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5665 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 876205 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14852 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 272950 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10085276 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5239623 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 15324899 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1818663600 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 438639718 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27989407 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 610505515 # number of memory reference insts executed -system.cpu.iew.exec_branches 170830738 # Number of branches executed -system.cpu.iew.exec_stores 171857297 # Number of stores executed -system.cpu.iew.exec_rate 1.977147 # Inst execution rate -system.cpu.iew.wb_sent 1813502289 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1806214095 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1379770015 # num instructions producing a value -system.cpu.iew.wb_consumers 2939115295 # num instructions consuming a value +system.cpu.iew.exec_refs 610490535 # number of memory reference insts executed +system.cpu.iew.exec_branches 170808194 # Number of branches executed +system.cpu.iew.exec_stores 171850817 # Number of stores executed +system.cpu.iew.exec_rate 1.994965 # Inst execution rate +system.cpu.iew.wb_sent 1813450071 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1806129580 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1379661197 # num instructions producing a value +system.cpu.iew.wb_consumers 2939711936 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.963543 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.469451 # average fanout of values written-back +system.cpu.iew.wb_rate 1.981216 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.469319 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 614215075 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 614283465 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14315916 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 817495684 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.870333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.327982 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14312346 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 814332181 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.877598 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.330573 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 301315612 36.86% 36.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 204371597 25.00% 61.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73328146 8.97% 70.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 95079836 11.63% 82.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30908814 3.78% 86.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28772319 3.52% 89.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16400347 2.01% 91.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11729678 1.43% 93.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 55589335 6.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 298731075 36.68% 36.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 203556250 25.00% 61.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73630894 9.04% 70.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 94876671 11.65% 82.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30957165 3.80% 86.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28752943 3.53% 89.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16466236 2.02% 91.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11737662 1.44% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 55623285 6.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 817495684 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 814332181 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877144 # Number of instructions committed system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -285,68 +285,69 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 55589335 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 55623285 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2905110180 # The number of ROB reads -system.cpu.rob.rob_writes 4370460169 # The number of ROB writes -system.cpu.timesIdled 411218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18442224 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2901981117 # The number of ROB reads +system.cpu.rob.rob_writes 4370596606 # The number of ROB writes +system.cpu.timesIdled 304669 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13359221 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877144 # Number of Instructions Simulated system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated -system.cpu.cpi 1.112469 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.112469 # CPI: Total CPI of All Threads -system.cpu.ipc 0.898901 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.898901 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4004380471 # number of integer regfile reads -system.cpu.int_regfile_writes 2286341091 # number of integer regfile writes -system.cpu.fp_regfile_reads 262 # number of floating regfile reads -system.cpu.misc_regfile_reads 1001920300 # number of misc regfile reads -system.cpu.icache.replacements 10653 # number of replacements -system.cpu.icache.tagsinuse 997.180863 # Cycle average of tags in use -system.cpu.icache.total_refs 183252097 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12174 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 15052.743305 # Average number of references to valid blocks. +system.cpu.cpi 1.102493 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.102493 # CPI: Total CPI of All Threads +system.cpu.ipc 0.907035 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.907035 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4004133317 # number of integer regfile reads +system.cpu.int_regfile_writes 2286262019 # number of integer regfile writes +system.cpu.fp_regfile_reads 284 # number of floating regfile reads +system.cpu.fp_regfile_writes 1 # number of floating regfile writes +system.cpu.misc_regfile_reads 1001892809 # number of misc regfile reads +system.cpu.icache.replacements 5521 # number of replacements +system.cpu.icache.tagsinuse 1042.048866 # Cycle average of tags in use +system.cpu.icache.total_refs 183243707 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7141 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25660.790786 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 997.180863 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.486905 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.486905 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 183258482 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 183258482 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 183258482 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 183258482 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 183258482 # number of overall hits -system.cpu.icache.overall_hits::total 183258482 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 224389 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 224389 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 224389 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 224389 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 224389 # number of overall misses -system.cpu.icache.overall_misses::total 224389 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1641701500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1641701500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1641701500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1641701500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1641701500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1641701500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 183482871 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 183482871 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 183482871 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 183482871 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 183482871 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 183482871 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7316.318982 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 7316.318982 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 7316.318982 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 7316.318982 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 7316.318982 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1042.048866 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.508813 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.508813 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 183260633 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 183260633 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 183260633 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 183260633 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 183260633 # number of overall hits +system.cpu.icache.overall_hits::total 183260633 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 217941 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 217941 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 217941 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 217941 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 217941 # number of overall misses +system.cpu.icache.overall_misses::total 217941 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1509664000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1509664000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1509664000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1509664000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1509664000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1509664000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 183478574 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 183478574 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 183478574 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 183478574 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 183478574 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 183478574 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001188 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001188 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001188 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001188 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001188 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001188 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6926.938942 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6926.938942 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6926.938942 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6926.938942 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6926.938942 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6926.938942 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -357,94 +358,94 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 8 # number of writebacks system.cpu.icache.writebacks::total 8 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2536 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2536 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2536 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2536 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2536 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2536 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 221853 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 221853 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 221853 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 221853 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 221853 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 221853 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915847000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 915847000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915847000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 915847000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915847000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 915847000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001209 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001209 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001209 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001209 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4128.170455 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4128.170455 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4128.170455 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4128.170455 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1622 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1622 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1622 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1622 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1622 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1622 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 216319 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 216319 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 216319 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 216319 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 216319 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 216319 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 823021000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 823021000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 823021000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 823021000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 823021000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 823021000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001179 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001179 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001179 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001179 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001179 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001179 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3804.663483 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3804.663483 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3804.663483 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3804.663483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3804.663483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3804.663483 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2527239 # number of replacements -system.cpu.dcache.tagsinuse 4087.019700 # Cycle average of tags in use -system.cpu.dcache.total_refs 415133448 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2531335 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.997830 # Average number of references to valid blocks. +system.cpu.dcache.replacements 2527069 # number of replacements +system.cpu.dcache.tagsinuse 4086.938445 # Cycle average of tags in use +system.cpu.dcache.total_refs 415239447 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2531165 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 164.050722 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 2117139000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.019700 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997808 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997808 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 266287966 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 266287966 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148171236 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148171236 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 414459202 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414459202 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414459202 # number of overall hits -system.cpu.dcache.overall_hits::total 414459202 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2669585 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2669585 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 988965 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 988965 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3658550 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3658550 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3658550 # number of overall misses -system.cpu.dcache.overall_misses::total 3658550 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39016731000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39016731000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20136479000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20136479000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 59153210000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 59153210000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 59153210000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 59153210000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 268957551 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 268957551 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4086.938445 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997788 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997788 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 266396251 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 266396251 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148172005 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148172005 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 414568256 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414568256 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414568256 # number of overall hits +system.cpu.dcache.overall_hits::total 414568256 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2642162 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2642162 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 988196 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 988196 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3630358 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3630358 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3630358 # number of overall misses +system.cpu.dcache.overall_misses::total 3630358 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33785416000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33785416000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18850913500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18850913500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 52636329500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 52636329500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 52636329500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 52636329500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 269038413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 269038413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418117752 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418117752 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418117752 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418117752 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009926 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009926 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006630 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006630 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008750 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008750 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008750 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008750 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14615.279528 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14615.279528 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20361.164450 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 20361.164450 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16168.484782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16168.484782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16168.484782 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 418198614 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418198614 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418198614 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418198614 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009821 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009821 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006625 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008681 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008681 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008681 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008681 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12787.034255 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12787.034255 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19076.087638 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 19076.087638 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14498.936331 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14498.936331 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14498.936331 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14498.936331 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,144 +454,144 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2229248 # number of writebacks -system.cpu.dcache.writebacks::total 2229248 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 908413 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 908413 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9153 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9153 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 917566 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 917566 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 917566 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 917566 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1761172 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1761172 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 979812 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 979812 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2740984 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2740984 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2740984 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2740984 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14912272500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14912272500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17125192000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17125192000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32037464500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32037464500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32037464500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32037464500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006548 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006548 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006569 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006556 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006556 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006556 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8467.243688 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8467.243688 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.038644 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17478.038644 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11688.307739 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11688.307739 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2302786 # number of writebacks +system.cpu.dcache.writebacks::total 2302786 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 881124 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 881124 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8927 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 8927 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 890051 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 890051 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 890051 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 890051 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1761038 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1761038 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 979269 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 979269 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2740307 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2740307 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2740307 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2740307 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11264952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11264952000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15850782000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15850782000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27115734000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27115734000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27115734000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27115734000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006546 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006546 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006565 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006565 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006553 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006553 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006553 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006553 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 6396.768270 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 6396.768270 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16186.341036 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16186.341036 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9895.144595 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 9895.144595 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9895.144595 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 9895.144595 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 574865 # number of replacements -system.cpu.l2cache.tagsinuse 21613.693664 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3194256 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 594053 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.377056 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 253036052000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 13760.767426 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 63.333478 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7789.592760 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.419945 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001933 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.237720 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.659598 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 6154 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1427336 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1433490 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2229256 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2229256 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1290 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1290 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 524130 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 524130 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 6154 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1951466 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1957620 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 6154 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1951466 # number of overall hits -system.cpu.l2cache.overall_hits::total 1957620 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 5926 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 332758 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 338684 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 208352 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 208352 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 247027 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 247027 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 5926 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 579785 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 585711 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 5926 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 579785 # number of overall misses -system.cpu.l2cache.overall_misses::total 585711 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 203005500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11360844500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11563850000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9809000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 9809000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8462790000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8462790000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 203005500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 19823634500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20026640000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 203005500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 19823634500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20026640000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 12080 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1760094 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1772174 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2229256 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2229256 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 209642 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 209642 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771157 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771157 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12080 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2531251 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2543331 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12080 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2531251 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2543331 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.490563 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189057 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.191112 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993847 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993847 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320333 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.320333 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490563 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229051 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.230293 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490563 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229051 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.230293 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.749916 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.461663 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34143.478877 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.078982 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.078982 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.562829 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.562829 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34192.016199 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.749916 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34191.354554 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34192.016199 # average overall miss latency +system.cpu.l2cache.replacements 408621 # number of replacements +system.cpu.l2cache.tagsinuse 29300.466705 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3609267 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 440961 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 8.185003 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 219912062000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21087.117194 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 148.252410 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8065.097101 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.643528 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.004524 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.246127 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.894179 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3623 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1537767 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1541390 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2302794 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2302794 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1289 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1289 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 561962 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 561962 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3623 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2099729 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2103352 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3623 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2099729 # number of overall hits +system.cpu.l2cache.overall_hits::total 2103352 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3448 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 222182 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 225630 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 207844 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 207844 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 209183 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 209183 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3448 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 431365 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 434813 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3448 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 431365 # number of overall misses +system.cpu.l2cache.overall_misses::total 434813 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 118183500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7588288000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 7706471500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 10472000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 10472000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7166759500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7166759500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 118183500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14755047500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14873231000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 118183500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14755047500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14873231000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7071 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1759949 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1767020 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2302794 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2302794 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 209133 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 209133 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771145 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771145 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 7071 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2531094 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2538165 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7071 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2531094 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2538165 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.487626 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.126243 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.127690 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993836 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993836 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.271263 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.271263 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.487626 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.170426 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.171310 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.487626 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.170426 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.171310 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34275.957077 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34153.477779 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34155.349466 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 50.383942 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 50.383942 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34260.716693 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34260.716693 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34275.957077 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34205.481437 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34206.040298 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34275.957077 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34205.481437 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34206.040298 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -599,60 +600,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 411201 # number of writebacks -system.cpu.l2cache.writebacks::total 411201 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5926 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 332758 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 338684 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 208352 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 208352 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 247027 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 247027 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5926 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 579785 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 585711 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5926 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 579785 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 585711 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183905000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10323225500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10507130500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6459209000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6459209000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7658508000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7658508000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183905000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17981733500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18165638500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183905000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17981733500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18165638500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189057 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191112 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993847 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993847 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320333 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.320333 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.230293 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.230293 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31023.403822 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.425472 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31002.716302 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31014.678741 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 324864 # number of writebacks +system.cpu.l2cache.writebacks::total 324864 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3448 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222182 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 225630 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 207844 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 207844 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209183 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 209183 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3448 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 431365 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 434813 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3448 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 431365 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 434813 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 107086500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6894107000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7001193500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6443438500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6443438500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6484873000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6484873000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 107086500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13378980000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13486066500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 107086500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13378980000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13486066500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.487626 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126243 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127690 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993836 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993836 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271263 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271263 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.487626 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170426 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.171310 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.487626 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170426 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.171310 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.569606 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31029.097767 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31029.532864 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.320702 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.320702 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.956101 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.956101 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.569606 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31015.450952 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31015.784947 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.569606 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31015.450952 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31015.784947 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |