diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt | 1629 |
1 files changed, 824 insertions, 805 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 3384a1591..2dc4a1c77 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.417996 # Number of seconds simulated -sim_ticks 417996021500 # Number of ticks simulated -final_tick 417996021500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.417249 # Number of seconds simulated +sim_ticks 417248608500 # Number of ticks simulated +final_tick 417248608500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98610 # Simulator instruction rate (inst/s) -host_op_rate 182341 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49848381 # Simulator tick rate (ticks/s) -host_mem_usage 430328 # Number of bytes of host memory used -host_seconds 8385.35 # Real time elapsed on the host +host_inst_rate 95567 # Simulator instruction rate (inst/s) +host_op_rate 176715 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48224052 # Simulator tick rate (ticks/s) +host_mem_usage 428536 # Number of bytes of host memory used +host_seconds 8652.29 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24536320 # Number of bytes read from this memory -system.physmem.bytes_read::total 24763520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18818240 # Number of bytes written to this memory -system.physmem.bytes_written::total 18818240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383380 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386930 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294035 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294035 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 543546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58699889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59243435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 543546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 543546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45020141 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45020141 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45020141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 543546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58699889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104263576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386930 # Number of read requests accepted -system.physmem.writeReqs 294035 # Number of write requests accepted -system.physmem.readBursts 386930 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294035 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24740928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue -system.physmem.bytesWritten 18817024 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24763520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18818240 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 222784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24527040 # Number of bytes read from this memory +system.physmem.bytes_read::total 24749824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18883520 # Number of bytes written to this memory +system.physmem.bytes_written::total 18883520 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3481 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383235 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386716 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295055 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295055 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 533936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58782796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59316732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 533936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 533936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45257239 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45257239 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45257239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 533936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58782796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104573971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386716 # Number of read requests accepted +system.physmem.writeReqs 295055 # Number of write requests accepted +system.physmem.readBursts 386716 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295055 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24729280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue +system.physmem.bytesWritten 18881664 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24749824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18883520 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 195133 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24110 # Per bank write bursts -system.physmem.perBankRdBursts::1 26511 # Per bank write bursts -system.physmem.perBankRdBursts::2 24689 # Per bank write bursts -system.physmem.perBankRdBursts::3 24586 # Per bank write bursts -system.physmem.perBankRdBursts::4 23301 # Per bank write bursts -system.physmem.perBankRdBursts::5 23773 # Per bank write bursts -system.physmem.perBankRdBursts::6 24463 # Per bank write bursts -system.physmem.perBankRdBursts::7 24300 # Per bank write bursts -system.physmem.perBankRdBursts::8 23625 # Per bank write bursts -system.physmem.perBankRdBursts::9 23952 # Per bank write bursts -system.physmem.perBankRdBursts::10 24787 # Per bank write bursts -system.physmem.perBankRdBursts::11 24070 # Per bank write bursts -system.physmem.perBankRdBursts::12 23353 # Per bank write bursts -system.physmem.perBankRdBursts::13 22981 # Per bank write bursts -system.physmem.perBankRdBursts::14 24097 # Per bank write bursts -system.physmem.perBankRdBursts::15 23979 # Per bank write bursts -system.physmem.perBankWrBursts::0 18543 # Per bank write bursts -system.physmem.perBankWrBursts::1 19847 # Per bank write bursts -system.physmem.perBankWrBursts::2 18947 # Per bank write bursts -system.physmem.perBankWrBursts::3 18939 # Per bank write bursts -system.physmem.perBankWrBursts::4 18047 # Per bank write bursts -system.physmem.perBankWrBursts::5 18457 # Per bank write bursts -system.physmem.perBankWrBursts::6 18996 # Per bank write bursts -system.physmem.perBankWrBursts::7 18981 # Per bank write bursts -system.physmem.perBankWrBursts::8 18548 # Per bank write bursts -system.physmem.perBankWrBursts::9 18168 # Per bank write bursts -system.physmem.perBankWrBursts::10 18839 # Per bank write bursts -system.physmem.perBankWrBursts::11 17728 # Per bank write bursts -system.physmem.perBankWrBursts::12 17372 # Per bank write bursts -system.physmem.perBankWrBursts::13 16973 # Per bank write bursts -system.physmem.perBankWrBursts::14 17820 # Per bank write bursts -system.physmem.perBankWrBursts::15 17811 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 188421 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24059 # Per bank write bursts +system.physmem.perBankRdBursts::1 26427 # Per bank write bursts +system.physmem.perBankRdBursts::2 24735 # Per bank write bursts +system.physmem.perBankRdBursts::3 24592 # Per bank write bursts +system.physmem.perBankRdBursts::4 23512 # Per bank write bursts +system.physmem.perBankRdBursts::5 23783 # Per bank write bursts +system.physmem.perBankRdBursts::6 24571 # Per bank write bursts +system.physmem.perBankRdBursts::7 24367 # Per bank write bursts +system.physmem.perBankRdBursts::8 23708 # Per bank write bursts +system.physmem.perBankRdBursts::9 23929 # Per bank write bursts +system.physmem.perBankRdBursts::10 24776 # Per bank write bursts +system.physmem.perBankRdBursts::11 24016 # Per bank write bursts +system.physmem.perBankRdBursts::12 23246 # Per bank write bursts +system.physmem.perBankRdBursts::13 22935 # Per bank write bursts +system.physmem.perBankRdBursts::14 23871 # Per bank write bursts +system.physmem.perBankRdBursts::15 23868 # Per bank write bursts +system.physmem.perBankWrBursts::0 18618 # Per bank write bursts +system.physmem.perBankWrBursts::1 19926 # Per bank write bursts +system.physmem.perBankWrBursts::2 18978 # Per bank write bursts +system.physmem.perBankWrBursts::3 19008 # Per bank write bursts +system.physmem.perBankWrBursts::4 18159 # Per bank write bursts +system.physmem.perBankWrBursts::5 18511 # Per bank write bursts +system.physmem.perBankWrBursts::6 19142 # Per bank write bursts +system.physmem.perBankWrBursts::7 19088 # Per bank write bursts +system.physmem.perBankWrBursts::8 18666 # Per bank write bursts +system.physmem.perBankWrBursts::9 18203 # Per bank write bursts +system.physmem.perBankWrBursts::10 18897 # Per bank write bursts +system.physmem.perBankWrBursts::11 17760 # Per bank write bursts +system.physmem.perBankWrBursts::12 17400 # Per bank write bursts +system.physmem.perBankWrBursts::13 16992 # Per bank write bursts +system.physmem.perBankWrBursts::14 17815 # Per bank write bursts +system.physmem.perBankWrBursts::15 17863 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 417995980500 # Total gap between requests +system.physmem.totGap 417248585500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386930 # Read request sizes (log2) +system.physmem.readPktSize::6 386716 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294035 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295055 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381306 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,48 +144,48 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6571 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 16924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -193,246 +193,248 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.402912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.387317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.474139 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54872 37.21% 37.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39881 27.05% 64.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13729 9.31% 73.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7544 5.12% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5538 3.76% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3897 2.64% 85.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3110 2.11% 87.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2694 1.83% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16184 10.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147449 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17448 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.155834 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.387263 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17435 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147457 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.740616 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.463963 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.226581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54784 37.15% 37.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40098 27.19% 64.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13706 9.29% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7465 5.06% 78.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5444 3.69% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3767 2.55% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3056 2.07% 87.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2830 1.92% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16307 11.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147457 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17513 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.062525 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 217.476315 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17502 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17448 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17448 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.850986 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.777295 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.658929 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17245 98.84% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 147 0.84% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.14% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 10 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 5 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17513 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17513 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.846114 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.774956 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.557273 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17320 98.90% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 139 0.79% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.18% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 5 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.02% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17448 # Writes before turning the bus around for reads -system.physmem.totQLat 4282714250 # Total ticks spent queuing -system.physmem.totMemAccLat 11531033000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932885000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11078.55 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::212-215 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17513 # Writes before turning the bus around for reads +system.physmem.totQLat 4300099500 # Total ticks spent queuing +system.physmem.totMemAccLat 11545005750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1931975000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11128.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29828.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.24 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.02 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29878.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 59.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.25 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 59.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.81 # Data bus utilization in percentage +system.physmem.busUtil 0.82 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.74 # Average write queue length when enqueuing -system.physmem.readRowHits 318033 # Number of row buffer hits during reads -system.physmem.writeRowHits 215097 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes -system.physmem.avgGap 613828.88 # Average gap between requests -system.physmem.pageHitRate 78.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 567967680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 309903000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1526584800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 976607280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63862686000 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 194773803000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 289318578240 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.167087 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 323459791500 # Time in different power states -system.physmem_0.memoryStateTime::REF 13957580000 # Time in different power states +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.79 # Average write queue length when enqueuing +system.physmem.readRowHits 318002 # Number of row buffer hits during reads +system.physmem.writeRowHits 215948 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.19 # Row buffer hit rate for writes +system.physmem.avgGap 612006.94 # Average gap between requests +system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 569698920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 310847625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1529026200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 981072000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27252204720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63410789430 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 194721715500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 288775354395 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.105150 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 323379971500 # Time in different power states +system.physmem_0.memoryStateTime::REF 13932620000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80574068000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 79931501500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 546278040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 298068375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1488138600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928098000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61813739205 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 196571124750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 288946473450 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.276862 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 326467583000 # Time in different power states -system.physmem_1.memoryStateTime::REF 13957580000 # Time in different power states +system.physmem_1.actEnergy 544690440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 297202125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1484246400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 930262320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 27252204720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61581182625 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 196326633750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 288416422380 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.244901 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 326066613500 # Time in different power states +system.physmem_1.memoryStateTime::REF 13932620000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77566206500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77244604500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 230262495 # Number of BP lookups -system.cpu.branchPred.condPredicted 230262495 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9742888 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131521089 # Number of BTB lookups -system.cpu.branchPred.BTBHits 128797905 # Number of BTB hits +system.cpu.branchPred.lookups 230038764 # Number of BP lookups +system.cpu.branchPred.condPredicted 230038764 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9737010 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 131438605 # Number of BTB lookups +system.cpu.branchPred.BTBHits 128726788 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.929470 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27751403 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1472504 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.936818 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27748214 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1467706 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 835992044 # number of cpu cycles simulated +system.cpu.numCycles 834497218 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 185232757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1269385486 # Number of instructions fetch has processed -system.cpu.fetch.Branches 230262495 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 156549308 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 639500926 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20224879 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 485 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 100878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 834249 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1640 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 179526470 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2741098 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 835783416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.825648 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.381813 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 185109509 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1269285801 # Number of instructions fetch has processed +system.cpu.fetch.Branches 230038764 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 156475002 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638168020 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20207441 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 514 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 99542 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 817516 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1330 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 56 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 179424674 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2717056 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 834300207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.829871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.382747 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 428043161 51.21% 51.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 33828750 4.05% 55.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32944896 3.94% 59.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33232373 3.98% 63.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27262474 3.26% 66.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27644327 3.31% 69.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 36950250 4.42% 74.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33776724 4.04% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 182100461 21.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 426804407 51.16% 51.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 33711236 4.04% 55.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 32817404 3.93% 59.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33341418 4.00% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27188546 3.26% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27662073 3.32% 69.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 36987842 4.43% 74.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33698291 4.04% 78.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 182088990 21.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 835783416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.275436 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.518418 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127710765 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 376117098 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240273770 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81569344 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10112439 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2225700133 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10112439 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159685424 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 160601450 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 42674 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285796855 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219544574 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2175664077 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 185857 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 136149821 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24262583 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 49140413 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2279803570 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5502723498 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3499975195 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 67752 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 834300207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.275662 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.521019 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127532754 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 374895763 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 240450543 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81317427 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10103720 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2225154931 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10103720 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159590885 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 159861387 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 39705 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285625371 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 219079139 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2175033402 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 169320 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 136042771 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24241877 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 48673196 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2279253847 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5500789642 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3498971898 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 55892 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 665762716 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3202 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3008 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 414696821 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528426075 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 209872279 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 239265917 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72168406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2101339198 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25266 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1827025844 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 429417 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 572375763 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 974716036 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24714 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 835783416 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.186004 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.072692 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 665212993 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3161 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2925 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 415266866 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 528334914 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 209874644 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 239338770 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72144908 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2101019043 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25133 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1826920514 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 398452 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 572055475 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 973771254 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24581 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 834300207 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.189764 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.073153 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 256113706 30.64% 30.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 125601677 15.03% 45.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 119268677 14.27% 59.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 111065913 13.29% 73.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 92467369 11.06% 84.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61706105 7.38% 91.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43038473 5.15% 96.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19113733 2.29% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7407763 0.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 254789239 30.54% 30.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 125577373 15.05% 45.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 119153367 14.28% 59.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 111141032 13.32% 73.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 92244378 11.06% 84.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61717114 7.40% 91.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43107761 5.17% 96.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19155881 2.30% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7414062 0.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 835783416 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 834300207 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11312018 42.37% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12328079 46.18% 88.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3055344 11.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11334405 42.48% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12275528 46.01% 88.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3069676 11.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2717945 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1211291441 66.30% 66.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 390219 0.02% 66.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881058 0.21% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 119 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2718617 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1211210104 66.30% 66.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 389740 0.02% 66.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881078 0.21% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 127 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 36 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 409 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 27 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 416 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued @@ -454,84 +456,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435052343 23.81% 90.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173692274 9.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435004125 23.81% 90.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173716278 9.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1827025844 # Type of FU issued -system.cpu.iq.rate 2.185458 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26695441 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014611 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4516927324 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2674001021 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1796885315 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 32638 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 71794 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7253 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1850988135 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 15205 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185719617 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1826920514 # Type of FU issued +system.cpu.iq.rate 2.189247 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26679609 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014604 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4515187521 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2673359658 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1796857140 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 31775 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 70770 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6885 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1850866868 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 14638 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185770181 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144326663 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 210089 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 386690 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 60712093 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 144235066 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213448 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 384677 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 60714458 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19150 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1058 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19450 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 994 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10112439 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 107482997 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6407343 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2101364464 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 396756 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528428820 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 209872279 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7401 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1872023 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3639843 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 386690 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5742846 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4583278 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10326124 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1805593119 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 428868135 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21432725 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10103720 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 107027275 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6171947 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2101044176 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 397040 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 528337223 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 209874644 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7154 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1885059 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3390398 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 384677 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5738634 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4563911 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10302545 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1805509782 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 428792858 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21410732 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 598999412 # number of memory reference insts executed -system.cpu.iew.exec_branches 171793179 # Number of branches executed -system.cpu.iew.exec_stores 170131277 # Number of stores executed -system.cpu.iew.exec_rate 2.159821 # Inst execution rate -system.cpu.iew.wb_sent 1802187162 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1796892568 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1367992688 # num instructions producing a value -system.cpu.iew.wb_consumers 2090178306 # num instructions consuming a value +system.cpu.iew.exec_refs 598991015 # number of memory reference insts executed +system.cpu.iew.exec_branches 171766085 # Number of branches executed +system.cpu.iew.exec_stores 170198157 # Number of stores executed +system.cpu.iew.exec_rate 2.163590 # Inst execution rate +system.cpu.iew.wb_sent 1802110409 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1796864025 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1368049337 # num instructions producing a value +system.cpu.iew.wb_consumers 2090115063 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.149413 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654486 # average fanout of values written-back +system.cpu.iew.wb_rate 2.153229 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654533 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 572454923 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 572135204 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9832210 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 758082487 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.016916 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.546878 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9825001 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 756651956 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.020729 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.548081 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 289327383 38.17% 38.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 175257093 23.12% 61.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57420140 7.57% 68.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86252758 11.38% 80.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27155131 3.58% 83.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27117110 3.58% 87.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9822533 1.30% 88.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8850930 1.17% 89.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 76879409 10.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 287953386 38.06% 38.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175292333 23.17% 61.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57344837 7.58% 68.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86221937 11.40% 80.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27113369 3.58% 83.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27107052 3.58% 87.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9811804 1.30% 88.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8976581 1.19% 89.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76830657 10.15% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 758082487 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 756651956 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -577,338 +579,344 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 76879409 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2782646702 # The number of ROB reads -system.cpu.rob.rob_writes 4280772798 # The number of ROB writes -system.cpu.timesIdled 2318 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 208628 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 76830657 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2780945204 # The number of ROB reads +system.cpu.rob.rob_writes 4280083493 # The number of ROB writes +system.cpu.timesIdled 2292 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 197011 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.011023 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.011023 # CPI: Total CPI of All Threads -system.cpu.ipc 0.989097 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.989097 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2762036439 # number of integer regfile reads -system.cpu.int_regfile_writes 1465125360 # number of integer regfile writes -system.cpu.fp_regfile_reads 7563 # number of floating regfile reads -system.cpu.fp_regfile_writes 476 # number of floating regfile writes -system.cpu.cc_regfile_reads 600921582 # number of cc regfile reads -system.cpu.cc_regfile_writes 409666959 # number of cc regfile writes -system.cpu.misc_regfile_reads 990189445 # number of misc regfile reads +system.cpu.cpi 1.009216 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.009216 # CPI: Total CPI of All Threads +system.cpu.ipc 0.990869 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.990869 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2762017076 # number of integer regfile reads +system.cpu.int_regfile_writes 1465005269 # number of integer regfile writes +system.cpu.fp_regfile_reads 7183 # number of floating regfile reads +system.cpu.fp_regfile_writes 481 # number of floating regfile writes +system.cpu.cc_regfile_reads 600929280 # number of cc regfile reads +system.cpu.cc_regfile_writes 409654003 # number of cc regfile writes +system.cpu.misc_regfile_reads 990121594 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2534281 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.998981 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 387677401 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2538377 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 152.726487 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.998981 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998047 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998047 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2534273 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.021333 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 387553004 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2538369 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 152.677961 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1679458500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.021333 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 873 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3167 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3168 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 784481905 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 784481905 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 239023256 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 239023256 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148173502 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148173502 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 387196758 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 387196758 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 387196758 # number of overall hits -system.cpu.dcache.overall_hits::total 387196758 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2788306 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2788306 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 986700 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 986700 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3775006 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3775006 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3775006 # number of overall misses -system.cpu.dcache.overall_misses::total 3775006 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 60089695608 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 60089695608 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31307364104 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31307364104 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91397059712 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91397059712 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91397059712 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91397059712 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 241811562 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 241811562 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 784232137 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 784232137 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 238902536 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 238902536 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148180257 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148180257 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 387082793 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 387082793 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 387082793 # number of overall hits +system.cpu.dcache.overall_hits::total 387082793 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2784146 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2784146 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 979945 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 979945 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3764091 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3764091 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3764091 # number of overall misses +system.cpu.dcache.overall_misses::total 3764091 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59451413500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59451413500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30841040499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30841040499 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90292453999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90292453999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90292453999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90292453999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 241686682 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 241686682 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 390971764 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 390971764 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 390971764 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 390971764 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011531 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011531 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006615 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006615 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009655 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009655 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009655 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009655 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21550.610158 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21550.610158 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31729.364654 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31729.364654 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24211.103164 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24211.103164 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10735 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 46 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1081 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.930620 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9.200000 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 390846884 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 390846884 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 390846884 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 390846884 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011520 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011520 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006570 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006570 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009631 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009631 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009631 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009631 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21353.554555 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21353.554555 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31472.215787 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31472.215787 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23987.850984 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23987.850984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23987.850984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23987.850984 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10871 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 28 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1128 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.637411 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2332980 # number of writebacks -system.cpu.dcache.writebacks::total 2332980 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1021252 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1021252 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18400 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18400 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1039652 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1039652 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1039652 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1039652 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767054 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1767054 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968300 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 968300 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2735354 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2735354 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2735354 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2735354 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32779677502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32779677502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29519299643 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 29519299643 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62298977145 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 62298977145 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62298977145 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 62298977145 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007308 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007308 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006996 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006996 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.467333 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.467333 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30485.696213 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30485.696213 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2332718 # number of writebacks +system.cpu.dcache.writebacks::total 2332718 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1016180 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1016180 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19269 # 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number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2728642 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33608501500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33608501500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29628930000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29628930000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63237431500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63237431500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63237431500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63237431500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006441 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006441 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006981 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006981 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006981 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006981 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19009.698999 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19009.698999 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30841.751017 # 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number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1336227738 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1336227738 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1336227738 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1336227738 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 179526469 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 179526469 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 179526469 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 179526469 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 179526469 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 179526469 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001161 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001161 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001161 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001161 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001161 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001161 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6409.626895 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6409.626895 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6409.626895 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6409.626895 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6409.626895 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6409.626895 # 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number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 201632 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 201632 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 201632 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 201632 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 201632 # number of overall misses +system.cpu.icache.overall_misses::total 201632 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1282836497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1282836497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1282836497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1282836497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1282836497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1282836497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 179424674 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 179424674 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 179424674 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 179424674 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 179424674 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 179424674 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001124 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001124 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001124 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001124 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001124 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001124 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6362.266391 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6362.266391 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6362.266391 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6362.266391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6362.266391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6362.266391 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 972 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 81.133333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 60.750000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2630 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2630 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2630 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2630 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2630 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2630 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205842 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 205842 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 205842 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 205842 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 205842 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 205842 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 900667759 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 900667759 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 900667759 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 900667759 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 900667759 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 900667759 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001147 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001147 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001147 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4375.529576 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4375.529576 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4375.529576 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4375.529576 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4375.529576 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4375.529576 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2599 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2599 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2599 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2599 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2599 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2599 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 199033 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 199033 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 199033 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 199033 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 199033 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 199033 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 971187998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 971187998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 971187998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 971187998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 971187998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 971187998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001109 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001109 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001109 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001109 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001109 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001109 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4879.532530 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4879.532530 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4879.532530 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4879.532530 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4879.532530 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4879.532530 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 354249 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29619.496841 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3704141 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 386604 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.581228 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 197893481000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21082.499774 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 254.372713 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8282.624354 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.643387 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007763 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.252766 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68454.807142 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18051.645277 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18051.645277 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66860.724177 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66860.724177 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1999 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1999 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 188379 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 188379 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206660 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206660 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3482 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3482 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176617 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176617 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3482 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 383277 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 386759 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3482 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 383277 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 386759 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3964257964 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3964257964 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14315409500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14315409500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 248098000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 248098000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12445958500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12445958500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 248098000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26761368000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27009466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 248098000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26761368000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27009466000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990046 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990046 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268105 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268105 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.402869 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099922 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099922 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150993 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151848 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150993 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151848 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21044.054613 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21044.054613 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69270.345011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69270.345011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71251.579552 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71251.579552 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70468.632691 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70468.632691 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71251.579552 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69822.525223 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69835.391032 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71251.579552 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69822.525223 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69835.391032 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1972695 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1972693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2332980 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 196977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 196977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771524 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214584 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803688 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8018272 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311766848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312326336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 197098 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5274176 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1966585 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2627773 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 256159 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 190273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 190273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 770816 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 770816 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 199033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1767553 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214213 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7980639 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8194852 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311749568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312302656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 544429 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5822983 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.060800 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.238964 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5274176 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5468944 93.92% 93.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 354039 6.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5274176 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4998685151 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5822983 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5095186894 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 309293990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 298551493 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3989146355 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 179950 # Transaction distribution -system.membus.trans_dist::ReadResp 179949 # Transaction distribution -system.membus.trans_dist::Writeback 294035 # Transaction distribution -system.membus.trans_dist::UpgradeReq 195133 # Transaction distribution -system.membus.trans_dist::UpgradeResp 195133 # Transaction distribution -system.membus.trans_dist::ReadExReq 206980 # Transaction distribution -system.membus.trans_dist::ReadExResp 206980 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1458160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1458160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1458160 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43581696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43581696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43581696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.respLayer1.occupancy 3902690569 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadResp 180098 # Transaction distribution +system.membus.trans_dist::Writeback 295055 # Transaction distribution +system.membus.trans_dist::CleanEvict 57423 # Transaction distribution +system.membus.trans_dist::UpgradeReq 188421 # Transaction distribution +system.membus.trans_dist::UpgradeResp 188421 # Transaction distribution +system.membus.trans_dist::ReadExReq 206618 # Transaction distribution +system.membus.trans_dist::ReadExResp 206618 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180098 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1502752 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1502752 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1502752 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43633344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43633344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43633344 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 876098 # Request fanout histogram +system.membus.snoop_fanout::samples 927615 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 876098 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 927615 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 876098 # Request fanout histogram -system.membus.reqLayer0.occupancy 2246796268 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 927615 # Request fanout histogram +system.membus.reqLayer0.occupancy 2233739536 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2437948408 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2422494891 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- |