diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 4d088ccd8..38495841e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.650501 # Nu sim_ticks 1650501252500 # Number of ticks simulated final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 482495 # Simulator instruction rate (inst/s) -host_op_rate 892859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 963127288 # Simulator tick rate (ticks/s) -host_mem_usage 277668 # Number of bytes of host memory used -host_seconds 1713.69 # Real time elapsed on the host +host_inst_rate 943240 # Simulator instruction rate (inst/s) +host_op_rate 1745467 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1882837072 # Simulator tick rate (ticks/s) +host_mem_usage 326104 # Number of bytes of host memory used +host_seconds 876.60 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory @@ -36,9 +37,14 @@ system.physmem.bw_total::writebacks 11369424 # To system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 3301002505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -99,6 +105,7 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2517016 # number of replacements system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. @@ -117,6 +124,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits @@ -205,6 +213,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1253 # number of replacements system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. @@ -223,6 +232,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits @@ -291,6 +301,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 348438 # number of replacements system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. @@ -312,6 +323,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits @@ -458,6 +470,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution @@ -490,6 +503,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 4221000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 174499 # Transaction distribution system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution system.membus.trans_dist::CleanEvict 53507 # Transaction distribution |