diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt | 690 |
1 files changed, 345 insertions, 345 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 58e8c99ef..aee130b35 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,111 +1,111 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.650601 # Number of seconds simulated -sim_ticks 1650600522500 # Number of ticks simulated -final_tick 1650600522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.650501 # Number of seconds simulated +sim_ticks 1650501252500 # Number of ticks simulated +final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236277 # Simulator instruction rate (inst/s) -host_op_rate 436901 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 471636555 # Simulator tick rate (ticks/s) -host_mem_usage 314152 # Number of bytes of host memory used -host_seconds 3499.73 # Real time elapsed on the host -sim_insts 826906380 # Number of instructions simulated -sim_ops 1529035683 # Number of ops (including micro ops) simulated +host_inst_rate 239314 # Simulator instruction rate (inst/s) +host_op_rate 442851 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 477703969 # Simulator tick rate (ticks/s) +host_mem_usage 314168 # Number of bytes of host memory used +host_seconds 3455.07 # Real time elapsed on the host +sim_insts 826847304 # Number of instructions simulated +sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24258880 # Number of bytes read from this memory -system.physmem.bytes_read::total 24374656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory +system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18765184 # Number of bytes written to this memory -system.physmem.bytes_written::total 18765184 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory +system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 379045 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380854 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293206 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293206 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 70142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14697002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14767144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 70142 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 70142 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11368701 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11368701 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11368701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 70142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14697002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26135845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3301201045 # number of cpu cycles simulated +system.cpu.numCycles 3301002505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826906380 # Number of instructions committed -system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses +system.cpu.committedInsts 826847304 # Number of instructions committed +system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 35346287 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls -system.cpu.num_int_insts 1526653037 # number of integer instructions +system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls +system.cpu.num_int_insts 1527470226 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read -system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written +system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read +system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read -system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written -system.cpu.num_mem_refs 533282319 # number of memory refs -system.cpu.num_load_insts 384117825 # Number of load instructions -system.cpu.num_store_insts 149164494 # Number of store instructions +system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written +system.cpu.num_mem_refs 533241508 # number of memory refs +system.cpu.num_load_insts 384083313 # Number of load instructions +system.cpu.num_store_insts 149158195 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3301201044.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 149762544 # Number of branches fetched -system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction -system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction -system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction -system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction -system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction +system.cpu.Branches 149981740 # Number of branches fetched +system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction +system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction +system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction +system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction +system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1529035683 # Class of executed instruction -system.cpu.dcache.tags.replacements 2515885 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.387052 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 530762383 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2519981 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 210.621581 # Average number of references to valid blocks. +system.cpu.op_class::total 1530082521 # Class of executed instruction +system.cpu.dcache.tags.replacements 2517016 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.387052 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -115,56 +115,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1069084709 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1069084709 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 382389020 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382389020 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148373363 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148373363 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530762383 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530762383 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530762383 # number of overall hits -system.cpu.dcache.overall_hits::total 530762383 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1728834 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1728834 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791147 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791147 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2519981 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2519981 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2519981 # number of overall misses -system.cpu.dcache.overall_misses::total 2519981 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30936646500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30936646500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20396358500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20396358500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51333005000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51333005000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51333005000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51333005000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384117854 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384117854 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149164510 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149164510 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533282364 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533282364 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533282364 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533282364 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004501 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004501 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005304 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005304 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004725 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004725 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004725 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004725 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17894.515321 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17894.515321 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25780.744286 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25780.744286 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20370.393666 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20370.393666 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits +system.cpu.dcache.overall_hits::total 530720441 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses +system.cpu.dcache.overall_misses::total 2521112 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,50 +173,50 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2324237 # number of writebacks -system.cpu.dcache.writebacks::total 2324237 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1728834 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1728834 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791147 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 791147 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2519981 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2519981 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2519981 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2519981 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29207812500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29207812500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19605211500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19605211500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48813024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 48813024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48813024000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 48813024000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004501 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004501 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.004725 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.004725 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16894.515321 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16894.515321 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24780.744286 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24780.744286 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks +system.cpu.dcache.writebacks::total 2325221 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29218757500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29218757500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19607887500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19607887500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48826645000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.377882 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1068379901 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 379665.920753 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.377882 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430360 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430360 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id @@ -224,44 +224,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 7 system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2136768244 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2136768244 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1068379901 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1068379901 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1068379901 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1068379901 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1068379901 # number of overall hits -system.cpu.icache.overall_hits::total 1068379901 # number of overall hits +system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits +system.cpu.icache.overall_hits::total 1068307822 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 125256000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 125256000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 125256000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 125256000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 125256000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 125256000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1068382715 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1068382715 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1068382715 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1068382715 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1068382715 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1068382715 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1068310636 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1068310636 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.727079 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44511.727079 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44511.727079 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44511.727079 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,126 +278,126 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122442000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 122442000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122442000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 122442000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122442000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 122442000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122441000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 122441000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122441000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 122441000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122441000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 122441000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.727079 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.727079 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.727079 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.727079 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.727079 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.727079 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 348437 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29288.556947 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3849932 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380797 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.110195 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 348438 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20940.547795 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.260188 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.748964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639055 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.639064 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.250755 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.893816 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.250751 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.893821 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8218 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24062 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41491408 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41491408 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 2324237 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2324237 # number of WritebackDirty hits +system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41509728 # 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miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150416 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.150965 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150349 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.150898 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150416 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.150965 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150349 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.150898 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.885019 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18852338500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89567000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762771500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18852338500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89566000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89566000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89566000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762821000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18852387000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89566000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762821000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18852387000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260831 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260831 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260758 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260758 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099888 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099888 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099836 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099836 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.150965 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150349 # 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average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234526 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234526 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.332228 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5039933 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2517138 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1731648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2617444 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 246878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 791147 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 791147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1728834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7555847 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7562728 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310029952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310290240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 348437 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2871232 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348438 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.024532 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2869503 99.94% 99.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2871232 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4845456500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3779971500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 174498 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293206 # Transaction distribution +system.membus.trans_dist::ReadResp 174499 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution system.membus.trans_dist::CleanEvict 53507 # Transaction distribution system.membus.trans_dist::ReadExReq 206356 # Transaction distribution system.membus.trans_dist::ReadExResp 206356 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174498 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108421 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108421 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1108421 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43139840 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 727567 # Request fanout histogram +system.membus.snoop_fanout::samples 727569 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 727567 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 727567 # Request fanout histogram -system.membus.reqLayer0.occupancy 1900421500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 727569 # Request fanout histogram +system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1904270000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |