diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt | 128 |
1 files changed, 64 insertions, 64 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index ae8bc7b58..9139f6ef0 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.652607 # Number of seconds simulated -sim_ticks 1652606875000 # Number of ticks simulated -final_tick 1652606875000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1652606827000 # Number of ticks simulated +final_tick 1652606827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 673883 # Simulator instruction rate (inst/s) -host_op_rate 1246085 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1346830511 # Simulator tick rate (ticks/s) -host_mem_usage 232676 # Number of bytes of host memory used -host_seconds 1227.03 # Real time elapsed on the host -sim_insts 826877145 # Number of instructions simulated -sim_ops 1528988757 # Number of ops (including micro ops) simulated +host_inst_rate 715148 # Simulator instruction rate (inst/s) +host_op_rate 1322389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1429304042 # Simulator tick rate (ticks/s) +host_mem_usage 236556 # Number of bytes of host memory used +host_seconds 1156.23 # Real time elapsed on the host +sim_insts 826877110 # Number of instructions simulated +sim_ops 1528988700 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 27359872 # Number of bytes read from this memory system.physmem.bytes_read::total 27483456 # Number of bytes read from this memory @@ -24,54 +24,54 @@ system.physmem.num_reads::total 429429 # Nu system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 74781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 16555584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16630365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 16555585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16630366 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 74781 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 74781 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12530796 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12530796 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12530796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 12530797 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12530797 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12530797 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 74781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 16555584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 16555585 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 29161162 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3305213750 # number of cpu cycles simulated +system.cpu.numCycles 3305213654 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826877145 # Number of instructions committed -system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.committedInsts 826877110 # Number of instructions committed +system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317615 # number of integer instructions +system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls +system.cpu.num_int_insts 1528317558 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 4441632810 # number of times the integer registers were read -system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written +system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read +system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 533262345 # number of memory refs -system.cpu.num_load_insts 384102160 # Number of load instructions +system.cpu.num_mem_refs 533262341 # number of memory refs +system.cpu.num_load_insts 384102156 # Number of load instructions system.cpu.num_store_insts 149160185 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3305213750 # Number of busy cycles +system.cpu.num_busy_cycles 3305213654 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.tagsinuse 881.608185 # Cycle average of tags in use -system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 881.608211 # Cycle average of tags in use +system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 881.608185 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 881.608211 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.430473 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.430473 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1068344296 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1068344296 # number of overall hits -system.cpu.icache.overall_hits::total 1068344296 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits +system.cpu.icache.overall_hits::total 1068344252 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses @@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 120792000 system.cpu.icache.demand_miss_latency::total 120792000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 120792000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 120792000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1068347110 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses @@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39925.373134 system.cpu.icache.overall_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.431953 # Cycle average of tags in use -system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4086.432071 # Cycle average of tags in use +system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8218697000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.431953 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8218649000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4086.432071 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997664 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997664 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530743932 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530743932 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530743932 # number of overall hits -system.cpu.dcache.overall_hits::total 530743932 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 530743928 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530743928 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530743928 # number of overall hits +system.cpu.dcache.overall_hits::total 530743928 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses @@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 53256878500 system.cpu.dcache.demand_miss_latency::total 53256878500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 53256878500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 53256878500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533262390 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533262390 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 533262386 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533262386 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533262386 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533262386 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses @@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18146.617494 system.cpu.dcache.overall_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 403150 # number of replacements -system.cpu.l2cache.tagsinuse 29113.385052 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29113.385897 # Cycle average of tags in use system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 773011530000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21035.861184 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 79.696348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7997.827520 # Average occupied blocks per requestor +system.cpu.l2cache.warmup_cycle 773011482000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21035.861795 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 79.696350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 7997.827752 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.641964 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.244074 # Average percentage of cache occupancy |