diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt | 87 |
1 files changed, 72 insertions, 15 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index c48e15266..b3396b2cb 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 1.658730 # Nu sim_ticks 1658729604000 # Number of ticks simulated final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 478704 # Simulator instruction rate (inst/s) -host_op_rate 885178 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 960288988 # Simulator tick rate (ticks/s) -host_mem_usage 252496 # Number of bytes of host memory used -host_seconds 1727.32 # Real time elapsed on the host +host_inst_rate 615589 # Simulator instruction rate (inst/s) +host_op_rate 1138293 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1234881669 # Simulator tick rate (ticks/s) +host_mem_usage 229524 # Number of bytes of host memory used +host_seconds 1343.23 # Real time elapsed on the host sim_insts 826877145 # Number of instructions simulated sim_ops 1528988757 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 37094976 # Number of bytes read from this memory -system.physmem.bytes_inst_read 148544 # Number of instructions bytes read from this memory -system.physmem.bytes_written 26349376 # Number of bytes written to this memory -system.physmem.num_reads 579609 # Number of read requests responded to by this memory -system.physmem.num_writes 411709 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 22363486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 89553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 15885275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 38248761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 148544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 36946432 # Number of bytes read from this memory +system.physmem.bytes_read::total 37094976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 148544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 148544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 26349376 # Number of bytes written to this memory +system.physmem.bytes_written::total 26349376 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2321 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 577288 # Number of read requests responded to by this memory +system.physmem.num_reads::total 579609 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 411709 # Number of write requests responded to by this memory +system.physmem.num_writes::total 411709 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 22273933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 22363486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15885275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15885275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15885275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 22273933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 38248761 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 3317459208 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,11 +91,17 @@ system.cpu.icache.demand_accesses::total 1068347110 # nu system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48641.791045 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48641.791045 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48641.791045 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -104,11 +123,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 128436000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128436000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 128436000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45641.791045 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use @@ -152,13 +177,21 @@ system.cpu.dcache.demand_accesses::total 533262390 # nu system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22005.441660 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.175798 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23627.363053 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23627.363053 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,13 +219,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 51949140000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51949140000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 51949140000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.440502 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24169.168845 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 568906 # number of replacements system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use @@ -257,18 +298,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 2518458 system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.824805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.190606 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.191637 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.313551 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.313551 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.824805 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.229223 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.229888 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.824805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.229223 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.229888 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.024190 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000.010352 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000.010352 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -303,18 +352,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23091520000 system.cpu.l2cache.overall_mshr_miss_latency::total 23184360000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.190606 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191637 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.313551 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.313551 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.229888 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.229888 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |