diff options
Diffstat (limited to 'tests/long/se/20.parser/ref/x86')
8 files changed, 667 insertions, 678 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index ea9092f76..5b84c1efd 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,28 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:30:36 -gem5 started Jul 26 2012 23:13:36 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:47:07 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ***********************info: Increasing stack size by one page. -***************info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -*********** +************************** 58924 words stored in 3784810 bytes @@ -35,6 +22,8 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's +info: Increasing stack size by one page. +info: Increasing stack size by one page. * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor * how fast the program is it * I am wondering whether to invite to the party @@ -80,4 +69,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 460506550000 because target called exit() +Exiting @ tick 460397003000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index ba1f3f77b..622f1b256 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.460507 # Number of seconds simulated -sim_ticks 460506550000 # Number of ticks simulated -final_tick 460506550000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.460397 # Number of seconds simulated +sim_ticks 460397003000 # Number of ticks simulated +final_tick 460397003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78127 # Simulator instruction rate (inst/s) -host_op_rate 144467 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43510964 # Simulator tick rate (ticks/s) -host_mem_usage 271484 # Number of bytes of host memory used -host_seconds 10583.69 # Real time elapsed on the host -sim_insts 826877144 # Number of instructions simulated -sim_ops 1528988756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 221568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 27602688 # Number of bytes read from this memory -system.physmem.bytes_read::total 27824256 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20791168 # Number of bytes written to this memory -system.physmem.bytes_written::total 20791168 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3462 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 431292 # Number of read requests responded to by this memory -system.physmem.num_reads::total 434754 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 324862 # Number of write requests responded to by this memory -system.physmem.num_writes::total 324862 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 481140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 59939838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 60420978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 481140 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 481140 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45148474 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45148474 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45148474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 481140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 59939838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 105569452 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 79363 # Simulator instruction rate (inst/s) +host_op_rate 146752 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44188751 # Simulator tick rate (ticks/s) +host_mem_usage 271496 # Number of bytes of host memory used +host_seconds 10418.87 # Real time elapsed on the host +sim_insts 826877109 # Number of instructions simulated +sim_ops 1528988699 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 220608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 27602816 # Number of bytes read from this memory +system.physmem.bytes_read::total 27823424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20793216 # Number of bytes written to this memory +system.physmem.bytes_written::total 20793216 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 431294 # Number of read requests responded to by this memory +system.physmem.num_reads::total 434741 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 324894 # Number of write requests responded to by this memory +system.physmem.num_writes::total 324894 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 479169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 59954378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 60433547 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 479169 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 479169 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45163665 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45163665 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45163665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 479169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 59954378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 105597212 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 921013101 # number of cpu cycles simulated +system.cpu.numCycles 920794007 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 225814140 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 225814140 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14312639 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 160732187 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 155963049 # Number of BTB hits +system.cpu.BPredUnit.lookups 225794462 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 225794462 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14310990 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 160522970 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 155979425 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 191714211 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1263294933 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225814140 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155963049 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 392136096 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 98589209 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 239295269 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 25132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 236819 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 183551766 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3669107 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 907433762 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.580701 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.385285 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 191744262 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1263331162 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225794462 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155979425 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 392171634 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 98591454 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 238962985 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25426 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 259827 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 183595750 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3654130 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 907193017 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.581432 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.385361 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 519759842 57.28% 57.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26004641 2.87% 60.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 29087197 3.21% 63.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 30312943 3.34% 66.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 19607781 2.16% 68.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25619101 2.82% 71.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 32643698 3.60% 75.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30879699 3.40% 78.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 193518860 21.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 519485485 57.26% 57.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25996327 2.87% 60.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 29110749 3.21% 63.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 30309742 3.34% 66.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 19641750 2.17% 68.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25638200 2.83% 71.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32631023 3.60% 75.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30872435 3.40% 78.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 193507306 21.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 907433762 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.245180 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.371636 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 253860681 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 190389456 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 329095586 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 50061804 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 84026235 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2290781397 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 907193017 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.245217 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.372002 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 253820361 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 190155093 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 329181376 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 50007304 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 84028883 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2290797520 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 84026235 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 290493220 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 45042707 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15282 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 340016370 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 147839948 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2240790840 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1987 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24419621 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 107426362 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 12159 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2887400396 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6494628948 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6493753174 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 875774 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993077484 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 894322912 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1296 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 351952477 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 540247389 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 217453734 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 211358657 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 61297047 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2143407595 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 68408 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1846659650 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1592160 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 612815347 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1231279567 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 67855 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 907433762 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.035035 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.801518 # Number of insts issued each cycle +system.cpu.rename.SquashCycles 84028883 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 290488558 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 45108603 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15221 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 340002879 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 147548873 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2240764057 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2605 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24418127 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 107087338 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 11838 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2887342076 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6494384791 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6493512354 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 872437 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993077392 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 894264684 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1272 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1264 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 351172253 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 540287564 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 217471494 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 211537272 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 61160620 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2143475674 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 68305 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1846648177 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1590040 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 612877032 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1231244444 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 67752 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 907193017 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.035563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.801610 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 248935467 27.43% 27.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 159182837 17.54% 44.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 153661987 16.93% 61.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149232137 16.45% 78.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 98738940 10.88% 89.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 59680898 6.58% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 27969436 3.08% 98.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 8976918 0.99% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1055142 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 248716450 27.42% 27.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 159225433 17.55% 44.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 153829003 16.96% 61.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 148683388 16.39% 78.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 98997552 10.91% 89.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 59757299 6.59% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 27989930 3.09% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8953405 0.99% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1040557 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 907433762 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 907193017 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2635361 18.49% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8379879 58.81% 77.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3234007 22.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2618041 18.27% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8472648 59.14% 77.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3236053 22.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2716087 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1219498090 66.04% 66.19% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2706611 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1219512996 66.04% 66.19% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.19% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.19% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.19% # Type of FU issued @@ -195,159 +195,159 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.19% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 447052191 24.21% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 177393282 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 447033831 24.21% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177394739 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1846659650 # Type of FU issued -system.cpu.iq.rate 2.005031 # Inst issue rate -system.cpu.iq.fu_busy_cnt 14249247 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007716 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4616586705 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2756248953 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1806266388 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 7764 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 302326 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 267 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1858190079 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2731 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 168174825 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1846648177 # Type of FU issued +system.cpu.iq.rate 2.005495 # Inst issue rate +system.cpu.iq.fu_busy_cnt 14326742 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007758 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4616398570 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2756384375 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1806263116 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 7583 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 297698 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 240 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1858265657 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2651 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 168095723 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 156145229 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 432412 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 271180 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 68293794 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 156185408 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 429800 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 272503 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 68311550 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7298 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 6430 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 84026235 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6572859 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1284585 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2143476003 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2866964 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 540247389 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 217453979 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5268 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 966767 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 66701 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 271180 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10086388 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5256785 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 15343173 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1818783281 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 438633483 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27876369 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 84028883 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6582029 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1299784 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2143543979 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2844739 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 540287564 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 217471735 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5098 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 982320 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 66743 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 272503 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10083086 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5258850 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 15341936 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1818766036 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 438618649 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27882141 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 610463331 # number of memory reference insts executed -system.cpu.iew.exec_branches 170879553 # Number of branches executed -system.cpu.iew.exec_stores 171829848 # Number of stores executed -system.cpu.iew.exec_rate 1.974764 # Inst execution rate -system.cpu.iew.wb_sent 1813538943 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1806266655 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1378870906 # num instructions producing a value -system.cpu.iew.wb_consumers 2933493121 # num instructions consuming a value +system.cpu.iew.exec_refs 610454199 # number of memory reference insts executed +system.cpu.iew.exec_branches 170875981 # Number of branches executed +system.cpu.iew.exec_stores 171835550 # Number of stores executed +system.cpu.iew.exec_rate 1.975215 # Inst execution rate +system.cpu.iew.wb_sent 1813520986 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1806263356 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1378693447 # num instructions producing a value +system.cpu.iew.wb_consumers 2933323666 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.961174 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.470044 # average fanout of values written-back +system.cpu.iew.wb_rate 1.961637 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.470011 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 614512471 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 826877109 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1528988699 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 614579352 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14337883 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823407527 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.856904 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.319659 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14336742 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 823164134 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.857453 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.320209 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 305105182 37.05% 37.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 205650111 24.98% 62.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 74228668 9.01% 71.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 96597559 11.73% 82.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29968597 3.64% 86.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28751826 3.49% 89.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15821579 1.92% 91.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11746400 1.43% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 55537605 6.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 305087340 37.06% 37.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 205283379 24.94% 62.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 74494797 9.05% 71.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 96404931 11.71% 82.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29976642 3.64% 86.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28775074 3.50% 89.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15838255 1.92% 91.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11740263 1.43% 93.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 55563453 6.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823407527 # Number of insts commited each cycle -system.cpu.commit.committedInsts 826877144 # Number of instructions committed -system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 823164134 # Number of insts commited each cycle +system.cpu.commit.committedInsts 826877109 # Number of instructions committed +system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 533262345 # Number of memory references committed -system.cpu.commit.loads 384102160 # Number of loads committed +system.cpu.commit.refs 533262341 # Number of memory references committed +system.cpu.commit.loads 384102156 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 149758588 # Number of branches committed +system.cpu.commit.branches 149758583 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. +system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 55537605 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 55563453 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2911371149 # The number of ROB reads -system.cpu.rob.rob_writes 4371143864 # The number of ROB writes -system.cpu.timesIdled 309440 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13579339 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 826877144 # Number of Instructions Simulated -system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated -system.cpu.cpi 1.113845 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.113845 # CPI: Total CPI of All Threads -system.cpu.ipc 0.897791 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.897791 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4004246874 # number of integer regfile reads -system.cpu.int_regfile_writes 2286313998 # number of integer regfile writes -system.cpu.fp_regfile_reads 266 # number of floating regfile reads -system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 1001920728 # number of misc regfile reads -system.cpu.icache.replacements 5588 # number of replacements -system.cpu.icache.tagsinuse 1044.044381 # Cycle average of tags in use -system.cpu.icache.total_refs 183312403 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7204 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25445.919350 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2911168732 # The number of ROB reads +system.cpu.rob.rob_writes 4371280103 # The number of ROB writes +system.cpu.timesIdled 309541 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13600990 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 826877109 # Number of Instructions Simulated +system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated +system.cpu.cpi 1.113580 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.113580 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898004 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898004 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4004208844 # number of integer regfile reads +system.cpu.int_regfile_writes 2286339718 # number of integer regfile writes +system.cpu.fp_regfile_reads 238 # number of floating regfile reads +system.cpu.fp_regfile_writes 2 # number of floating regfile writes +system.cpu.misc_regfile_reads 1001924846 # number of misc regfile reads +system.cpu.icache.replacements 5564 # number of replacements +system.cpu.icache.tagsinuse 1044.277661 # Cycle average of tags in use +system.cpu.icache.total_refs 183360161 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7185 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25519.855393 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1044.044381 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.509787 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.509787 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 183329342 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 183329342 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 183329342 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 183329342 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 183329342 # number of overall hits -system.cpu.icache.overall_hits::total 183329342 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 222424 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 222424 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 222424 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 222424 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 222424 # number of overall misses -system.cpu.icache.overall_misses::total 222424 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1554709500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1554709500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1554709500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1554709500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1554709500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1554709500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 183551766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 183551766 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 183551766 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 183551766 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 183551766 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 183551766 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001212 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001212 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001212 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001212 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001212 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001212 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6989.845970 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6989.845970 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6989.845970 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6989.845970 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6989.845970 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6989.845970 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1044.277661 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.509901 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.509901 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 183377049 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 183377049 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 183377049 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1530978500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1530978500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 183595750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 183595750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 183595750 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 183595750 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 183595750 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 183595750 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001191 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001191 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001191 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001191 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001191 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001191 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7000.326930 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 7000.326930 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 7000.326930 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 7000.326930 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 7000.326930 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 7000.326930 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -356,94 +356,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1671 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1671 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1671 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1671 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1671 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1671 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 220753 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 220753 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 220753 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 220753 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 220753 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 220753 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 807012500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 807012500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 807012500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 807012500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 807012500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 807012500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001203 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001203 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001203 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3655.726083 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3655.726083 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3655.726083 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3655.726083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3655.726083 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3655.726083 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1667 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1667 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1667 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1667 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1667 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1667 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 217034 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 217034 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 217034 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 217034 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 217034 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 217034 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 795818000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 795818000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 795818000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 795818000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 795818000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 795818000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001182 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001182 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001182 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001182 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3666.789535 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3666.789535 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3666.789535 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3666.789535 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3666.789535 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3666.789535 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2526911 # number of replacements -system.cpu.dcache.tagsinuse 4087.001481 # Cycle average of tags in use -system.cpu.dcache.total_refs 415013959 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2531007 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.971873 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2119650000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.001481 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997803 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997803 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 266164816 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 266164816 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148172858 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148172858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 414337674 # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 163.995484 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2118352000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.012033 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997806 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997806 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 266229970 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 266229970 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148176522 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148176522 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 414406492 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414406492 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414406492 # 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number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55557310000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55557310000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55557310000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55557310000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 268882957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 268882957 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 417977527 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 417977527 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 417977527 # 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miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008708 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008708 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13843.841871 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13843.841871 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19229.820842 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 19229.820842 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15304.837311 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15304.837311 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15304.837311 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15304.837311 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006595 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006595 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008699 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008699 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008699 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008699 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13839.328651 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13839.328651 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19154.369464 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 19154.369464 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15276.989968 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15276.989968 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15276.989968 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15276.989968 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -452,144 +452,144 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2302631 # number of writebacks -system.cpu.dcache.writebacks::total 2302631 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 892307 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 892307 # 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average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16083.027367 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10321.543492 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10321.543492 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10321.543492 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10321.543492 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2302737 # number of writebacks +system.cpu.dcache.writebacks::total 2302737 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 892793 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 892793 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3022 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3022 # 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average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49.799051 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49.799051 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.569674 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.569674 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35087.666089 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.529619 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34298.860880 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35087.666089 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.529619 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34298.860880 # average overall miss latency +system.cpu.l2cache.ReadReq_accesses::total 1766511 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2302737 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2302737 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 209807 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 209807 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771643 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771643 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 7110 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2531044 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2538154 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7110 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2531044 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2538154 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.484810 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.126258 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.127701 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.993956 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.993956 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.271094 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.271094 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.484810 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.170415 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.171295 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.484810 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.170415 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.171295 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35059.326951 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34323.585377 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34334.827658 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 50.688360 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 50.688360 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.697918 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.697918 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35059.326951 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.115801 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34298.198448 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35059.326951 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.115801 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34298.198448 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -598,60 +598,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 324862 # number of writebacks -system.cpu.l2cache.writebacks::total 324862 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3462 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222130 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 225592 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 212243 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 212243 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209197 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 209197 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3462 # number of demand (read+write) MSHR misses +system.cpu.l2cache.writebacks::writebacks 324894 # number of writebacks +system.cpu.l2cache.writebacks::total 324894 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3447 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222139 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 225586 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 208539 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 208539 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209188 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 209188 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3447 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 431327 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 434789 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 434774 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3447 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 431327 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 434789 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110501000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6934646999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7045147999 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6580894500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6580894500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6486675500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6486675500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110501000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13421322499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13531823499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110501000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13421322499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13531823499 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.484399 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126253 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127702 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994103 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994103 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.484399 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170417 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.171301 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.484399 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170417 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.171301 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31918.255344 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31218.867325 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31229.600336 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31006.414817 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31006.414817 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31007.497717 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31007.497717 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31918.255344 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31116.351397 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31122.736543 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31918.255344 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31116.351397 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31122.736543 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 434774 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109944000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6934594999 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7044538999 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6467053500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6467053500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6486625500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6486625500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109944000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13421220499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13531164499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109944000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13421220499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13531164499 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.484810 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126258 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127701 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993956 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993956 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271094 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271094 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.484810 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170415 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.171295 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.484810 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170415 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.171295 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31895.561358 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31217.368400 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31227.731326 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31011.242501 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31011.242501 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.592749 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31008.592749 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31895.561358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31116.114917 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31122.294569 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31895.561358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31116.114917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31122.294569 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index 8e0e263be..631aee4c4 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -120,8 +120,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +width=8 +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 337e5053a..2e1cac91e 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:38:11 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:52:16 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -69,4 +69,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 885229360000 because target called exit() +Exiting @ tick 885229327000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index a8445ed5c..84b45e732 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.885229 # Number of seconds simulated -sim_ticks 885229360000 # Number of ticks simulated -final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 885229327000 # Number of ticks simulated +final_tick 885229327000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1285236 # Simulator instruction rate (inst/s) -host_op_rate 2376545 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1375933868 # Simulator tick rate (ticks/s) -host_mem_usage 220604 # Number of bytes of host memory used -host_seconds 643.37 # Real time elapsed on the host -sim_insts 826877145 # Number of instructions simulated -sim_ops 1528988757 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 8546776872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2285655660 # Number of bytes read from this memory -system.physmem.bytes_read::total 10832432532 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 8546776872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 8546776872 # Number of instructions bytes read from this memory +host_inst_rate 1279506 # Simulator instruction rate (inst/s) +host_op_rate 2365950 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1369799774 # Simulator tick rate (ticks/s) +host_mem_usage 228100 # Number of bytes of host memory used +host_seconds 646.25 # Real time elapsed on the host +sim_insts 826877110 # Number of instructions simulated +sim_ops 1528988700 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2285655656 # Number of bytes read from this memory +system.physmem.bytes_read::total 10832432176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 8546776520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8546776520 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 991849460 # Number of bytes written to this memory system.physmem.bytes_written::total 991849460 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1068347109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 384102189 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1452449298 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1068347065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 384102185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1452449250 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 149160201 # Number of write requests responded to by this memory system.physmem.num_writes::total 149160201 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9654872803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2581992604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12236865406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9654872803 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9654872803 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1120443475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1120443475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9654872803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3702436078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13357308881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 9654872765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2581992695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12236865460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9654872765 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9654872765 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1120443516 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1120443516 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9654872765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13357308977 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 1770458721 # number of cpu cycles simulated +system.cpu.numCycles 1770458655 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826877145 # Number of instructions committed -system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.committedInsts 826877110 # Number of instructions committed +system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317615 # number of integer instructions +system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls +system.cpu.num_int_insts 1528317558 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 4441632810 # number of times the integer registers were read -system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written +system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read +system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 533262345 # number of memory refs -system.cpu.num_load_insts 384102160 # Number of load instructions +system.cpu.num_mem_refs 533262341 # number of memory refs +system.cpu.num_load_insts 384102156 # Number of load instructions system.cpu.num_store_insts 149160185 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1770458721 # Number of busy cycles +system.cpu.num_busy_cycles 1770458655 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index 2d97cc0b1..5307ccc0b 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing +cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr @@ -202,7 +202,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index 1335d3658..d712433e8 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 13:47:25 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 19:03:12 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -69,4 +69,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1652606875000 because target called exit() +Exiting @ tick 1652606827000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index ae8bc7b58..9139f6ef0 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.652607 # Number of seconds simulated -sim_ticks 1652606875000 # Number of ticks simulated -final_tick 1652606875000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1652606827000 # Number of ticks simulated +final_tick 1652606827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 673883 # Simulator instruction rate (inst/s) -host_op_rate 1246085 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1346830511 # Simulator tick rate (ticks/s) -host_mem_usage 232676 # Number of bytes of host memory used -host_seconds 1227.03 # Real time elapsed on the host -sim_insts 826877145 # Number of instructions simulated -sim_ops 1528988757 # Number of ops (including micro ops) simulated +host_inst_rate 715148 # Simulator instruction rate (inst/s) +host_op_rate 1322389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1429304042 # Simulator tick rate (ticks/s) +host_mem_usage 236556 # Number of bytes of host memory used +host_seconds 1156.23 # Real time elapsed on the host +sim_insts 826877110 # Number of instructions simulated +sim_ops 1528988700 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 27359872 # Number of bytes read from this memory system.physmem.bytes_read::total 27483456 # Number of bytes read from this memory @@ -24,54 +24,54 @@ system.physmem.num_reads::total 429429 # Nu system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 74781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 16555584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16630365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 16555585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16630366 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 74781 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 74781 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12530796 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12530796 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12530796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 12530797 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12530797 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12530797 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 74781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 16555584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 16555585 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 29161162 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3305213750 # number of cpu cycles simulated +system.cpu.numCycles 3305213654 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826877145 # Number of instructions committed -system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses +system.cpu.committedInsts 826877110 # Number of instructions committed +system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317615 # number of integer instructions +system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls +system.cpu.num_int_insts 1528317558 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 4441632810 # number of times the integer registers were read -system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written +system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read +system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 533262345 # number of memory refs -system.cpu.num_load_insts 384102160 # Number of load instructions +system.cpu.num_mem_refs 533262341 # number of memory refs +system.cpu.num_load_insts 384102156 # Number of load instructions system.cpu.num_store_insts 149160185 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3305213750 # Number of busy cycles +system.cpu.num_busy_cycles 3305213654 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.tagsinuse 881.608185 # Cycle average of tags in use -system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 881.608211 # Cycle average of tags in use +system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 881.608185 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 881.608211 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.430473 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.430473 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1068344296 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1068344296 # number of overall hits -system.cpu.icache.overall_hits::total 1068344296 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits +system.cpu.icache.overall_hits::total 1068344252 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses @@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 120792000 system.cpu.icache.demand_miss_latency::total 120792000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 120792000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 120792000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1068347110 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses @@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39925.373134 system.cpu.icache.overall_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.431953 # Cycle average of tags in use -system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4086.432071 # Cycle average of tags in use +system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8218697000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.431953 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8218649000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4086.432071 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997664 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997664 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530743932 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530743932 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530743932 # number of overall hits -system.cpu.dcache.overall_hits::total 530743932 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 530743928 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530743928 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530743928 # number of overall hits +system.cpu.dcache.overall_hits::total 530743928 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses @@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 53256878500 system.cpu.dcache.demand_miss_latency::total 53256878500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 53256878500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 53256878500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533262390 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533262390 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 533262386 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533262386 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533262386 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533262386 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses @@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18146.617494 system.cpu.dcache.overall_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 403150 # number of replacements -system.cpu.l2cache.tagsinuse 29113.385052 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29113.385897 # Cycle average of tags in use system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 773011530000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21035.861184 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 79.696348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7997.827520 # Average occupied blocks per requestor +system.cpu.l2cache.warmup_cycle 773011482000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21035.861795 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 79.696350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 7997.827752 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.641964 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.244074 # Average percentage of cache occupancy |