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-rw-r--r--tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini39
-rwxr-xr-xtests/long/se/20.parser/ref/x86/linux/o3-timing/simout8
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt27
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini10
-rwxr-xr-xtests/long/se/20.parser/ref/x86/linux/simple-atomic/simout4
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini27
-rwxr-xr-xtests/long/se/20.parser/ref/x86/linux/simple-timing/simout4
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt210
9 files changed, 172 insertions, 167 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index b3fdd5038..ab5e0012f 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -514,9 +519,9 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/x86/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/gem5/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
index 1c86b657b..c205806bb 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:20:54
-gem5 started Jan 4 2013 22:32:47
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 16:49:19
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index 93e747e50..2768ee697 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.434475 # Nu
sim_ticks 434474519000 # Number of ticks simulated
final_tick 434474519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 38128 # Simulator instruction rate (inst/s)
-host_op_rate 70503 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 20033995 # Simulator tick rate (ticks/s)
-host_mem_usage 425632 # Number of bytes of host memory used
-host_seconds 21686.86 # Real time elapsed on the host
+host_inst_rate 63257 # Simulator instruction rate (inst/s)
+host_op_rate 116969 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33237666 # Simulator tick rate (ticks/s)
+host_mem_usage 473612 # Number of bytes of host memory used
+host_seconds 13071.75 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988700 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 208768 # Number of bytes read from this memory
@@ -192,18 +192,19 @@ system.physmem.writeRowHits 151214 # Nu
system.physmem.readRowHitRate 88.35 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 51.49 # Row buffer hit rate for writes
system.physmem.avgGap 639455.00 # Average gap between requests
+system.cpu.branchPred.lookups 215014033 # Number of BP lookups
+system.cpu.branchPred.condPredicted 215014033 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 13139181 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 150598539 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 147901505 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 98.209123 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 868949039 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 215014033 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 215014033 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 13139181 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 150598539 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 147901505 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 180614847 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1193262475 # Number of instructions fetch has processed
system.cpu.fetch.Branches 215014033 # Number of branches that fetch encountered
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
index 5fcf89c74..43e0511db 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -15,6 +15,7 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -83,6 +86,9 @@ int_master=system.membus.slave[5]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
index cda645856..5586bce3b 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-ato
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:35:29
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 16:35:03
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 2fe2ac232..c7a71973c 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu
sim_ticks 885229327500 # Number of ticks simulated
final_tick 885229327500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 941243 # Simulator instruction rate (inst/s)
-host_op_rate 1740465 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1007666185 # Simulator tick rate (ticks/s)
-host_mem_usage 271920 # Number of bytes of host memory used
-host_seconds 878.49 # Real time elapsed on the host
+host_inst_rate 978383 # Simulator instruction rate (inst/s)
+host_op_rate 1809140 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1047426540 # Simulator tick rate (ticks/s)
+host_mem_usage 293648 # Number of bytes of host memory used
+host_seconds 845.15 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
index bfee22e10..32281f28e 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -63,21 +66,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -102,21 +100,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -133,6 +126,9 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
@@ -152,21 +148,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
index 26674a0c2..f781a0970 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:51:49
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:08:30
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index c29684f08..532eed382 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu
sim_ticks 1647872848000 # Number of ticks simulated
final_tick 1647872848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 488671 # Simulator instruction rate (inst/s)
-host_op_rate 903607 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 973865405 # Simulator tick rate (ticks/s)
-host_mem_usage 280376 # Number of bytes of host memory used
-host_seconds 1692.10 # Real time elapsed on the host
+host_inst_rate 579757 # Simulator instruction rate (inst/s)
+host_op_rate 1072035 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1155389699 # Simulator tick rate (ticks/s)
+host_mem_usage 301076 # Number of bytes of host memory used
+host_seconds 1426.25 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory
@@ -135,106 +135,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2514362 # number of replacements
-system.cpu.dcache.tagsinuse 4086.415786 # Cycle average of tags in use
-system.cpu.dcache.total_refs 530743929 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 8211723000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4086.415786 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 530743929 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 530743929 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 530743929 # number of overall hits
-system.cpu.dcache.overall_hits::total 530743929 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
-system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 533262387 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 533262387 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 533262387 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 533262387 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
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-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
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-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency
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-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 348459 # number of replacements
system.cpu.l2cache.tagsinuse 29286.402681 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks.
@@ -373,5 +273,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------